EP0694886B1 - Electronic franking system with a rechargeable operating programm in a flash memory - Google Patents

Description

The invention relates generally to field of postage machines which are now widely used in shipping offices of corporate mail.

It relates more particularly to a system electronic postage including a microprocessor connected by an address bus and a bus data to a non-volatile memory circuit in which is recorded an operating program (see EP-A-0 605 313).

By operating program is meant a program intended for the control of the microprocessor in order to obtain a desired operation of it. It can be used in particular with amount accounting information management postage. This information includes generally the amount of funds available in the system (this amount being decremented with each transaction postage) as well as the cumulative amount of postage (this amount is incremented each time franking operation). This information is maintained in the so-called top-down and bottom-up registers in non-volatile memory backed up by battery. Most franking system has two memories not battery-backed birds in which are duplicate the top and bottom registers.

Such a franking system is generally mounted inside a sealed enclosure. In the known postage systems, the program operating system is saved in a memory of the type EPROM. Such memory requires exposure to rays ultra violet to be erased then reprogrammed in order to change the operating program. To achieve this function, the circuit or EPROM memory box must be mounted in the franking system on a support so as to be removable. The presence of such a support increases the cost of the postage system. It would be possible to record the operating program in a RAM type read / write memory backed up by drums. But such a solution increases the cost even more of the franking system. Furthermore, this arrangement would cause complications to ensure the level of program data security required by Postal administrations. In other words, it is not planned today to change, in situ in a system electronic franking, the operating program stored in a non-volatile memory circuit, i.e. without removing the memory circuit from the sealed enclosure containing the franking system.

The object of the invention is to propose a system electronic postage meter having a circuit of memory arranged in such a way as to allow a change in situ of the operating program recorded in the circuit of memory without penalizing the cost of the system and without affecting its security level.

To this end, the invention relates to a system electronic postage characterized in that the memory circuit is of the flash memory type having a memory space divided into a plurality of sectors selectively addressable from the address bus, in this that there is an address decoding circuit between the address bus and a memory circuit terminal authorizing or prohibiting writing to memory, this circuit of decoding being arranged so that the microprocessor is prevented from writing to a first memory sector in which the operating program is saved when the decoding circuit detects the presence of a signal control set to a logical first level and the microprocessor is allowed to write to said first memory sector when the decoding circuit detects the presence of the control signal set to a second level logic, and that there is a loading program saved in a second protected memory sector, by programmed configuration of the memory circuit, against all write access, this loading program being planned to control the microprocessor in such a way that he establish a dialogue with another processor in view load a new operating program, provided by this other processor, instead of the operating program already saved in said first memory sector when the control signal is set to the second level logic.

Non-volatile memory circuit technology from flash type is starting to appear on the market and is of interest for a franking system electronic postal. Such a memory circuit has space memory organized into sectors of fixed size selectively erasable by a microprocessor control. The sectors of such memory are otherwise likely to be selectively protected against write or write access erasure. This protection is done by configuring the flash memory on a programming bench. This protection can therefore be performed before mounting the memory circuit flash directly on a printed circuit board. Such non-volatile memory circuit may be suitable for recording the operating program of a machine postage because it has a memory space important enough.

Decoding circuit prevents changes untimely operating program in memory flash, for example in the event of a malfunction of the microprocessor, and contributes to the security of the system.

It is even possible to download a new one operating program in flash memory if a system telecommunications is provided between the microprocessor of the postage system and that other processor.

According to a particularly simple embodiment to implement, this control signal comes from a line conductive connected to a current source by a pin removable. This way when the spindle is interposed between the decoding circuit and the current source, the control signal is set to its first logical state. When this pin is removed, the control signal changes of logical state which makes the first sector of memory containing the operating program accessible in erasing and writing by the microprocessor which can then reload a new operating program.

To prevent unauthorized loading of a new one operating program in the first sector of the memory, it is expected that the microprocessor, the circuit memory, address decoding circuit and pin be placed inside a sealed enclosure. This way, only the manufacturer can load a new one. operating program in the first sector of the memory.

Other features and advantages will emerge from the following description of exemplary embodiments of the invention made with reference to the drawings.

Figure 1 shows in schematic form a first embodiment of the franking system.

Figure 2 illustrates the organization into sectors of the flash memory.

In Figure 1, the franking system includes a microprocessor 1 having seventeen address bits A0-A16 and eight data bits D0-D7, for example the circuit integrated known as "80C166" or the circuit integrated known under the reference "ST10". He still understands a non-volatile flash memory circuit 2, for example the integrated circuit known under the reference "29F10PL". This memory has a capacity of 128 Kilo bytes divided into eight memory sectors of 16 Kilo bytes each. These eight sectors are designated by S1 to S8 in Figure 2.

The data inputs / outputs D0 to D7 of the memory 2 are connected to the data inputs / outputs microprocessor 1 through a bus data 10 comprising eight lines of data. The entrees of addresses A0 to A16 of memory circuit 2 are connected to corresponding address outputs of microprocessor 1 to across an address bus 11 comprising seventeen lines addresses.

The memory circuit 2 also has an input of OE read command, WR write command input and a CE box selection input. The entrance to selection of CE box permanently receives a signal 0 volt electric so the memory circuit 2 receives all read and write commands from microprocessor 1.

The microprocessor 1 also has an output of RD read command, a write command output WR, a reserved input of a CHPRG control signal, and a serial RXD1 input and TXD1 output port.

RD microprocessor read command output is connected to the RD read command input of the circuit of memory. The serial RXD1 input and TXD1 output of the microprocessor are connected to a connector 5 through a control bus 12 comprising several lines of orders.

In addition, the microprocessor input for receive the CHPRG control signal is connected through the control bus 12 and a removable pin 4 (under the shape of a jumper) to a current source delivering a 5 volts electrical signal corresponding to a level logic equal to 1.

There is also an address decoder 3 having a output connected to the WE write command input of the memory circuit 2.

The address decoder 3 includes an AND gate reverser 31 with three inputs to receive respectively the CHPRG control signal and signals from the outputs of most significant addresses A15 and A16 of microprocessor. These last two signals are taken directly on address bus 11. It also includes a reversing single door 32 which receives a control signal write from WR write command output of microprocessor 1. It includes yet another AND gate reverser 33 having a first input connected to the output of gate 31 and two other inputs connected to the output of door 32. The output of door 33 is connected to the input write command WR of memory circuit 2.

The microprocessor 1, the memory circuit 2, the address decoder 3 and pin 4 are enclosed in a enclosure 20 comprising a hatch 21 giving access from the outside of the enclosure on pin 4. The hatch closes normally the enclosure and is sealed to prevent any unauthorized access to the interior of the enclosure by a user. As shown in Figure 1, the connector 5 is freely accessible from outside the enclosure 20. However, it could also be locked inside of the enclosure so as to be accessible only when the hatch 21 is open.

The set of circuits 1,2,3,4,5 is mounted on one or printed circuit boards not shown, the terminals memory circuit 2 can be directly soldered on a printed circuit board.

The memory space of memory 2 is divided into a plurality of memory sectors of identical capacity, in the occurrence eight sectors S1 to S8 of 16 Kilo bytes each.

A loading program is saved in the sector S1. In addition, the S1 sector is protected against erasing or writing, after the program load recorded there and before mounting the circuit memory 2 directly on the printed circuit board. Such protection is achieved using a device specific memory programming known per se.

A machine operating program postage is recorded in sectors S7 and S8 from memory. Sectors S2 to S6 are left free for the recording of other data.

These two sectors are accessible by the microprocessor through address bits A15 and A16.

During normal system operation , the address decoder 3 prevents access writing the microprocessor in sectors S7 and S8 of memory of the fact that the combination of the input signals of door 31 forces the output of the address decoder to a logic level equal to 1 and that this logic level is that required to inhibit WR write command input memory circuit 2.

Consequently, the address decoder 3 ensures that the operating program saved in the S7 and S8 memory is not affected by a malfunction microprocessor for example.

In addition, when the system is powered up postage, the microprocessor accesses the first bytes saved in sector S1 of the memory which constitute the beginning of the loading program.

This loading program is first designed to test during the start of its execution the logic level CHPRG signal received by the microprocessor. If this signal to a logic level equal to 1, the loading program launches execution of the operating program at the same time as stops. It is therefore the normal framework for operation of the franking system.

Now if pin 4 is removed from the circuit electric between the +5 volts source and the decoder of addresses 3, the CHPRG signal will have a logic level equal to 0. When the CHPRG signal has a logic level equal to 0, the address decoder 3 lets through the control signal WR writing from the microprocessor so that authorize the microprocessor to write in the S7 sectors and S8 from memory.

The loading program, upon signal detection CHPRG at a logic level equal to 0, command the microprocessor in such a way that it first erases the contents of sectors S7 and S8 and then that it establishes a communication with another processor connected to the ports RXD1 and TXD1 serial input / output via connector 5 to load a new one in situ operating program in sectors S7 and S8, this new operating program from the other processor. After loading the new program the loading program can stop and block the functioning of the system postage. System power postage should be cut. At this time, the spindle 4 must be replaced again so that the CHPRG signal level is equal to 1. Then the machine meter is turned back on and the program loading as indicated above will launch the execution of the new operating program.

As a variant, the signal CHPRG can come from directly from the microprocessor which is controlled in such a way so as to change the logic level of the CHPRG signal to response to a coded message obtained from the port of entry RXD1 series. In this variant, the microprocessor of the franking system is connected, for example by a telephone line, at a fleet management center postage systems.

Claims (3)

1. An electronic postal franking system comprising a microprocessor (1) which is connected by an address bus (11) and a data bus (10) to a nonvolatile memory circuit (2) in which is stored an operation program, characterised in that the memory circuit is of the flash memory type, having a memory space divided into a plurality of sectors (S1-S8) which are selectively addressable from the address bus, and in that an address-decoding circuit (3) is provided between the address bus and a terminal (WE) of the memory circuit, permitting or preventing writing in the memory, this decoding circuit being arranged in a manner such that the microprocessor is prevented from writing in a first sector (S7, S8) of the memory, in which first sector the operation program is stored, when the decoding circuit detects the presence of a control signal (CHPRG) set at a first logic level, and the microprocessor is permitted to write in the said first sector of the memory when the decoding circuit detects the presence of the control signal set at a second logic level, and in that there is provided a loading program stored in a second sector (S1) of the memory, which second sector is protected, by programmed configuration of the memory circuit, against all written access, this loading program being provided in order to control the microprocessor in a manner such that it sets up a dialogue with another processor with a view to loading a new operation program, provided by this other processor, in the place of the operation program already stored in the said first sector of the memory, when the control signal is set at the second logic level.
2. The system according to claim 1, in which the control signal (CHPRG) comes from a conductive line which is connected to a current source by a movable pin (4).
3. The system according to claim 2, in which the microprocessor (1), the memory circuit (2), the address-decoding circuit (3) and the movable pin (4) are placed inside a sealed enclosure (20).

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