EP0660042B1 - Circuit de couplage de lignes sous tension avec un micro-processeur - Google Patents

Circuit de couplage de lignes sous tension avec un micro-processeur Download PDF

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Publication number
EP0660042B1
EP0660042B1 EP93810908A EP93810908A EP0660042B1 EP 0660042 B1 EP0660042 B1 EP 0660042B1 EP 93810908 A EP93810908 A EP 93810908A EP 93810908 A EP93810908 A EP 93810908A EP 0660042 B1 EP0660042 B1 EP 0660042B1
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EP
European Patent Office
Prior art keywords
voltage
circuit
switch devices
call
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP93810908A
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German (de)
English (en)
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EP0660042A1 (fr
Inventor
Mirko Bulinsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Electrowatt Technology Innovation AG
Original Assignee
Landis and Gyr Technology Innovation AG
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Publication date
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Priority to DE59300430T priority Critical patent/DE59300430D1/de
Priority to EP93810908A priority patent/EP0660042B1/fr
Publication of EP0660042A1 publication Critical patent/EP0660042A1/fr
Application granted granted Critical
Publication of EP0660042B1 publication Critical patent/EP0660042B1/fr
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Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F23—COMBUSTION APPARATUS; COMBUSTION PROCESSES
    • F23N—REGULATING OR CONTROLLING COMBUSTION
    • F23N5/00—Systems for controlling combustion
    • F23N5/24—Preventing development of abnormal or undesired conditions, i.e. safety arrangements
    • F23N5/242—Preventing development of abnormal or undesired conditions, i.e. safety arrangements using electronic means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
    • H01H9/16—Indicators for switching condition, e.g. "on" or "off"
    • H01H9/167—Circuits for remote indication
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F23—COMBUSTION APPARATUS; COMBUSTION PROCESSES
    • F23N—REGULATING OR CONTROLLING COMBUSTION
    • F23N2223/00—Signal processing; Details thereof
    • F23N2223/08—Microprocessor; Microcomputer
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F23—COMBUSTION APPARATUS; COMBUSTION PROCESSES
    • F23N—REGULATING OR CONTROLLING COMBUSTION
    • F23N2223/00—Signal processing; Details thereof
    • F23N2223/20—Opto-coupler
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F23—COMBUSTION APPARATUS; COMBUSTION PROCESSES
    • F23N—REGULATING OR CONTROLLING COMBUSTION
    • F23N2227/00—Ignition or checking
    • F23N2227/12—Burner simulation or checking
    • F23N2227/16—Checking components, e.g. electronic

Definitions

  • the invention relates to a circuit arrangement for coupling live, in particular live, lines to a microprocessor, the switching states of first switching devices arranged in live signal lines being supplied to the microprocessor via an interface.
  • Circuit arrangements of this type are used, for example, for the control and monitoring of the oil burner and the ignition device of oil firing systems, the microprocessor evaluating the information supplied via line voltage-carrying signal lines and sending the corresponding commands back.
  • a control device for oil burners in which information about the switching states of relay and sensor contacts is transmitted to a microprocessor by means of an amplifier.
  • Each amplifier is connected on the output side to an input of the microprocessor, so that the microprocessor must have a number of inputs corresponding to the number of amplifiers.
  • the use of a relatively large number of amplifiers for the transmission of information causes high costs which, since most of the amplifiers are connected to the microprocessor via optocouplers, further increase them. Since a minimum current is required to query the signaling contacts, increased power loss must be expected with this type of information transmission.
  • mains voltage-carrying lines are connected to an interrogation unit of an AC voltage detector via optocouplers.
  • the lines are each connected to the optocoupler via a low-pass filter, which consists of a resistor and a capacitor connected in series with it.
  • the switching states of the AC switches are queried and saved via the lines.
  • the switching states are compared with a target state - open or closed - and then a switch state signal is formed, which contains at least one piece of information - error or no error - in total for all AC switches that occur.
  • the invention has for its object a circuit arrangement to propose of the type mentioned at the outset which works reliably and safely with minimal power loss.
  • second switching devices connected in series with the first switching devices are provided in the signaling lines, which are switched sequentially into a conductive state for the purpose of querying the switching states of the first switching devices.
  • a positive half-wave of an AC voltage is supplied and the first and second switching devices are closed, a current flows via a line common to all the signal lines, a load element and, optionally, a Zener diode to a ground connection.
  • a voltage of the common line and a voltage of a power supply circuit dependent thereon are each compared with a reference voltage.
  • a pulse is generated which characterizes the ON state of the currently queried signal line and which is fed to the microprocessor.
  • ML indicates signal lines which are connected on the one hand to a phase P of an AC network and on the other hand to an interface KRA in the form of an integrated circuit.
  • First switching devices 1 in the form of relay or sensor contacts, as well as second switching devices 2 connected in series therewith, are provided in the signaling lines ML and are described in more detail below with reference to FIG. 2.
  • Two of the first switching devices 1 in FIG. 1 serve as sensor or signaling contacts, as can be implemented, for example, with bimetal switches, while a further first switching device 1 serves to actuate a load L, which is connected to the ground M of the AC network.
  • a power supply circuit 3 is connected to phase P of the AC network and the integrated circuit KRA.
  • the signal lines ML are connected via the second switching devices 2 to a common line fvl which is connected to the power supply circuit 3, the integrated circuit KRA and, as described in more detail below with reference to FIG. 2, to ground.
  • 4 denotes a microprocessor which is connected to the integrated circuit KRA via two optocouplers 5, 6, the optocouplers 5, 6 being assigned opposite signal transmission directions.
  • the second switching devices provided in the signaling lines ML are 2 low-voltage switching fet's, the drain electrodes with the relevant signaling lines, the source electrodes with the line fvl and common to all the signaling lines the gate electrodes are connected to associated outputs of the integrated circuit KRA.
  • Rectifier diodes 7 are arranged in the signaling lines ML between the first switching devices 1 (FIG. 1) and the second switching devices 2.
  • the common line fvl is connected on the one hand via a load element Ld and advantageously a Zener diode HVZ to the ground connection M and on the other hand to a first connection vss of the integrated circuit KRA.
  • the Zener voltage of the Zener diode HVZ is chosen so large in accordance with the peak value of the voltage of the phase P that 2 low-voltage fet's can be used as second switching devices.
  • the load element Ld can be an ohmic resistance, the value of which is dimensioned such that the peak value of the current flowing through the load element Ld is in the range of the desired load current for the first switching devices 1.
  • the power supply circuit 3 has a diode 8 which is connected to the anode at the phase P of the AC network and which is connected in series with a resistor 9.
  • the resistor 9 is connected to the cathode of a further Zener diode 10 and a second connection vdd of the integrated circuit KRA.
  • a capacitor 11 is connected in parallel with the further Zener diode 10.
  • the anode of the Zener diode 10 is connected to the common line fvl and the connection vss, the connection vss representing the negative pole and the connection vdd the positive pole of the power supply circuit 3.
  • a battery could also serve as the power supply circuit 3.
  • Reference numeral 12 designates a reference voltage circuit which has a parallel connection, in the one branch of which a first resistor 13 and the other branch of which a diode 14 and a capacitor 15 are arranged.
  • a second resistor 16 is connected to the connection between the diode 14 and the capacitor 15 and is connected to an input of the integrated circuit KRA.
  • the parallel connection is connected on the one hand via a third resistor 17 to the phase P of the AC network and on the other hand to the ground connection M.
  • a comparison circuit 20 arranged within the integrated circuit KRA consists of two diodes 21, 22 connected in series.
  • the cathode of one diode 21 and the anode of the other diode 22 are connected via a node 23 to the second resistor 16 of the reference voltage circuit 12.
  • the anode of one diode 21 is connected to the common line fvl and the negative pole of the power supply circuit 3 via the connection vss, and the cathode of the other diode 22 is connected to the positive pole of the power supply circuit 3 via the connection vdd.
  • 20 pulses DI are generated by means of the comparison circuit, which occur at the node 23 and which are supplied to the microprocessor 4.
  • the inputs of the buffers 24 are, for example, with a ring counter Connection so that the second switching devices 2 can be switched into a conductive state one after the other in time.
  • Us denotes a voltage occurring at the node 23 of the comparison circuit 20, the upper level of which corresponds to the voltage Vd and the lower level of which corresponds to the voltage Vs.
  • the two levels are levels of a pulse DI which occurs in the region of a positive half-wave when the switching state "ON" of a signal line ML.
  • the switching lines ML can be assigned further switching devices 25 in the form of switching fet's.
  • the drain electrodes are connected to a DC voltage source G and the source electrodes via diodes 26 to the drain electrodes of the second switching devices 2.
  • the gate electrodes of the further switching devices 25 are connected to the outputs of further buffers 27 which are arranged within the integrated circuit KRA and whose further connections are described in more detail below with reference to FIG. 5.
  • 30 denotes a filter which is connected on the input side to the comparison circuit 20 (node 23, FIG. 2) and on the output side to a multiplexer 31.
  • the multiplexer 31 is connected to a register 32 via parallel outputs and connected to the outputs of a ring counter 33 via parallel inputs.
  • the outputs of the ring counter 33 are connected to the inputs of the buffers 24.
  • a serial output of the register 32 is connected to an interface controller 34, which on the output side is connected to the microprocessor 4 (FIG. 1) via the one optocoupler 5.
  • the interface controller 34 is also on the input side via the other optocoupler 6 with the microprocessor 4 and via further outputs with the Inputs of the other buffers 27 connected.
  • the circuit arrangement described above works as follows:
  • the second switching devices 2 are successively switched into a conductive state by the buffers 24 activated by the ring counter 33 in order to query the switching states of the first switching devices 1.
  • a current flows via the relevant second switching device 2, the common line fvl, the load element Ld and the Zener diode HVZ to the ground connection M.
  • the voltage difference occurring at the connections vss, vdd remains constant regardless of the floating voltages Vs and Vd.
  • the other diode 22 of the comparison circuit 20 (FIG. 2) is conductive and the upper level of the voltage Us occurs at node 23 (FIG. 3b). If the voltage Vs at the connection vss becomes greater than the reference voltage Ve, the one diode 21 becomes conductive, so that the lower level of the voltage Us appears at the node 23 (FIGS. 2, 3a, 3b). After the positive half-wave H2 disappears, the voltage Vd drops again below the reference voltage Ve and the voltage Vs to the potential of the Zener voltage Vz.
  • the pulses DI thus formed from the two levels of the voltage Us at the node 23 are fed to the microprocessor 4 via the filter 30, the multiplexer 31, the register 32, the interface controller 34 and the one optocoupler 5, whereby they are logic "1 "(Signal line ML or switching state” ON ") can be interpreted.
  • the circuit arrangement ensures that if the load element Ld is interrupted or short-circuited, no logic "1" signal can be generated, so that safety requirements are easily met.
  • the pulses DI are preferably transmitted synchronously, for which purpose a clock signal is supplied via the other optocoupler 6.
  • the circuit arrangement can also be designed with a larger or smaller number.
  • an integrated circuit KRA set up for example, for ten signaling lines and circuit arrangements with a larger number of signaling lines, several integrated circuits KRA can be cascaded.
  • the KRA interface can also be formed in a conventional manner from individual components.
  • the advantages that can be achieved from rational production, in particular in the case of larger quantities, cannot be achieved here.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Combustion & Propulsion (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Electronic Switches (AREA)

Claims (8)

  1. Circuit de couplage de lignes sous tension, comprenant un microprocesseur (4), une interface (KRA), qui est reliée à des lignes d'ordres sous tension (ML) et au microprocesseur (4), des premiers dispositifs de commutation (1) étant placés sur les lignes d'ordres (ML) sous tension, dispositifs dont les états de commutation sont envoyés au microprocesseur (4), caractérisé en ce que l'interface (KRA) présente un circuit comparateur (20), en ce que, sur les lignes d'ordres (ML), des deuxièmes dispositifs de commutation (2) sont placés en série avec les premiers dispositifs de commutation (1), en ce que les lignes d'ordres (ML) sont raccordées par l'intermédiaire des deuxièmes dispositifs de commutation (2) à une ligne commune (fvl), laquelle est reliée d'une part, par l'intermédiaire d'un élément de charge (Ld), à un branchement de terre (M) et, d'autre part, à un premier branchement (vss) du circuit comparateur (20), en ce qu'un circuit d'alimentation en courant (3) est présent, lequel est raccordé à un pôle négatif sur le premier branchement (vss) et à un pôle positif sur un deuxième branchement (vdd) du circuit comparateur (20), en ce qu'un circuit de tension de référence (12) est présent, qui peut être raccordé à une phase (P) d'un réseau alternatif et est en liaison avec le branchement de terre (M) et avec le circuit comparateur (20) afin de délivrer une tension de référence au circuit comparateur (20), et en ce que les deuxièmes dispositifs de commutation (2), pour détecter l'état de commutation des premiers dispositifs de commutation (1), sont branchés dans un état conducteur l'un après l'autre dans le temps, de sorte que, les premiers et deuxièmes dispositifs de commutation (1) et (2) étant fermés et lorsque est présent une demi-onde positive d'une tension alternative appliquée aux lignes d'ordre, un courant s'écoule depuis la phase (P), par l'intermédiaire de la ligne commune (fvl) et de l'élément de charge (Ld), vers le branchement de terre (M), la tension (Vs) au pôle négatif et la tension (Vd) au pôle positif du circuit d'alimentation en courant (3), par suite d'une chute de tension (uLd) sur l'élément de charge (Ld), étant augmentées de la chute de tension (uLd), en ce que la tension (Vs) au pôle négatif et la tension (Vd) au pôle positif sont comparées au moyen du circuit comparateur (2) à la tension de référence (Ve), des impulsions (DI) étant produites lors de la présence d'une demi-onde positive et de la chute de tension (uLd), lesquelles impulsions caractérisent l'état de commutation "MARCHE" de la ligne d'ordres (ML) analysée à cet instant et sont transmises au microprocesseur (4).
  2. Circuit selon la revendication 1, caractérisé en ce que la tension (Vs) au pôle négatif et la tension (Vd) au pôle positif du dispositif d'alimentation en courant (3) sont branchées par rapport à la tension de référence (Ve) par l'intermédiaire d'une diode (21, 22), en ce qu'un niveau supérieur d'une autre tension (Us) est présent en un noeud (23) lorsque la tension (Vd) au pôle positif du dispositif d'alimentation en courant (3) est inférieure à la tension de référence (Ve), en ce que, pour une demi-onde positive, un niveau inférieur de l'autre tension (Us) est présente au noeud (23) lorsque la tension (Vs) au pôle négatif est supérieure à la tension de référence (Ve), et en ce que les niveaux supérieur et inférieur de l'autre tension (Us) sont les niveaux de l'impulsion (DI).
  3. Circuit selon la revendication 1 ou 2, caractérisé en ce que le dispositif d'alimentation en courant (3) peut être alimenté depuis la phase (P) du réseau alternatif, raison pour laquelle il est constitué du branchement en série d'une diode (8), d'une résistance (9) et d'une diode Zener (10), sur laquelle un condensateur (11) est branché en parallèle, l'anode et la cathode de la diode Zener (10) formant le pôle négatif et le pôle positif du dispositif d'alimentation en courant (3).
  4. Circuit selon l'une quelconque des revendications 1 à 3, caractérisé en ce qu'une autre diode Zener (HVZ) est branchée en série sur l'élément de charge (Ld) et en ce que les deuxièmes dispositifs de commutation (2) sont des transistors à effet de champ (FET) à commutation basse tension.
  5. Circuit selon la revendication 4, caractérisé en ce que les électrodes de drain des FET à commutation basse tension (2) sont reliées aux lignes d'ordres (ML) associées, les électrodes de source à la ligne (fvl) commune à toutes les lignes d'ordres (ML), et les électrodes de grille aux sorties de tampons (24).
  6. Circuit selon la revendication 5, caractérisé en ce que les entrées des tampons (24) sont en liaison avec un compteur annulaire, de sorte que les FET à commutation basse tension (2) peuvent être branchés dans un état conducteur les uns après les autres dans le temps.
  7. Circuit selon l'une quelconque des revendications 1 à 6, caractérisé en ce que d'autres dispositifs de commutation (25) sous la forme de FET de commutation sont associés aux lignes d'ordres (ML), les électrodes de drain étant reliées à une source de tension continue (G), les électrodes de source, par l'intermédiaire de diodes (26) aux électrodes de drain des deuxièmes dispositifs de commutation (2) et les électrodes de grille aux sorties d'autres tampons (27), et en ce que, pour examiner un deuxième dispositif de commutation (2), tous les deuxièmes dispositifs de commutation (2) sont mis à l'arrêt et un signal d'examen est délivré à la ligne d'ordres (ML) concernée, en ce qu'après confirmation de l'état ARRET de toutes les lignes d'ordres (ML), le deuxième dispositif de commutation (2) de la ligne d'ordres (ML) à examiner est mis en route et un signal d'examen est délivré à cette ligne d'ordres (ML), le cycle d'examen étant terminé lorsque l'état MARCHE de la ligne d'ordres (ML) à examiner et les états ARRET des autres lignes d'ordres (ML) ont été confirmés.
  8. Circuit selon l'une quelconque des revendications 1 à 7, caractérisé en ce que l'interface (KRA) est conformée en circuit intégré qui présente des branchements pour un certain nombre de lignes d'ordres (ML).
EP93810908A 1993-12-24 1993-12-24 Circuit de couplage de lignes sous tension avec un micro-processeur Expired - Lifetime EP0660042B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE59300430T DE59300430D1 (de) 1993-12-24 1993-12-24 Schaltungsanordnung zur Kopplung von spannungsführenden Leitungen mit einem Mikroprozessor.
EP93810908A EP0660042B1 (fr) 1993-12-24 1993-12-24 Circuit de couplage de lignes sous tension avec un micro-processeur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93810908A EP0660042B1 (fr) 1993-12-24 1993-12-24 Circuit de couplage de lignes sous tension avec un micro-processeur

Publications (2)

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EP0660042A1 EP0660042A1 (fr) 1995-06-28
EP0660042B1 true EP0660042B1 (fr) 1995-08-02

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EP93810908A Expired - Lifetime EP0660042B1 (fr) 1993-12-24 1993-12-24 Circuit de couplage de lignes sous tension avec un micro-processeur

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DE (1) DE59300430D1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2743664B1 (fr) * 1996-01-12 1998-03-27 Crouzet Appliance Controls Systeme de surveillance des etats d'interrupteurs relies a une tension alternative

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3801952C2 (de) * 1988-01-23 2000-05-11 Mannesmann Vdo Ag Elektronische Verarbeitungseinheit für Analogsignale mit einer Überwachungseinrichtung für eine Referenzspannung
CH682608A5 (de) * 1991-10-28 1993-10-15 Landis & Gyr Business Support Anordnung zur Ueberwachung von Wechselstromschaltern.

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DE59300430D1 (de) 1995-09-07
EP0660042A1 (fr) 1995-06-28

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