EP0656544A3 - Technik und Verfahren für asynchrones Abfrage design - Google Patents
Technik und Verfahren für asynchrones Abfrage design Download PDFInfo
- Publication number
- EP0656544A3 EP0656544A3 EP94117928A EP94117928A EP0656544A3 EP 0656544 A3 EP0656544 A3 EP 0656544A3 EP 94117928 A EP94117928 A EP 94117928A EP 94117928 A EP94117928 A EP 94117928A EP 0656544 A3 EP0656544 A3 EP 0656544A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- latch
- technique
- scan design
- scannable
- asynchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/158,557 US5406216A (en) | 1993-11-29 | 1993-11-29 | Technique and method for asynchronous scan design |
US158557 | 1999-10-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0656544A2 EP0656544A2 (de) | 1995-06-07 |
EP0656544A3 true EP0656544A3 (de) | 1998-07-29 |
Family
ID=22568678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP94117928A Withdrawn EP0656544A3 (de) | 1993-11-29 | 1994-11-14 | Technik und Verfahren für asynchrones Abfrage design |
Country Status (3)
Country | Link |
---|---|
US (1) | US5406216A (de) |
EP (1) | EP0656544A3 (de) |
JP (1) | JPH07202645A (de) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5513123A (en) * | 1994-06-30 | 1996-04-30 | Nec Usa, Inc. | Non-scan design-for-testability of RT-level data paths |
US5574731A (en) * | 1995-02-22 | 1996-11-12 | National Semiconductor Corporation | Set/reset scan flip-flops |
WO1997021107A1 (en) * | 1995-12-05 | 1997-06-12 | Atg Technology, Inc. | Partial scan logic |
US5958077A (en) * | 1995-12-27 | 1999-09-28 | Nec Usa, Inc. | Method for testing asynchronous circuits |
JP3758285B2 (ja) * | 1997-03-17 | 2006-03-22 | ソニー株式会社 | 遅延回路およびそれを用いた発振回路 |
US5951702A (en) * | 1997-04-04 | 1999-09-14 | S3 Incorporated | RAM-like test structure superimposed over rows of macrocells with added differential pass transistors in a CPU |
US5983377A (en) * | 1997-11-17 | 1999-11-09 | Ncr Corporation | System and circuit for ASIC pin fault testing |
US6128758A (en) * | 1998-05-20 | 2000-10-03 | National Semiconductor Corporation | Modular re-useable bus architecture |
US6300809B1 (en) * | 2000-07-14 | 2001-10-09 | International Business Machines Corporation | Double-edge-triggered flip-flop providing two data transitions per clock cycle |
ATE359524T1 (de) * | 2000-09-11 | 2007-05-15 | Freescale Semiconductor Inc | Prüfbare analog/digitalschnittstelleschaltung |
US6573775B2 (en) | 2001-10-30 | 2003-06-03 | Integrated Device Technology, Inc. | Integrated circuit flip-flops that utilize master and slave latched sense amplifiers |
US6700425B1 (en) | 2001-10-30 | 2004-03-02 | Integrated Device Technology, Inc. | Multi-phase clock generators that utilize differential signals to achieve reduced setup and hold times |
KR20050012820A (ko) * | 2002-06-21 | 2005-02-02 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 전자 회로 및 전자 회로 테스트 방법 |
JP4265934B2 (ja) * | 2003-06-06 | 2009-05-20 | シャープ株式会社 | スキャンパス回路およびそれを備える論理回路ならびに集積回路のテスト方法 |
JP4274457B2 (ja) * | 2003-06-27 | 2009-06-10 | インターナショナル・ビジネス・マシーンズ・コーポレーション | トランスペアレントラッチ回路 |
JP4281648B2 (ja) * | 2004-08-04 | 2009-06-17 | セイコーエプソン株式会社 | 印刷装置 |
US7680474B2 (en) * | 2005-10-04 | 2010-03-16 | Hypres Inc. | Superconducting digital mixer |
US7667500B1 (en) * | 2006-11-14 | 2010-02-23 | Xilinx, Inc. | Glitch-suppressor circuits and methods |
US7890826B2 (en) * | 2006-12-11 | 2011-02-15 | Oracle America, Inc. | Method and apparatus for test of asynchronous pipelines |
FR2961043B1 (fr) * | 2010-06-04 | 2012-07-20 | St Microelectronics Sa | Registre a double front et son controle a partir d'une horloge |
WO2011158500A1 (ja) * | 2010-06-17 | 2011-12-22 | 国立大学法人 奈良先端科学技術大学院大学 | スキャン非同期記憶素子およびそれを備えた半導体集積回路ならびにその設計方法およびテストパターン生成方法 |
JP2014158176A (ja) * | 2013-02-15 | 2014-08-28 | Renesas Electronics Corp | 半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6029680A (ja) * | 1983-07-27 | 1985-02-15 | Toshiba Corp | Cmos論理回路の試験方法 |
GB2218816A (en) * | 1988-05-19 | 1989-11-22 | Plessey Co Plc | Testing integrated circuits |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4506165A (en) * | 1982-06-30 | 1985-03-19 | At&T Bell Laboratories | Noise rejection Set-Reset Flip-Flop circuitry |
JP2945103B2 (ja) * | 1990-05-15 | 1999-09-06 | 株式会社リコー | テスト用スキャン回路装置 |
-
1993
- 1993-11-29 US US08/158,557 patent/US5406216A/en not_active Expired - Fee Related
-
1994
- 1994-11-14 EP EP94117928A patent/EP0656544A3/de not_active Withdrawn
- 1994-11-28 JP JP6316095A patent/JPH07202645A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6029680A (ja) * | 1983-07-27 | 1985-02-15 | Toshiba Corp | Cmos論理回路の試験方法 |
GB2218816A (en) * | 1988-05-19 | 1989-11-22 | Plessey Co Plc | Testing integrated circuits |
Non-Patent Citations (2)
Title |
---|
MAUNDER: "IEEE Standard Test Access Port and Boundary-Scan Architecture", 21 May 1990, INSTITUTE OF ELECTRICAL AND ELECTRONIC ENGINEERS, NEW YORK, USA, XP002026236, 11491 * |
PATENT ABSTRACTS OF JAPAN vol. 9, no. 151 (P - 367) 26 June 1985 (1985-06-26) * |
Also Published As
Publication number | Publication date |
---|---|
EP0656544A2 (de) | 1995-06-07 |
JPH07202645A (ja) | 1995-08-04 |
US5406216A (en) | 1995-04-11 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB |
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PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
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AK | Designated contracting states |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19990601 |