EP0650646A1 - Recepteur rake a double transmission pour liaison radio digitale entre un appareil radio fixe et un appareil radio mobile - Google Patents

Recepteur rake a double transmission pour liaison radio digitale entre un appareil radio fixe et un appareil radio mobile

Info

Publication number
EP0650646A1
EP0650646A1 EP94909998A EP94909998A EP0650646A1 EP 0650646 A1 EP0650646 A1 EP 0650646A1 EP 94909998 A EP94909998 A EP 94909998A EP 94909998 A EP94909998 A EP 94909998A EP 0650646 A1 EP0650646 A1 EP 0650646A1
Authority
EP
European Patent Office
Prior art keywords
output
input
circuit
signal
filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94909998A
Other languages
German (de)
English (en)
Inventor
Anthony Peter Hulbert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Roke Manor Research Ltd
Original Assignee
Roke Manor Research Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB939309748A external-priority patent/GB9309748D0/en
Application filed by Roke Manor Research Ltd filed Critical Roke Manor Research Ltd
Publication of EP0650646A1 publication Critical patent/EP0650646A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
    • H04B1/7117—Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers

Definitions

  • the present invention relates to apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit.
  • the RF input signal is passed through a filter 2, the output of which is applied to an input of half linear multipliers 4, 6.
  • a local oscillator 8 feeds a 0/90° phase shifter 10 which applies the local oscillator signal to a second input of the half linear multiplier 4 and a 90° phase signal to the second input of the half linear multiplier 6.
  • the output signal from each of the half linear multipliers 4 and 6 is applied to a number of Rake fingers 10, 12, 14, 16.
  • Each Rake finger comprises a pilot correlator 18, the output of which is connected to a Wiener-like filter 20, and a signal correlator 24, the output of which is connected to a delay circuit 26.
  • the correlators 18, 24 each receive the output signal from the half linear multiplier 6.
  • the output of the Wiener-like filter 20 and the delay circuit 26 are multiplied together by a multiplier 22, the output of which is applied to a first input of an adder circuit 28.
  • Each Rake finger also includes a pilot correlator 30, the output of which is connected to a Wiener-like filter 32.
  • a signal correlator 36 has an output connected to delay circuit 38.
  • the pilot correlator 30 and the signal correlator 36 receives the output signal from the half linear multiplier 4.
  • the output signals from the Wiener filter 32 and the delay circuit 38 are multiplied by a multiplier 34, the output of which is applied to a second input of the adder circuit 28.
  • the output signal generated by the adder circuit 28 is applied to a further adder circuit 40 which combines all the output signals from the other Rake fingers 12, 14, 16.
  • the multipliers 22, 34 are four quadrant multipliers having several bit precision on their inputs. All the circuitry shown in Rake finger 1 is repeated in the other Rake fingers. The only difference between the different Rake fingers is that the correlators are fed with pseudo random sequences timed to correlate against signals received over different paths.
  • the architecture shown in Figure 1 implements fully coherent maximum ratio combining over the different Rake fingers. Multiplication with the Wiener filter outputs not only compensates the phase of the signal but also weights the amplitude of each Rake component according to its signal strength prior to addition.
  • FIG. 2 Another form of Wiener-like filter arrangement is shown which may be used in the demodulation of DBPSK (dual binary phase shift keying).
  • DBPSK dual binary phase shift keying
  • FIG. 2 a plurality of Rake fingers are shown 42, 44, 46, 48.
  • Each Rake finger comprises a signal correlator 50 which handles the in-phase signal and a further signal correlator 52 which handles the Quadrature phase signal.
  • the output signal from the correlator 50 is applied to a half linear multiplier 54 by way of a 1-bit delay circuit 53.
  • the output of the half linear multiplier 54 is applied to an input of a Wiener-like filter 56.
  • the output of the Wiener-like filter 56 is applied to a multiplier 58.
  • the output of the correlator 50 is also applied to a further input of the multiplier 58, the output of which is applied to a first input of an adder circuit 60.
  • the output signal from the signal correlator 52 is applied to a half linear multiplier 62 by way of a 1-bit delay circuit 61.
  • the output of the half linear multiplier 62 is applied to an input of a further Wiener-like filter 64.
  • the output of the Wiener-like filter 64 is applied to an input of a multiplier 66.
  • the output signal from the correlator 52 is also applied to a further input of the multiplier 66, the output of which is applied to a second input of the adder circuit 60.
  • the output of the adder circuit 60 together with the output signals from the other Rake fingers 44, 46, 48 are applied to an adder circuit 68 which generates a combined sum of all the input signals for application to a decision circuit 70.
  • the decision circuit 70 merely identifies whether the signal is high or low and the output of the decision circuit 70 is fed back by way of a latch circuit 71 , to a second input of the respective half linear multipliers 54, 62 in the Rake finger 1 , 42 and similarly to the half linear multipliers in the other Rake fingers to modify the signal applied to the respective Wiener-like filters 56, 64 in the Rake finger 1 , 42 and similarly in the other Rake fingers.
  • the output of the decision circuit 70 is applied to an input of a differential decode circuit 72 which is arranged to output data on the output line 74.
  • the circuit shown in Figure 2 uses hard decisions which are taken using the sum over all the Rake fingers to remove the modulation from the received signal.
  • the most up to date available decision is the previous one so in order to remove the modulation this must be applied to the previous sample, leading to a one sample delay.
  • This delay is removed from the derived channel estimate by using a Wiener-like filter operating as a one step predictor. Inevitably this will mean that the variance in the channel estimate will be greater than in systems incorporating a pilot which can apply symmetrical filtering.
  • An object of the present invention is to provide apparatus for use in equipment for providing a digital radio link between a fixed and mobile radio unit which uses a Wiener-like filter arrangement having an improved performance over the prior art arrangements.
  • apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit comprising a plurality of circuit means each being arranged to generate a data output signal and a feedback signal, said circuit means including a Wiener-like filter for an In-phase channel and a Quadrature phase channel and arranged to receive an In-phase and Quadrature phase input signal respectively, processing means for determining the nature of said feedback signal to be applied to each circuit means to modify the input signal, characterised in that each Wiener filter has an associated past sample symmetrical filter, and an output from each Wiener filter is processed by said processing means, and an output from the said past sample symmetrical filter is used to generate said output data signal.
  • FIGURE 3 shows a block diagram of a double pass decision directed demodulator in accordance with the present invention
  • FIGURE 4 shows a block diagram of a dual role Wiener-like filter for use in the arrangement shown in Figure 3;
  • FIGURES 5 shows a simplified variation of the block diagram of the demodulator shown in Figure 3;
  • FIGURE 6 shows a variation of the Wiener-like filter shown in Figure 4 for use with the demodulator shown in Figure 5;
  • FIGURES 7 and 8 show a variation of the demodulator and Wiener-type filter shown respectively in Figures 5 and 6;
  • FIGURES 9 and 10 show a block diagram of a further embodiment of the present invention suitable for handling multiple phase differential phase shift keying (MDPSK), and,
  • MDPSK multiple phase differential phase shift keying
  • FIGURE 11 shows a variation of the block diagrams shown in Figures 9 and 10.
  • a demodulator having a plurality of Rake fingers 76, 78, 80, 82.
  • Each Rake finger includes a signal correlator 84 which handles the In-phase signals and a signal correlator 86 which handles Quadrature phase signals.
  • the correlator 84 is connected to an input of a 1-bit delay circuit 87 and to an input of a multiplier 90.
  • the output of the 1-bit delay circuit 87 is connected to an input of a half linear multiplier 88, the output of which is connected to a one step predictor filter 92, a past sample symmetrical filter 94 and to a signal shift register 96.
  • the output of the one step predictor filter 92 is connected to a further input of the multiplier 90.
  • the output of the past sample symmetrical filter 94 is connected to an input of a multiplier 98, and the output of the signal shift register 96 is connected to a further input of the multiplier 98.
  • the output of the multiplier 98 is connected to an input of an adder circuit 100.
  • the signal correlator 86 has an output connected to an input of a 1-bit delay circuit 101 and to an input of a multiplier 104.
  • the output of the 1 -bit delay circuit 101 is connected to an input of the half linear multiplier 102, the output of which is connected to an input of a one step predictor filter 106, an input of a past sample symmetrical filter 108, and to an input of a signal shift register 110.
  • the output of the one step predictor filter 106 is connected to a further input of the multiplier 104.
  • the output of the multiplier 104 is connected to an input of an adder circuit 112, which receives at a second input the output of the multiplier circuit 90.
  • the output of the past sample symmetrical filter 108 is connected to an input of a multiplier circuit 114, and the output of the signal shift register 110 is connected to a further input of the multiplier circuit 114.
  • the output of the multiplier circuit 114 is connected to a further input of the adder circuit 100.
  • Each Rake finger includes the above mentioned circuitry, and the output signals from the respective adder circuits 100 are summed by an adder circuit 1 16.
  • the output of the adder circuit 1 16 is connected to a limiter 1 18 the output of which is connected to a further input of each past sample symmetrical filter 94, 108 in each Rake finger to invert the incorrect samples.
  • the output of the adder 116 is also connected to an input of a half linear multiplier 126.
  • each Rake finger has an adder circuit 112, the output of which is connected to the input of an adder circuit 120 which has its output connected to a limiter devices 122.
  • the output of the limiter devices 122 is connected to a further input of each half linear multiplier 88, 102 in each Rake finger and is also connected to an input of a data shift register 124.
  • the output of the data shift register 124 is connected to a further input of the half linear multiplier 126.
  • the output of the half linear multiplier 126 is connected to an input of a 1-bit delay circuit 128, and to an input of a multiplier 130.
  • An output of the 1-bit delay circuit is connected to a further input of the multiplier 130.
  • the 1-bit delay circuit 128 and multiplier circuit 130 define a differential decode circuit 132.
  • Figure 3 combines the features of Figure 1 and Figure 2, which use respectively known pilot and decision directed operations respectively.
  • the block designated 76, Rake finger 1 shows the real and the imaginary circuits drawn as mirror images.
  • the elements closest together implement the decision directed operations of the prior art circuit shown in Figure 2, whilst the elements furthest apart implement pilot reference detection operations of Figure 1.
  • the one step predictor and the past sample symmetrical filter 92, 94 and 106, 108 respectively are shown combined into one block because as will be explained later significant savings in complexity can be achieved by performing the two filtering operations together.
  • the principles of operation are as follows.
  • the one step predictor filter 92, 106 provides channel estimates which are used to phase align and amplitude weight the signals on each of the Rake fingers 76 to 82. These output signals from the one step predictors are combined by the adder circuit 112, after passing through the respective multipliers 90, 104 and hard (tentative) decisions are taken.
  • the data which is fed into the one step predictor filters and the past sample symmetrical filters are corrected in sense by the decisions. For any given place in a received sequence, sometime later, the past sample symmetrical filter will produce a new, usually more accurate, channel estimate. This new channel estimate is used to phase align and weight the correspondingly delayed received signal sample.
  • the delay in the received single sample is caused by the respective signal shift register 96, 110.
  • the output signal from the multipliers 98 and 114 are combined by the adder circuit 100 to create new decisions. Note however, that each delayed signal sample has already been compensated by the tentative decisions.
  • the new decisions represents the difference between the tentative decisions and the final decisions. If the output of the limiter device 122 is positive, then the original decision is validated otherwise it should be inverted.
  • the output signal from the limiter device 122 is applied to the inputs of the combiner circuits 88, 102 and to the shift register 124.
  • the output from the shift register is combined with the output from the adder circuit 1 16 in the half linear multiplier 126, and applied to the differential decode circuit 132.
  • the new decisions can also be used to correct the contents of the shift register contained in the past sample symmetrical filters. This is achieved by the feedback path from the second limiter device 118 to the Wiener filter block marked "Invert Incorrect Sample".
  • the Wiener-like filter comprises a shift register 136 which receives an input signal from the respective half linear multiplier 88, 102, Figure 3.
  • An integrate and dump circuit 142 also receives the input signal.
  • the final stage of the shift register 136 is connected to a half linear multiplier 138 which receives the Invert Incorrect Samples signal as shown in Figure 3.
  • the output of the half linear multiplier 138 is connected to a shift register 140 and to an input of a second integrate and dump circuit 146.
  • the final stage of the shift register 140 is connected to the second input of the integrate and dump circuit 146.
  • the integrate and dump circuit 142 has its second input connected to one of the stages of shift register 136.
  • the output of the integrate dump circuit 142 is connected to an input of a shift register 144, and the output of the integrate dump circuit 146 is connected to the input of a shift register 148.
  • the block designated 150 represents a one step predictor and comprises three multiplying circuits 152, 154, 156, each having an input connected to a respective stage of the shift register 144, and each multiplying circuit having a second input for receiving a weighted coefficient as shown.
  • the output from each multiplying circuit is connected to an input of an adder circuit 158 which also has an input connected to the output of the second integrate and dump circuit 142.
  • the output of the adder circuit 158 represents the output of the one step predictor which is connected to its associating multiplying circuit in Figure 3.
  • the symmetrical past sample filter includes adder circuits 160, 162, 164, 166.
  • the output of the second integrate and dump circuit 146 is connected to an input of the adder circuit 160, and the second input of the adder circuit 160 is connected to the final stage of the shift register 144.
  • the adder circuits 162 and 164 each have a pair of input lines, one of which is connected to a respective different stage of the shift register 144, and their second input is connected to a respective different stage of the shift register 148.
  • the adder circuit 160 has an input connected to the last stage of the shift register 148 and its other input is connected to the output of the integrate and dump circuit 142.
  • the output of the adder circuits 162, 164, 166 is connected to an input of a respective multiplying circuit 168, 170, 172.
  • the multiplying circuits 168, 170, 172 have a further input for receiving a weighted coefficient as shown.
  • the outputs from the multiplying circuits are connected to an input of a further adder circuit 174 which also receives the output from the adder circuit 160.
  • the output of the adder circuit 174 represents the output of the symmetrical past sample filter which is connected to the respective multiplier in Figure 3.
  • the block designated 150 may be replicated, for example, three times with different coefficients according to the required filter speed.
  • FIG. 5 shows a simplified variation of the circuit shown in Figure 3. It will be appreciated that like circuit blocks have been designated with the same numerical reference and their function is the same as that described with reference to Figure 3.
  • each past sample symmetrical filter 94, 108 has an extra input to which the output from the signal correlator 84 and 86 is connected respectively.
  • the signal shift registers 96, 1 10 also receive the output from the signal correlators 84, 86 respectively instead of being connected to receive the output from the half linear multipliers 88, 102 respectively.
  • the second half of the modulation is removed by the signal fed from the limiter device 1 18, and the additional input to each past sample symmetrical filter constitutes the second half of the input signal.
  • FIG. 7 and 8 Another variation of the circuitry shown in Figures 5 and 6 are shown in Figure 7 and 8. It will be appreciated that the circuits operate in similar manner and like elements have been given like designations. It will be seen by comparing Figure 6 with Figure 8 that with respect to the second half input there is no need for the shift register 136 and the half linear multiplier 138, which was used to remove the second half of the modulation. With reference to Figure 8, the second half input is fed directly to the shift register 140 and to the integrate and dump circuit 146.
  • the block diagram shown in Figure 7 now includes a further 1-bit delay circuit 97 and a further combiner circuit 99 with respect to the In-phase channel and a further 1 -bit delay circuit 111 and a half linear multiplier 113 in respect to the Quadrature-phase channel.
  • the 1-bit delay circuit 97, 1 11 receives the output from the shift registers 96 and 1 10 respectively, and the output from the 1-bit delay circuit is combined with the signal fed from the limiting circuit 118 by the half linear multiplier 99, 113 respectively.
  • the outputs from the half linear multipliers 99, 113 are applied to the past sample symmetrical filter 94, 108 respectively, as the second half input as shown in Figure 8.
  • FIG. 9 a block diagram is shown of a further embodiment of the present invention suitable for handling multiple phase differential phase shift keying (MDPSK).
  • MDPSK multiple phase differential phase shift keying
  • each Rake finger includes the circuitry shown as described with reference to Rake finger 180.
  • Each Rake finger includes a signal correlator 186 which receives an In-phase signal I from a down converter at an input thereof. The output of the signal correlator 186 is connected to an input of a 1-bit delay circuit 188, an input of a signal shift register 190, and to an input of a multiplier 192. An output of the signal shift register 190 is connected to an input of a multiplier 194 and an output of the 1-bit delay circuit 188 is connected to a first input of a complex linear multiplying circuit 196.
  • a second signal correlator 198 receives a Quadrature phase signal from the down converter at an input thereof, and the output of the signal correlator 198 is connected to an input of a 1- bit delay circuit 200, an input of a multiplier 202, and to an input of a signal shift register 204. An output of the signal shift register 204 is connected to an input of a multiplier 206. An output of the 1-bit delay circuit 200 is connected to a second input of the complex linear multiplying circuit 196.
  • the complex linear multiplying circuit 196 has a first output connected to a past sample symmetrical filter 208 and to a one step predictor filter 210. An output from the past sample symmetrical filter 208 is connected to a further input of the multiplying circuit 194.
  • An output of the one step predictor filter 210 is connected to a further input of the multiplying circuit 192.
  • a second output from the complex linear multiplying circuit 196 is connected to an input of a further past sample symmetrical filter 212, and to an input to a one step predictor filter 214.
  • An output of the past sample symmetrical filter 212 is connected to a further input of the multiplying circuit 206, and an output of the one step predictor filter 214 is connected to a further input of the multiplying circuit 202.
  • the outputs from the multiplying circuits 194, 206 are respectively applied to an input of an adder circuit 216, 218. It will be appreciated that these adder circuits receive the outputs from the other Rake fingers 182, 183, 184.
  • the outputs from the multiplying circuits 192, 202 are connected respectively to further adder circuits 220, 222, and it will be appreciated that the adder circuits 220, 222 receive the respective outputs from the other Rake finger circuits 182, 183, 184.
  • the outputs of the adder circuits 216, 218 are connected to respective inputs of a differential decode circuit 224 which generates data on an output lead 226.
  • the outputs of the adder circuits 216, 218 may also be connected to respective inputs of a normalised amplitude and threshold nearest phase in alphabet circuit 228, the outputs from which are connected to respective inputs of a complex conjugate circuit 230.
  • the outputs from the adder circuits 220, 222 are respectively connected to an input of a further normalise amplitude and nearest threshold phase in alphabet circuit 232, the outputs of which are connected to a respective input of a further complex conjugate circuit 234 and to inputs of a respective delay circuit 236, 238.
  • the outputs from the complex conjugate circuit 234 are connected to a respective input of the complex linear multiplying circuit in each Rake finger such as circuit 196 in Rake finger 1.
  • the outputs from the delay circuits 236, 238 are connected to a respective input of a further complex linear multiplying circuit 240, which also receives the outputs from the complex conjugate circuit 230.
  • the complex linear multiplying circuit 240 has two output lines which may be connected to the complex linear multiplying circuits such as 196 in each Rake finger instead of those signals which may be generated from the complex conjugate circuit 234.
  • the complex linear multiplying circuit 196 has two output lines each connected to an input designated I Comp In on the past sample symmetrical filter 208 and to an input designated Q Comp In on the past sample symmetrical filter 212.
  • the output designated I Comp Out from the past sample symmetrical filter 208 is connected to an input of the complex linear multiplying circuit 196, and similarly the output designated Q Comp Out from the past sample symmetrical filter 212 is connected to a further input of the complex linear multiplying circuit 196.
  • Figure 9 described the new implementation of the invention designed to handle multiple phase differential phase shift keying (MPDSK). Because MPDSK modulates information into the I and the Q channels separately, a full complex demodulation function is required.
  • the first operation in the channel estimation path is to, as before, remove the effect of the data, and then to remove the modulation from the received signal. Because the modulation is now complex this has to be done by a complex linear multiplier circuit 196. This circuit receives inputs from the first past demodulator as will be described later.
  • the outputs of the complex linear multiplier circuit 196 feed, as before, into the paired past sample symmetrical filter 208, 212 and the one step predictor filter 210, 214 and phase and amplitude weighting and compensation are applied as before in respect of the first and second past outputs.
  • the previous outputs pass from the multipliers 192, 202 and are summed across the other Rake fingers in the adder circuits 220, 222.
  • At this stage we have a complex signal which is phase compensated and has been optimally combined across the Rake components. For the purposes of stripping off the modulation from the received signal, a form of decision is required on these outputs.
  • the output from the adder circuits 220, 222 are fed into a circuit 232 which normalises the amplitude of the complex signal and thresholds it to the nearest phase in the signal alphabet, so for eight phase DPSK, for example, the thresholding would be to the nearest of the 8, ⁇ / 4 phases. Having performed this function, the outputs are passed to a circuit 234 which performs the complex conjugate of this output, thus reversing the associated phase. This inverts the Q channel whilst passing through. The signal is then passed up to complex linear multiplier 196 for removal of the modulation.
  • the outputs from the multiplier circuits 194, 206 are again summed across the Rake fingers in the adder circuits 216, 218 and for the normal purposes of demodulation the output signals are fed to a differential decode circuit 224 which performs differential decoding.
  • This operation consists of complex multiplication of the current complex sample with the complex conjugate of the previous complex sample, thus if the current complex sample is denoted Zn and previous complex sample is denoted Zn- 1, the output will be Zn x Z*n- 1.
  • the demodulation then can be performed through suitable thresholding or if a form of error control coding has been applied then this complex signal may then be applied directly to the decoder.
  • a further attribute of the invention as described earlier, is the ability to perform the second pass compensation of data to the contents of the second half of the past sample symmetrical filter, this operation is not essential to the working of the invention but will improve performance. If required then the blocks shown within the dotted outline 242 are used.
  • the outputs of the adder circuits 216, 218 feed into the circuit 228 which performs the same function as previously described, thus providing a phaser which has the correct decision applied to it. Now because this signal bears the modulation and it is desirable to compensate the signal that has had the modulation stripped, there is a need to remove the original stripping of the modulation from the original signal.
  • the original stripping signal was derived from the outputs of circuit 232, and is this held over by delay circuits 236, 238.
  • the difference between the data on the two outputs is computed in the complex linear multiplier circuit 240.
  • the outputs of the complex multiplier circuit 240 labelled Mid-Filter Compensating Lines can then be applied to compensate the phase of the signals within the centre point of the past sample symmetrical filters through the respective outputs and inputs I Comp Out, I Comp In, Q Comp Out, Q Comp In.
  • I Comp Out, I Comp In, Q Comp Out, Q Comp In For clarity these operations are shown separately in Figure 6.
  • it is shown how the outputs I Comp Out and Q Comp Out are fed to a complex linear multiplier for processing by the outputs from the mid-filter compensating lines before being returned back into the filters through the I Comp In line and the Q Comp In lines respectively.
  • FIG. 1 1 a variation of the block diagram shown in Figure 9 is depicted. Again, like elements have been given the same designation and function in the same manner as described with reference to Figure 9. It will be seen that the variation mainly concerns the box identified as 242.
  • the complex linear multiplying circuit 230 is no longer used to generate signals on the mid filter compensating lines, but receives as before the output signals from the complex conjugate circuit 230.
  • the complex linear multiplying circuit receives signals from respective 1-bit delay circuits 236 and 238, * whose inputs are connected to the outputs of the signal .shift register 190 in the I-signal channel, and to signal shift register 204 in the Q-signal channel respectively.
  • Complex linear multiplying circuit 230 generates two output signal designated e, f which are applied to the respective inputs of the past sample symmetrical filters 208, 212. It will be appreciated by those skilled in the art that various modifications are possible without departing from the spirit and scope of the present invention. For example in Figure 4, the implementation of the combined past sample symmetrical filter and the one step predictor filter could still be as shown in Figure 4, except that the multiplier circuit 138 would be removed from this figure and the input would become I Comp Out and its output would become I Comp In or Q Comp Out and Q Comp In for the other filter.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

L'appareil comprend une pluralité de circuits Rake conçus chacun pour générer un signal de sortie de transmission de données et un signal de retour. Chaque circuit Rake comprend un filtre de type Wiener pour la bande du signal I et la bande du signal Q, et un dispositif de traitement pour déterminer la nature du signal de retour appliqué à chaque circuit Rake pour modifier le signal d'entrée. A chaque filtre Wiener correspond un filtre symétrique pour signaux échantillonnés et une sortie de chaque film Wiener est traitée dans ledit dispositif de traitement, et une sortie dudit filtre symétrique pour signaux échantillonnés est utilisée pour générer ledit signal de sortie de transmission de données.
EP94909998A 1993-05-12 1994-03-22 Recepteur rake a double transmission pour liaison radio digitale entre un appareil radio fixe et un appareil radio mobile Withdrawn EP0650646A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
GB939309748A GB9309748D0 (en) 1993-05-12 1993-05-12 Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit
GB9309748 1993-05-12
GB9317204 1993-08-18
GB9317204A GB2278029B (en) 1993-05-12 1993-08-18 Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit
PCT/GB1994/000580 WO1994027379A1 (fr) 1993-05-12 1994-03-22 Recepteur rake a double transmission pour liaison radio digitale entre un appareil radio fixe et un appareil radio mobile

Publications (1)

Publication Number Publication Date
EP0650646A1 true EP0650646A1 (fr) 1995-05-03

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EP94909998A Withdrawn EP0650646A1 (fr) 1993-05-12 1994-03-22 Recepteur rake a double transmission pour liaison radio digitale entre un appareil radio fixe et un appareil radio mobile

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Country Link
EP (1) EP0650646A1 (fr)
JP (1) JPH07509113A (fr)
FI (1) FI945795A0 (fr)
WO (1) WO1994027379A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2281482B (en) * 1993-08-26 1997-10-22 Roke Manor Research Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit
US5574747A (en) 1995-01-04 1996-11-12 Interdigital Technology Corporation Spread spectrum adaptive power control system and method
US5737326A (en) * 1996-07-12 1998-04-07 Lucent Technologies Inc. Multi-code code division multiple access receiver

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9023605D0 (en) * 1990-10-30 1990-12-12 British Telecomm Digital radio

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9427379A1 *

Also Published As

Publication number Publication date
JPH07509113A (ja) 1995-10-05
FI945795A (fi) 1994-12-09
WO1994027379A1 (fr) 1994-11-24
FI945795A0 (fi) 1994-12-09

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