EP0631284B1 - Circuit de protection pour les dispositifs comprenant des mémoires non-volatiles - Google Patents

Circuit de protection pour les dispositifs comprenant des mémoires non-volatiles Download PDF

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Publication number
EP0631284B1
EP0631284B1 EP93830279A EP93830279A EP0631284B1 EP 0631284 B1 EP0631284 B1 EP 0631284B1 EP 93830279 A EP93830279 A EP 93830279A EP 93830279 A EP93830279 A EP 93830279A EP 0631284 B1 EP0631284 B1 EP 0631284B1
Authority
EP
European Patent Office
Prior art keywords
circuit
supply line
transistor
output
fact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP93830279A
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German (de)
English (en)
Other versions
EP0631284A1 (fr
Inventor
Saverio Pezzini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, SGS Thomson Microelectronics SRL filed Critical STMicroelectronics SRL
Priority to EP93830279A priority Critical patent/EP0631284B1/fr
Priority to DE69314013T priority patent/DE69314013T2/de
Priority to JP6139096A priority patent/JPH07141894A/ja
Priority to US08/267,145 priority patent/US5579196A/en
Publication of EP0631284A1 publication Critical patent/EP0631284A1/fr
Application granted granted Critical
Publication of EP0631284B1 publication Critical patent/EP0631284B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Definitions

  • the present invention relates to a protection circuit for devices comprising nonvolatile memories.
  • the content of the memory must be protected in the event supply V CC is inadvertently cut off in the presence of programming voltage V PP , or in the event voltage V PP is applied before supply voltage V CC when the device is turned on.
  • protection circuits comprising comparators, which compare supply voltage V CC with a reference voltage and, if the supply voltage is lower than the reference voltage, disable supply of voltage V PP to prevent damaging the memory or altering the stored data.
  • EP-A-0 053 273 discloses a protection circuit for a nonvolatile memory.
  • the circuit compares the supply voltage with a reference voltage and grounds the wordlines of the memory if the supply voltage drops below the reference voltage.
  • the circuit according to the present invention receives two reference voltages V CC (defining the supply voltage) and V PP (defining the programming voltage of the memory, not shown) supplied respectively over lines 8 and 9.
  • the circuit substantially comprises a comparator 2, a reference voltage V REF source 3 (both supplied with voltage V PP via respective P channel MOS transistors 4, 5), and an inverter 6 supplied with voltage V PP and controlled by supply voltage V CC .
  • comparator 2 comprises a pair of N channel MOS transistors 10, 11 having the control terminals connected respectively to V CC supply line 8 and voltage source 3; the source terminals connected to each other and to a constant current source 12 (in this case, a MOS transistor); and the drain terminals connected (at nodes 13, 14) to the inputs of a current mirror 15 formed by two P channel MOS transistors 16, 17.
  • Transistor 16 connected to transistor 10 of comparator 2 is diode-connected, with its control terminal shortcircuited with its drain terminal connected to node 13.
  • the source terminals of transistors 16, 17 not connected to nodes 13, 14 are mutually connected at node 18, which is connected via transistor 4 to line 9 supplying voltage V PP Transistor 4 presents the control terminal connected to line 8 (V CC ), the drain terminal connected to node 18, and the source terminal and substrate connected to line 9.
  • V CC line 8
  • V PP source terminal and substrate connected to line 9.
  • the drawing also shows the connection between the substrate of transistors 16, 17 and line 9 (V PP ).
  • voltage source 3 is formed by the series connection of two diode-connected N channel MOS transistors 22 and 23 connected between node 24, to which the control terminal of transistor 11 is connected, and ground (also defined as reference potential line).
  • Node 24 is also connected to line 9 via transistor 5, which presents the control terminal connected to voltage V CC , the drain terminal connected to node 24, and the source terminal and substrate connected to line 9.
  • the output node 14 of comparator 2 is connected to the control terminal of an N channel MOS output transistor 27 having the source terminal grounded and the drain terminal connected, via node 28, to the drain terminal of a P channel MOS transistor 29, which presents the control terminal connected to V CC line 8, and the source terminal and substrate connected to V PP line 9.
  • Transistors 27 and 29 combine to form an inverter.
  • Node 28 is connected to the output of inverter 6 and to the control terminal of a P channel MOS transistor 30 operating as a switch. More specifically, transistor 30 presents the source terminal and substrate connected to line 9, and the drain terminal (defining output 31 of circuit 1) connected to the device 32 for protection (including a memory not shown).
  • Inverter 6 comprises a pair of opposite-channel transistors 35, 36 series connected to each other; an inverter 37; and an N channel MOS transistor 38 operating as a switch. More specifically, transistor 35 is of P channel type, with the source terminal and substrate connected to line 9; the drain terminal connected to the drain terminal of transistor 36 at node 40; and the control terminal connected to the control terminal of transistor 36 and to V CC line 8. Transistor 36, which is of N channel type, also presents a grounded source terminal. Inverter 37 is located between node 40 and the control terminal of transistor 38, which presents a grounded source terminal, and the drain terminal connected to node 28.
  • V TH the threshold voltage of the PMOS transistors (the voltage between the source terminal and control terminal, over and above which the transistor is turned on) is indicated by V TH .
  • transistor 35 is on; transistor 36 is off; node 40 is high; the output of inverter 37 is low, so that transistor 38 is off; transistors 4, 5 and 29 are on and supply comparator 2 and voltage source 3; and, since the control terminal of transistor 10 is at a lower potential (V CC ) than node 24 (V PP ), output 14 of comparator 2 is low, transistor 27 is off, node 28 presents roughly the same potential as line 9 (V PP ), and transistor 30 is off, thus disabling supply of V PP .
  • transistor 35 is off; transistor 36 is on; node 40 is low; the output of inverter 37 is high; transistor 38 is on, thus grounding node 28; transistor 30 is on, thus enabling supply of V PP ; and transistors 4, 5 and 29 are off, so that comparator 2 is also off and absorbs no current.
  • the state of transistor 27 is unknown.
  • V REF ⁇ V CC ⁇ V PP - V TH i.e. V PP - V CC > V TH
  • transistor 35 is on; node 40 is high; the output of inverter 37 is low, so that transistor 38 is off; transistors 4, 5 and 29 are on and supply voltage source 3 and comparator 2, the output 14 of which is high; transistor 27 is on and maintains a low voltage at node 28; and transistor 30 is on, thus enabling supply of programming voltage V PP to output 31 of the circuit and to device 32.
  • the circuit according to the present invention provides for detecting situations endangering the device and due to the supply voltage being cut off in the presence of programming voltage, or due to the programming voltage rising more rapidly as compared with the supply voltage when the device is turned on. Secondly, under normal operating conditions, static consumption of the comparator is zero, thus eliminating any consumption and associated dissipation problems. In any case, the circuit according to the present invention provides for correct supply of the programming voltage as determined by the operating conditions.
  • the transistors may consist of bipolar devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Electronic Switches (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Claims (8)

  1. Circuit de protection (1) pour dispositifs (32) comprenant des mémoires non volatiles, le circuit (1) comprenant au moins une première (8) et une seconde (9) lignes d'alimentation présentant respectivement une première (VCC) et une seconde (VPP) tensions d'alimentation; un moyen formant source de tension de référence (3) destiné à produire une tension de référence (VREF); un moyen de comparaison (2) connecté à ladite première ligne d'alimentation (8) et audit moyen formant source; et un moyen de commutation (30) commandé par ledit moyen de comparaison, par l'intermédiaire d'une borne de commande, et situé entre ladite seconde ligne d'alimentation (9) et la sortie (31) dudit circuit (1) afin de déconnecter la seconde ligne d'alimentation (9) de ladite sortie (31) lorsque la première tension d'alimentation (VCC) chute au-dessous de ladite tension de référence (VREF); caractérisé en ce que ledit circuit comprend, en outre, un moyen de commande de validation (4 à 6, 29) connecté auxdites première et seconde lignes d'alimentation (8, 9) et audit moyen de comparaison (2) afin de désactiver ledit moyen de comparaison et d'activer ledit moyen de commutation (30) lorsque lesdites première et seconde tensions d'alimentation différent d'une valeur inférieure à un seuil prédéterminé.
  2. Circuit selon la revendication 1, caractérisé en ce que ledit moyen de commande de validation (4 à 6, 29) comprend un premier commutateur commandé (4) situé entre ladite seconde ligne d'alimentation (9) et ledit moyen de comparaison (2) et dont la borne de commande est connectée à ladite première ligne d'alimentation (8).
  3. Circuit selon la revendication 1 ou 2, caractérisé en ce que lesdits moyens formant source (3) sont connectés à ladite seconde ligne d'alimentation (9) par l'intermédiaire d'un deuxième commutateur commandé (5) situé entre ladite seconde ligne d'alimentation et ledit moyen formant source et dont la borne de commande est connectée à ladite première ligne d'alimentation (8).
  4. Circuit selon l'une quelconque des revendications 1 à 3 précédentes, caractérisé en ce que ledit moyen de comparaison (2) comprend un circuit différentiel (10, 11) présentant une borne de sortie (14) connectée à la borne de commande d'un transistor de sortie (27), ledit transistor de sortie étant connecté entre ladite seconde ligne d'alimentation (9), par l'intermédiaire d'un troisième commutateur commandé (29), et une ligne de potentiel de référence.
  5. Circuit selon les revendications 2 à 4, caractérisé en ce que chacun desdits premier, deuxième et troisième commutateurs commandés (4, 5, 29) comprend un transistor MOS à canal P; et ledit transistor de sortie (27) comprend un transistor MOS à canal N.
  6. Circuit selon l'une quelconque des revendications 1 à 5 précédentes, caractérisé en ce que ledit moyen de commande de validation (4 à 6, 29) comprend un étage inverseur différentiel (6) présentant une première et seconde entrées connectées respectivement à ladite première et à ladite seconde ligne d'alimentation (8, 9), et une sortie (28) connectée à ladite borne de commande dudit moyen de commutation (30).
  7. Circuit selon la revendication 6, caractérisé en ce que ledit étage inverseur (6) comprend un premier et un deuxième transistor (35, 36) dont des premières bornes respectives sont connectées au même noeud (40), des deuxièmes bornes respectives sont connectées respectivement à ladite seconde ligne d'alimentation (9) et à une ligne de potentiel de référence, et des bornes de commande respectives sont connectées l'une à l'autre et à ladite première ligne d'alimentation (8); un élément inverseur (37) présentant une entrée connectée audit noeud (40), et une sortie; et un troisième transistor (38) présentant une première borne connectée à ladite borne de commande dudit moyen de commutation (30), et une borne de commande connectée à ladite sortie dudit élément d'inversion (37).
  8. Circuit selon la revendication 7, caractérisé en ce que ledit premier transistor (35) est un transistor MOS à canal P; et lesdits deuxième et troisième transistors (36, 38) sont des transistors MOS à canal N.
EP93830279A 1993-06-28 1993-06-28 Circuit de protection pour les dispositifs comprenant des mémoires non-volatiles Expired - Lifetime EP0631284B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP93830279A EP0631284B1 (fr) 1993-06-28 1993-06-28 Circuit de protection pour les dispositifs comprenant des mémoires non-volatiles
DE69314013T DE69314013T2 (de) 1993-06-28 1993-06-28 Sicherungsschaltungen für aus nicht-flüchtigen Speichem bestehenden Anordnungen
JP6139096A JPH07141894A (ja) 1993-06-28 1994-06-21 保護回路
US08/267,145 US5579196A (en) 1993-06-28 1994-06-27 Protection circuit for devices comprising nonvolatile memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93830279A EP0631284B1 (fr) 1993-06-28 1993-06-28 Circuit de protection pour les dispositifs comprenant des mémoires non-volatiles

Publications (2)

Publication Number Publication Date
EP0631284A1 EP0631284A1 (fr) 1994-12-28
EP0631284B1 true EP0631284B1 (fr) 1997-09-17

Family

ID=8215191

Family Applications (1)

Application Number Title Priority Date Filing Date
EP93830279A Expired - Lifetime EP0631284B1 (fr) 1993-06-28 1993-06-28 Circuit de protection pour les dispositifs comprenant des mémoires non-volatiles

Country Status (4)

Country Link
US (1) US5579196A (fr)
EP (1) EP0631284B1 (fr)
JP (1) JPH07141894A (fr)
DE (1) DE69314013T2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE503646C2 (sv) * 1994-11-10 1996-07-22 Ericsson Telefon Ab L M Automatisk omkopplingsanordning
DE19602456C1 (de) * 1996-01-24 1997-04-10 Texas Instruments Deutschland BiCMOS/CMOS-Schaltung
US6421213B1 (en) * 2000-03-17 2002-07-16 Advanced Technology Materials, Inc. Method and apparatus for detecting a tamper condition and isolating a circuit therefrom
CA2360117A1 (fr) * 2001-10-24 2003-04-24 Catena Networks Canada Inc. Utilisation de signaux de sonnerie de service telephonique de base sans perturbation des signaux de ligne d'acces numerique
JP4569541B2 (ja) * 2006-08-11 2010-10-27 Ｔｄｋ株式会社 電源回路、フラッシュメモリシステム及び電源供給方法
JP5348541B2 (ja) * 2009-05-20 2013-11-20 ルネサスエレクトロニクス株式会社 半導体装置
US8630139B2 (en) * 2011-11-30 2014-01-14 International Business Machines Corporation Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3044689C2 (de) * 1980-11-27 1982-08-26 Deutsche Itt Industries Gmbh, 7800 Freiburg Integrierte Schaltung mit nichtflüchtig programmierbaren Halbleiterspeichern
US4975878A (en) * 1988-01-28 1990-12-04 National Semiconductor Programmable memory data protection scheme
US4975883A (en) * 1990-03-29 1990-12-04 Intel Corporation Method and apparatus for preventing the erasure and programming of a nonvolatile memory
JP2778199B2 (ja) * 1990-04-27 1998-07-23 日本電気株式会社 内部降圧回路
US5199032A (en) * 1990-09-04 1993-03-30 Motorola, Inc. Microcontroller having an EPROM with a low voltage program inhibit circuit
US5371709A (en) * 1993-04-01 1994-12-06 Microchip Technology Incorporated Power management system for serial EEPROM device

Also Published As

Publication number Publication date
US5579196A (en) 1996-11-26
JPH07141894A (ja) 1995-06-02
DE69314013D1 (de) 1997-10-23
DE69314013T2 (de) 1998-02-19
EP0631284A1 (fr) 1994-12-28

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