EP0598030A1 - Reseau de commutation et d'acheminement de messages sans blocage, a acheminement autonome et pouvant etre mis a l'echelle - Google Patents

Reseau de commutation et d'acheminement de messages sans blocage, a acheminement autonome et pouvant etre mis a l'echelle

Info

Publication number
EP0598030A1
EP0598030A1 EP92917766A EP92917766A EP0598030A1 EP 0598030 A1 EP0598030 A1 EP 0598030A1 EP 92917766 A EP92917766 A EP 92917766A EP 92917766 A EP92917766 A EP 92917766A EP 0598030 A1 EP0598030 A1 EP 0598030A1
Authority
EP
European Patent Office
Prior art keywords
switches
stage
crossbar
message
set forth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92917766A
Other languages
German (de)
English (en)
Inventor
Aloke Guha
Michael B. Atlass
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Publication of EP0598030A1 publication Critical patent/EP0598030A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/64—Distributing or queueing
    • H04Q3/68—Grouping or interlacing selector groups or stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1515—Non-blocking multistage, e.g. Clos
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/201—Multicast operation; Broadcast operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane

Definitions

  • This invention relates to a self-routing, non-blocking switch system for routing messages from any one of a number of inputs to any one of a number of outputs in an efficient and cost effective manner.
  • any system or subcomponent thereof which allows for ease of routing messages from any of a large number of inputs to any particular one of a large number of outputs is important.
  • the invention described herein allows for the routing of such messages with very little overhead, at high speed.
  • the invention herein employs a return network, is capable of using different kinds of switches in the switching network, may operate in a broadcast mode, may reduce the number of switches necessary by using a Clos network or by reliance on busses and controllers, and uses a self-routing algorithm, eliminating the need for preprocessing overhead.
  • Self-routing algorithms use information contained in the message itself to route the message at the switch level to the desired location.
  • Clos networks are preferred for larger networks because they reduce the number of switches necessary to accomplish a N x N message switching system to a much smaller number than N ⁇ . See, for example, U.S. Patent No. 4,696,000, issued to Payne, which refers to the Clos network and rearrangeable networks.
  • the switches may be arranged in a standard crossbar network for small scale implementations, a Clos network or a variation of a Clos network using busses, and the types of switches and routings, dependent on the switch type used, may also vary depending on the implementation.
  • a preferred implementation employs a return network for all blocked messages that wish to address the same output node and returns them to the source or sending node. Due to the nature of the routing system itself and the construction of the switching network, essentially no overhead or preprocessing is required to route messages through the system described from the input nodes to the output nodes.
  • Fig. 1 is a two-dimensional layout of the switches in an N x N crossbar.
  • Fig. 2 is a block diagram of a trap network for removing connection request conflicts.
  • Fig. 3 is a layout of a second implementation of an n by m crossbar.
  • Fig. 4 is a layout of a n by m crossbar with an associated return network.
  • Fig. 5a is a schematic diagram of 2 x 2 crossbar switch.
  • Fig. 5b is a diagram of a gate-level implementation of the switch described in Fig. 5a.
  • Fig. 6a (i), (ii), and (iii) are three possible modes of operation of the 2 x 2 broadcast switch.
  • Fig. 6a is a diagram of a gate-level implementation of a broadcast switch.
  • Fig. 7 is an electronic-level diagram of an implementation of a crossbar switch.
  • Fig. 8 is a 36 x 36 Clos network diagram.
  • Fig. 9 is a 16 x 16 Clos network diagram.
  • Fig. 10 is a layout of a non-blocking nr x nr self-routing Clos network with return networks.
  • Figs. 11a, b and c are diagrams of the inputs and outputs of the crossbars used in Fig. 10.
  • Fig. 12 is a schematic diagram of the bus implementation of a truly non-blocking network in accord with the invention.
  • Fig. 13 is a block diagram of a finite-state machine model of the bus controller which may be used with the invention as described in Fig. 12.
  • Fig. 14 is a detailed schematic diagram of the databus controller blocks employed in one of the 2n-l databus controller blocks used with the invention as described with reference to Fig. 12.
  • Fig. 15 is a drawing of a complete 4 x 4 crossbar with associated return net.
  • This invention teaches a truly non-blocking switching network for use as a messaging system which has a plurality of stages, at least the first and last stages comprising a multiplicity of crossbars, which may be called "units".
  • Each crossbar in the first stage can switch messages having headers with source and destination addresses and an associated turn signal indicator means for each.
  • the crossbar has a number of inputs, n, and a number of outputs, m, wherein the m inputs are connected by an n X m array of 2 X 2 switches organized into logical columns and logical rows labeled 1 to m and 1 to n, respectively, and wherein said switches are connected between said n input sources and m outputs-
  • the switches may be set into a pass or exchange mode based on the coincidence of two events, first that the message header source address matches the column address of the switch, and second, that the turn signal has not already been reset by a previous switch having a matching column address.
  • Each last stage crossbar or "unit” is of similar size and organization to each said first stage crossbar, except that the last stage crossbars have m inputs and n outputs.
  • Each stage has some number r which is the number of crossbars in the first and last stages.
  • the m outputs of each of the first stage crossbars are routed through the intermediary stage or stages to the m inputs of the last stage crossbars. For each output of the first stage there is a return path for the messages sent via said first stage outputs to subsequent stages.
  • the return network operates to return messages that attempt to route themselves to outputs which are already occupied. This re-routing or routing back is automatic, and takes less time than a time-out, especially in larger networks, to inform the sending node that the message has not gotten through. (A timeout is a counter or timer that waits some increment longer than the maximum delay, and upon finding the time expired or the counter full, a new action is begun.)
  • TABs Trusted Non-Blocking Networks
  • TNBs can provide for practical implementation for high speed and high band width applications using a distributed local routing control. (They are principally oriented toward electrical switching but additional benefits can be gained using optical switching, such as no separate line being required for a return signal.)
  • the crossbar switch in general can be thought of as a square or rectangular two-dimensional array connecting a set of inputs to an equal or, if rectangular, unequal, number of outputs.
  • a crossbar has NM crosspoints and can simultaneously provide any combination of input and output one-to-one connections in a non-blocking manner.
  • other methods besides using an array of switches, where each switch represents a crosspoint, have been used. These include for example, in electronics, bus arbitrated architecture used to simplify the quadratic complexity of switches and control and, in optics, outeiproduct matrix multiplying architectures have been used.
  • the primary approach here is to use switch level design for self-routing.
  • a TNB that requires less switches than are required in a crossbar was first proposed by Clos in A Study of Non-Blocking Switching Networks. Bell . System Technical Journal, 32, pp. 406-424, 1953.
  • the number of switches which would be required for a Clos network would be on the order of N x N, when a comparably sized crossbar would be N x N.
  • networks of more than three stages can be built from three-stage networks by successively replacing the center-stage by another three-stage CN.
  • the size of a crossbar can be designated with the sequence (n,m,r).
  • the Clos network will be truly non-blocking if m ⁇ 2n-l.
  • the CN is not truly non-blocking but may be rearrangeably non-blocking if m ⁇ 2n-l.
  • Fig. 1 in which a simple crossbar network (10) is shown.
  • each one of the 2 x 2 switches may be labeled as points in a matrix or, 1,1 to n,m.
  • the switches may be labeled with their column address only since this is the one which will be compared with the message header as will be explained later.
  • a Clos network is drawn for a 36 x 36 array of inputs to outputs.
  • the network is comprised of 6, 6 x 11 crossbars in column 1, plus 11, 6 x 6 crossbars in column 2, plus another 6, 11 x 6 crossbars in column 3.
  • an input on line 81 may be directed at switch or crosspoint 82 to connect to the first top line 83 of crossbar 84 in column 2, row 1, which may again be directed by switch 85 to output 86 of the same crossbar, connecting it to input 87 of crossbar 88. At this point it may only be routed to one of the six outputs of crossbar 88 by one of the six switches in that column of crossbar 88. It will occur to the reader at this point that three crosspoints are involved in transferring the message from input 81 to one of the outputs in crossbar 88.
  • the Clos network it will also be noted, is generally constructed having square root of N rows (plus m rows of center crossbars, not labeled) by three columns.
  • the network may be expanded and the number of switches further reduced by splitting the central portion into three in accordance with the teachings of Clos.
  • Fig. 2 in which a trap network scheme is used to remove connection request conflicts before they happen, according to the design 20. This design is avoided by the invention.
  • L Fig. 2 inputs 1-n are provided to a parallel sorting network 21 and provided, sorted, to a comparator stage 22.
  • the comparator stage 22 provides an indication of a conflict to the duplicate router stage 23 along with each message being passed.
  • the duplicate router stage 23 returns messages, along lines 24 or 25, to the inputs prior to the sorting network a, to be handled in accordance with whatever scheme is desired.
  • either the message header itself may go back to the input node where the message header and the message may be directed to a buffer, or any number of other things may be desired for messages which may require resending at some other time.
  • the crossbar 27 then allows its switches to be set in accordance with the instructions carried in the header which indicate the output address for each message routed through it. Using the teachings described herein, such an implementation, including units 21, 22, 23 and outputs 24 and 25, is not required. Switches
  • the basic 2 x 2 switch can be seen in Fig. 5a, 50, as having two inputs, IN 1 and IN 2, and two outputs, OUT 1 and OUT 2. It may be generally set in either a pass or exchange mode. Under the pass mode, lines 51 and 52 will be open and lines 53 and 54 will be closed. In the exchange mode, the reverse is true.
  • Fig. 5b the switch 50 is shown in logic diagram form.
  • the "change" in input 55 will control whether the switch is in the pass or exchange mode.
  • OUT 1 is open to 1 1 and closed to 12
  • OUT 2 is open to 12 and closed to 1 1.
  • OUT 1 is open to IN 2
  • OUT 2 is open to IN 1.
  • Fig. 6a three modes of operation of a broadcast switch logical connection are shown, i, ii, and iii.
  • mode i one input may be connected to both outputs.
  • mode ii the inputs are connected to their direct outputs.
  • mode iii the inputs are connected to their crossed outputs.
  • Fig. 6b a gate-level implementation of such a switch is shown.
  • the switch may be redesigned to eliminate broadcast conditions if desired. As is also true with the gate-level implementation of the switches described previously, this switch may be designed differently as is well known to those of ordinary skill in the art.
  • this invention requires reference to the intended address of the message. Thus, it requires a device similar to that described with reference to Fig. 7, 70, which contains the 2 x 2 switch, sw.
  • Input data containing the address is received by the crossbar switch device 70 across datalines 71 and 72.
  • a serial or parallel input may be desired.
  • a delay buffer 73a and 73b is provided before th data reaches the switch sw.
  • the address label part of the message is read into the address comparator 74 at line 75.
  • the signal output by comparator 74 on line 75 is positive if the switch address matches the appropriate part of the destination address.
  • Such a positive signal on line 75 latches And-gate 78. In this way, if the And 78 is not disabled by line 76 or reset by a signal from line
  • control output will provide input C to switch sw.
  • the C signal also changes the output on 77a from “turn” to "no-turn” by means of latched And
  • the switches should all have a default setting, either pass or exchange, and all should be set in that mode when beginning to make any connections.
  • the default setting is exchange.
  • the default settings and switches could all be reversed and appropriate adjustments made to accommodate the reversed order. Such adjustments would be principally to reverse the input lines to each switch. The switch itself may require redesign.
  • the header having a destination address will be routed along the row corresponding to the source from which i is sent. Thus, if it enters from input port or node 1, it will be routed along switches 1,1; 1,2; 1,3; ... l,m.
  • the message will be accompanied with a separate, active signal which will be denoted for the purposes of this explanation "turn".
  • the label on the switch will be compared with the destination address in the header of the message at each switch at which the message arrives. If they are the same and the turn signal is high, the switch will be set into, for example, the pass mode, and the turn signal will be reset by the switch (see Fig. 7). If a destination label or indicator does not match the address of the switch, or if the turn signal is low, the switch will remain in the default mode (in the preferred embodiment, the case exchange mode). Thus, if a message is to be transferred from node 1 to output node 3, at switch 1,1, it will be told to exchange to switch 1,2 across line a'. The turn signal will not have been reset since it is to continue to travel across this row. No match has been made so the switch will remain in an exchange condition.
  • a network 30 is shown having nearly the identical layout as the network of Fig. 1. The difference here is that each one of the input nodes broadcasts its message across all of the columns of switches so that each one may compare its address at the same time, providing for muc faster connections. These broadcast lines are indicated as lines 31-34. Return Networks
  • the key concept for eliminating the need for a conflict resolution device is the provision of the return network for each input node or line.
  • a simplified implementation is described with reference to Fig. 4 in which a crossbar network 40 and an associated return net 41 are shown.
  • a modification is also required in the header: both the destination address and the source address are required in order to route back the message which has found a conflict.
  • Each should also have its own turn signal.
  • the first part of the header should contain the destination address in the preferred embodiment. Thus, for a message from node 1, it is 1 ' of 1 to m outputs. If all goes well, the header routes itself to the proper output as described previously.
  • the header will be diverted to the return network 41.
  • input node 42 using input line 1 and a second input node using input line 2 have connection requests for output node 3 (and thus send messages with headers to node 3).
  • the header from the second node for example, reaches the switch 2,3 before the header from node 42, if the two headers are clocked out together.
  • switch 2,3 will be set (in the preferred embodiment) into the pass mode by the header from the second node and, therefore, the header from node 42 (input line 1) on arriving at node 2,3 will be routed through switch 2,n into the return net 41.
  • the switches in the return net will look only at the source address part of the header and its associated turn signal. Since the source has sent a message request, it should not be busy when it receives the request back, in this case across line 44. To get there it will have come through switch s from switch t.
  • the routing through the switches in the return net may work exactly the same way as in the forward net, with a separate turn signal for the sending address, which is only reset when the switch address matches the origin address, and it then stays in reset condition through the switches in that (diagonal) return switch line until the header with its message (if any) is returned across one of the long horizontal lines in the crossbar (see Fig. 15).
  • FIG. 9 illustrates a crossbar network similar to that illustrated in Fig. 8 but smaller.
  • Each input line Cl has an address, in this network being a 16 X 16 Clos network there addresses being (for base 10, 1 through 16 but as shown) for base 2, 0000 through 1111.
  • the destination addresses in column C3 have the same designation and C3 is likewise comprised of the same number of crossbar switches.
  • C2 has a greater number of smaller crossbar switches in accordance with the requirements of a Clos network. (The crossbars in columns Cl and C3 are of size n by 2n-l).
  • the number of crossbar switches in Cl and C3 is not a power of 2 (thus r is not a power of 2) the number should be increased until a power of 2 is achieved.
  • the number of bits and the label for each address is
  • no switches are considered latched thus they are all in the pass position.
  • the header containing the destination address is routed following the self-routing algorithm described above for the first column.
  • the destination address will be made up of two parts: the output crossbar address of
  • the algorithm is termed greedy in that any unused column may be used for routing.
  • the address 00— was free and a connection made on 91 to the second stage crossbar is C2.
  • the other message that wants this crossbar is coming in on 92. If they are going to different final crossbars as shown, across lines 93 and 94 there is no problem, otherwise the second message through will be blocked and have to be rerouted. This is why the greedy algorithm was created.
  • stage 1 and 3 conflicting requests due to true input request conflicts (where two input requests specify the same output address) are returned to the source node.
  • Crossbars l a to r a establish the first stage, 1 ⁇ to 2n-l jj the second and l c to r c the third.
  • Each has a return net 102 , similar to the one described in detail with reference Fig. 15.
  • Switch 3 in the first row is still held in the pass mode and the network message is routed through across to the return net.
  • the return net routes the message back to node 2. (All switches, once changed from the default state, should be held in that state for the maximum delay required for the message to return if blocked at the last stage.)
  • M2 then would be routed through the second row, 4th column switch, into the return net which would forward the header back to node 2, using the return address.
  • destination address can then be incremental and the header resent.
  • Figs. 11a, b, and c detail the number of lines used in each of the crossbars of Fig. 10.
  • the header's destination address is simply incremented and the header reset to try the next second stage switch.
  • the incrementing is only done to the first part of the destination address, however. So, for example, (with reference to Fig. 9 assuming it has return nets), if output node at receiving address 0000 wants to send a message to a receiving node at 0000, the incrementing can be done to the first two digits of the 0000 address, making the next attempt through line 01-of crossbar 95.
  • Clos networks having an intermediary stage or set of stages of crossbars, they can use busses for routing messages. This embodiment further reduces the number of switches but adds complexity in that it requires bus controllers.
  • Fig. 12 in which a network 120 is shown having again 1 through r crossbars with return nets for both the first and third stages. Again, as in Fig. 10, the return lines are shown attached near the sending line even though they are located as described with reference to Fig. 15 on the side opposite the output.
  • the difference in structure between this Fig. and Fig. 10 is that there are 2n-l controllers 121 j - 12l2 n _i- Each controller itself has a set of r data bus controllers 121 ⁇ - 121 ⁇ .
  • a signal or message sent from node 1 of crossbar 123 passes on output line 1 to Data and Bus Controller 121 Id * If the message is supposed to go to crossbar 124, for one of its 1 to
  • a bus controller 140 is shown. This is essentially an exploded view of the box labeled 121 j in Fig. 12. However, the diagram also illustrates a variation in embodiments in which a demultiplexer is used rather than an input and output line from and to each one of the first stage crossbars and their return networks.
  • the input data coming in on line 141 is demultiplexed by looking at the destination address, first part, and the request is sent to one of the bus control units, say bus control 1.
  • Bus control 1 then needs to seize databus 1 in order to send the message as data across the data line to databus 1. To do so it first checks the status of bus status 1 to determine if databus 1 is busy.
  • Inputs Parallel Input Data/Header bus, the Bus Status (0/1), and the Next_Stage Response, a single packet of data equal to the bus width, usually a header bit, and the source and destination addresses sent back from the next stage.
  • the input Data/Header always contains 2 reserved bits for routing.
  • bus lines are tri-state (low, high, high impedance) to distinguish between no signal and O-valued signal.
  • Input Data/Header bit 00 /"'leading bit denotes header or message packet*/
  • this implementation in routing through the second stage assumes that the source node operates in two modes: first it sends out the requesting header packet. If the response received from the routers is negative, it retransmits the headers until it obtains a connection. Second, if a positive response is received, the source node transmits its message in packets until it frees all the latches switches in the crossbars or the busses it had used. Routing Delays
  • the worst case delay in setting up the routing path in this implementation is 0(2n+nlog2r).
  • the switching delay is smaller since no conflicts have to be further resolved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

On décrit un ensemble de structures de réseau permettant l'acheminement de messages, sans blocage, à travers des systèmes de commutation très importants. Des structures Clos et Crossbar sont utilisées. Des voies de retour sont utilisées pour indiquer la présence de messages bloqués (dus à des noeuds de sortie ou des noeuds de réception occupés). Lorsqu'il rencontre un noeud occupé, le message peut être réacheminé à travers d'autres voies dans le réseau. Un modèle permettant d'utiliser des bus pour une partie du réseau est aussi décrit.
EP92917766A 1991-08-05 1992-08-05 Reseau de commutation et d'acheminement de messages sans blocage, a acheminement autonome et pouvant etre mis a l'echelle Withdrawn EP0598030A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US74026391A 1991-08-05 1991-08-05
US740263 1991-08-05
PCT/US1992/006651 WO1993003580A1 (fr) 1991-08-05 1992-08-05 Reseau de commutation et d'acheminement de messages sans blocage, a acheminement autonome et pouvant etre mis a l'echelle

Publications (1)

Publication Number Publication Date
EP0598030A1 true EP0598030A1 (fr) 1994-05-25

Family

ID=24975747

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92917766A Withdrawn EP0598030A1 (fr) 1991-08-05 1992-08-05 Reseau de commutation et d'acheminement de messages sans blocage, a acheminement autonome et pouvant etre mis a l'echelle

Country Status (4)

Country Link
EP (1) EP0598030A1 (fr)
JP (1) JPH06509917A (fr)
CA (1) CA2113725A1 (fr)
WO (1) WO1993003580A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104243354A (zh) * 2014-10-09 2014-12-24 福建星网锐捷网络有限公司 Clos网络的链路分配方法及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1156369B (it) * 1982-06-22 1987-02-04 Cselt Centro Studi Lab Telecom Rete di commutazione pcm modulare e autoinstradante con comando di in stradamento su canale virtuale per autocommutatori telefonici a comando distribuito
JPS61214694A (ja) * 1985-03-18 1986-09-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション データ伝送のスイッチング装置
US4725835A (en) * 1985-09-13 1988-02-16 T-Bar Incorporated Time multiplexed bus matrix switching system
US4706240A (en) * 1985-11-29 1987-11-10 American Telephone And Telegraph Co., At&T Bell Labs Switching system having multiple parallel switching networks
US4696000A (en) * 1985-12-12 1987-09-22 American Telephone And Telegraph Company, At&T Bell Laboratories Nonblocking self-routing packet and circuit switching network

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9303580A1 *

Also Published As

Publication number Publication date
JPH06509917A (ja) 1994-11-02
CA2113725A1 (fr) 1993-02-18
WO1993003580A1 (fr) 1993-02-18

Similar Documents

Publication Publication Date Title
US5319639A (en) Crossbar with return net for scalable self-routing non-blocking message switching and routing system
US6999466B2 (en) Switching concentrator
KR100211123B1 (ko) 고속 패킷 스위칭을 위한 다단 상호 연결 망
US5687172A (en) Terabit per second distribution network
EP0405208B1 (fr) Réseau à plusieurs étages avec commande répartie
US5654695A (en) Multi-function network
JP2963316B2 (ja) パケット分配ネットワーク
WO1986002511A1 (fr) Equilibrage de la charge pour noeuds de commutation par paquets
JP2918772B2 (ja) パケット交換配置
JP2915260B2 (ja) パケット交換配置
US6992984B1 (en) Credit-based adaptive flow control for multi-stage multi-dimensional switching architecture
Hui Switching integrated broadband services by sort-banyan networks
EP0598030A1 (fr) Reseau de commutation et d'acheminement de messages sans blocage, a acheminement autonome et pouvant etre mis a l'echelle
JP2004511992A (ja) 複数の制御回線を用いた多重最小論理網においてスループットを増大させる拡張可能な装置および方法
KR0170493B1 (ko) 다중 프로세서 시스템을 위한 논블록킹 결함허용 감마 연결망
WO1993003581A1 (fr) Structure de message pour systeme d'acheminement et de commutation de message, sans blocage, a acheminement autonome et pouvant etre mis a l'echelle
WO1993006676A1 (fr) Reseaux a commutation rapide de paquets/circuits point a point sans blocage
JP3079068B2 (ja) Ａｔｍスイッチ
Chen et al. RC-BB switch: a high performance switching network for B-ISDN
JP3186686B2 (ja) Ａｔｍスイッチ
JP2756604B2 (ja) 自己ルーチングスイッチ網
Yan et al. A large scale ATM switch system using multi-channel switching paradigm
Gu Nonblocking conditions for self-routing Benes network
JPH01177744A (ja) パケット交換方式
JPH0336844A (ja) パケット通信方式

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19940301

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 19960430

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Withdrawal date: 19960817