EP0550163A1 - Architecture de circuit pour l'opération à canaux multiples d'accès direct en mémoire - Google Patents
Architecture de circuit pour l'opération à canaux multiples d'accès direct en mémoire Download PDFInfo
- Publication number
- EP0550163A1 EP0550163A1 EP92311130A EP92311130A EP0550163A1 EP 0550163 A1 EP0550163 A1 EP 0550163A1 EP 92311130 A EP92311130 A EP 92311130A EP 92311130 A EP92311130 A EP 92311130A EP 0550163 A1 EP0550163 A1 EP 0550163A1
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- European Patent Office
- Prior art keywords
- channel
- data
- dual
- port memory
- interleave
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Definitions
- the present invention relates to data transfer operations in a computer system and more specifically, to direct memory access operations in a computer system.
- a central processing unit may transfer data to a network device while time-multiplexing data transfer activities with other devices to fully utilize the CPU.
- buffers are sometimes implemented as an intermediary between each device and the CPU to optimize data transfer rates of multiple devices. With buffers, data can be temporarily stored until the transfer resource is available or when the transfer destination is free. Implementing a buffer for each device creates a problem for an integrated circuit when there are more and more devices interacting with the CPU, as the more sophisticated systems often require. In an integrated circuit, the die-size limitation simply does not permit more and more buffers and their associated decode logic to be added.
- DMA Direct memory access
- I/O computer input/output
- DMA typically involves an additional module on the system bus.
- DMA module 100 such as shown in Figure 1 , is capable of emulating the CPU (not shown) and of taking over control of the system bus from the CPU.
- a DMA operation works as follows: when the CPU wishes to read or write a block of data, it issues a command to DMA module 100.
- the command includes information regarding whether a read 101 or write 102 is requested, the address 103 of the I/O device involved, the starting location in memory to read from or write to, and the number 105 of words to be read or written.
- the CPU then continues with other tasks because it has delegated this I/O operation to the DMA module, and the module will take care of the task.
- the DMA module thus transfers the entire block of data, one word at a time, directly to or from memory, without going through the CPU.
- the DNA module sends an interrupt signal 110 to the CPU. As such, the CPU only needs to get involved at the beginning and end of the transfer.
- the DMA module needs to take control of the bus in order to transfer data to and from memory. For this purpose, the DMA module must use the bus only when the CPU does not need it, or the DMA module must force the CPU to temporarily suspend its operation. Since the only function this DMA module performs is data transfer, the transfer sequence can be hard-wired into the module circuit. By fetching instructions at a much higher level, the use of band-width can be minimized. Since the DMA module has the capability of generating the address and control signals required by the bus, the DMA module is capable of performing I/O operations at full memory speed.
- DMA operations must also accommodate multiple-channel data transfers with a variety of devices.
- an independent buffer is allocated to a DMA channel.
- the "one-buffer-per-channel" approach becomes less desirable, if not totally impractical.
- a single buffer such as a first-in, first-out (“FIFO") buffer, may serve as an intermediary for the multiple-channel DMA operations, the FIFO still experiences the problem of bottlenecking when one channel needing all the data right away is blocked by another channel's data.
- FIFO first-in, first-out
- the present invention discloses a method and apparatus for transferring data through multiple DMA channels by interleaving the transfer sequences from different channels to achieve high band-width and efficient resource utilization. Also disclosed is a circuit architecture to be most advantageously used in conjunction with supporting multiple-channel DMA transfers to maximize band-width and system efficiency.
- the present invention discloses a method and apparatus for supporting multiple-channel DMA operations by splitting data transfers for each channel into sequences of data slices and interleaving the transfer on a slice-by-slice basis. While the control of transfer resources may be shifted among the DMA channels, the ordering of the data slices for each channel is preserved.
- the present invention also discloses a circuit architecture to be most advantageously used with the multiple interleaving DMA channels.
- the circuit architecture comprises a dual-port memory, channel sequencer, and channel interleave control.
- the dual-port memory stores slices of data to be transferred through the channels.
- a channel sequencer maintains the channel ordering of data slices in the dual-port memory.
- a channel interleave control unit allows channels to interleave their data transfers by monitoring the channel interleave size, current data transfer count and total transfer count per channel.
- a second channel is allowed to transfer data through the same medium as a first channel either when the first channel has reached its channel interleave size, or when the first channel has transferred its requested total transfer count, thus providing efficient bus utilization.
- the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary, or desirable in most cases, in any of the operations described herein which form part of the present invention; the operations are machine operations.
- Useful machines for performing the operations of the present invention include general purpose digital computers or other similar devices. In all cases there should be borne in mind the distinction between the method operations in operating a computer and the method of computation itself.
- the present invention relates to method steps for operating a computer in processing electrical or other (e.g., mechanical, chemical) physical signals to generate other desired physical signals.
- the present invention also relates to apparatus for performing these operations.
- This apparatus may be specially constructed for the required purposes or it may comprise a general purpose computer as selectively activated or reconfigured by a computer program stored in the computer.
- the algorithms presented herein are not inherently related to a particular computer or other apparatus.
- various general purpose machines may be used with programs written in accordance with the teachings herein, or it may prove more convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these machines will appear from the description given.
- the channel interleaving method and apparatus of the present invention allows multiple-channel transfers to proceed in an orderly and efficient manner by splitting the data transfer sequences into slices and interleaving the slices from different channels.
- the present invention also discloses a circuit architecture for supporting the interleaving channels such that sliced data are transferred through their respective channels.
- the channel interleaving method and apparatus thus achieves better bus utilization and higher band-width by interleaving other channels when the transfer resource is not used by one channel.
- interleaving channel method and apparatus may utilize other buffering scheme aside from the unique circuit architecture described.
- unique circuit architecture may be utilized in conjunction with other multiple-device transfers in addition to the interleaving method and apparatus of the present invention disclosed.
- a DMA controller module 220 facilitates data transfers among memory 240 and various peripheral units 250 by obtaining control of the system bus 200 when the CPU 210 is not using the system bus 200.
- Buffer 230 coupled to DMA controller module 220 provides data buffering for data transfers.
- an architecture capable of supporting multiple DMA channels will significantly enhance the performance of DMA operations among memory 240 and various peripheral units 250.
- a DMA request for transferring a total_transfer_count (“TIC") of data through channel M is made.
- the TTC is compared with a pre-determined channel_interleave_size ("CIS") of channel M to determine whether the transfer sequence should be split into two or more separate slices such that the slices from channel M may be interleaved with slices from another channel N wishing to use the same transfer resources. If the TTC from channel M is less than or equal to its CIS, the transfer is completed in one slice.
- CIS channel_interleave_size
- the CIS of a DMA channel specifies the amount of data the DMA channel needs to transfer before another DMA channel can interleave using the same transfer resources as the first DMA channel.
- channel M's TTC is within its CIS, the data can be readily transferred through in one slice.
- channel M's CIS is less than its requested TTC
- the transfer of TTC is split time-wise into multiple slices of CIS-size data, each of which can be transferred through the transfer resources.
- the control of transfer resources is made available for another slice of data from another channel to interleave.
- the control of the transfer resources can be passed to another channel with a higher priority by the channel's priority arbitration scheme, which may be on a rotating or a fixed basis. If another channel N gains control of the transfer resources after channel M's slice, a data slice from channel N can be transferred using the transfer resources.
- the control of the transfer resources will also pass from channel N to other channels with higher priority after each slice, if present.
- the control structure 300 comprises a dual-port memory 320 and a channel sequencer 330.
- the dual-port memory 320 writes and reads data for DMA data transfers and operates in a wrap-around fashion with read pointer 321 and write pointer 325.
- the write pointer 325 points to a data location in the dual-port memory 320 to be written to next.
- the write pointer 325 moves to a next location in dual-port memory 320.
- the read pointer 321 points to a data location in the dual-port memory 320 to be read next.
- data is read out of the dual-port memory 320 at the location pointed to by read pointer 321.
- the write pointer 325 is the leading pointer such that when two pointers coincide, or "bump up" against each other, the dual-port memory 320 is empty; and when write pointer 325 is located immediately behind read pointer 321, the dual-port memory 320 is full.
- the control 300 starts its operation with an empty state.
- the write pointer 325 should never pass the read pointer 321 such that valid data are not overwritten before they are read out of the dual-port memory 320.
- the channel sequencer 330 records DMA channel numbers associated with each DMA data transfer through the dual-port memory 320 such that channel sequencing corresponding to data buffered in the dual-port memory 320 is preserved when multiple channels are exercising DMA transfers with the dual-port memory 320.
- the channel sequencer 330 operates in a wrap-around fashion with a source pointer 331 and a destination pointer 335.
- the source pointer 331 writes a channel number to a location in the channel sequencer 330 representing the channel from which data are written.
- the source pointer 331 increments to a next location in the channel sequencer 330 to be ready for a next channel number to be written to.
- the destination pointer 335 initiates data transfer out of the dual-port memory 320 by pointing to a location in the channel sequencer 330 such that data are read out of the dual-port memory 320 into the channel indicated by the destination pointer 335 in the channel sequencer 320. Thus, data are written into and read out of the dual-port memory 320 in the same channel. It should be apparent to those skilled in the art that the source pointer 331 and the destination pointer 335 do not cross one another to avoid misdirecting data transfers.
- the source pointer 331 skips over and tags the location at tag 332 in the channel sequencer 330.
- the destination pointer 335 reads tag 332 to know that data transfer has not been performed by the source pointer 331 in relation to the tagged location of the channel sequencer 330.
- the destination pointer 335 does not cause data to be transferred out according to the tagged location, invalidates or resets the tag 332 and skips to transfer the channel in the next location. This is to ensure that the circuit architecture of the present invention does not transfer data out more than it has transferred in with respect to the same channel.
- the "skip-over" may occur when there is not enough room in the dual-port memory 327 to write data or when the bus is not available for transfer.
- the channel interleave control 310 allows channels to interleave their transfers by monitoring the channel interleave size, total transfer size and current transfer size for each channel in both write and read directions.
- the channel interleave size of each channel specifies the number of bytes a first channel must transfer before another channel can interleave its transfer using the same resource as the first channel.
- the total transfer size specifies the total number of data bytes a specific channel has been requested to transfer through the dual-port memory 320.
- the current transfer count records both current write and current read counts in progress for each channel with respect to data bytes buffered in the dual-port memory 320.
- the channel interleave control 310 determines the number of data slices the current transfer can be split into by reading that channel's channel interleave size and total transfer size. If data transfer can be split into more than one data slice, then the channel interleave control 310 can allow a second channel to execute its transfer after the first channel has transferred up to its channel interleave size.
- the channel interleave control also monitors the current transfer count of each channel in both write and read directions such that the circuit architecture of the present invention keeps track of how many data bytes it has transferred for each channel and how many more to transfer, in addition to when channel interleave can occur. As such, the circuit architecture of the present invention can proceed with transfers by executing data slice transfers from different channels in random orders until various DMA transfer sequences are complete because the channel ordering associated with the data slices is maintained by the channel sequencer 330 and channel interleave control 310.
- channel interleaving involves various transfer sizes, a situation arises when the channel transfer in one location of the channel sequencer 330 is completed before the channel transfer in another location. This situation causes the channel sequencer 330 to have randomly scattered gaps, although the channel sequencer 330 is initially loading channels sequentially through its source pointer.
- incoming channels are not allocated to locations which are between the source and destination pointers (i.e., behind the source pointer and ahead of the destination pointer). Thus, the new channels are not in the locations to be hit first by the destination pointer 335 and the sequence of the locations are preserved in the channel sequencer 330.
- the channel interleave control 310 determines whether data of less than that channel's channel interleave size is to be transferred, such as the remaining portion of a transfer ("remnant"), by comparing the channel interleave size with the difference between the total transfer size and current transfer count. If data of less than the channel interleave size is to be transferred through a channel, the channel interleave control 310 allows another channel to execute its transfer as soon as the first channel's transfer is complete so as to achieve better bus utilization. Also, where there is no other channel requesting data transfer after the first channel completes its transfer, the channel interleave control 310 allows the first channel to continue transfer or to respond to further request, whichever the case may be.
- the channel interleave control 310 can theoretically be a processor which processes information regarding the channel interleave size, current transfer count and total transfer size for each channel.
- a DMA transfer requests 1000 bytes of data through channel 1, which has been programmed to have a channel interleave size of 500 bytes on a host which supports up to 32-byte bursts.
- channel interleave size refers to the most data which will be transferred before another channel is allowed to transfer through the same bus.
- the transfer is to begin with the memory 400 through the ABus 460 to the dual-port memory 420 and from the dual-port memory 420 through the BBus 470 to its requesting peripheral unit 450.
- the channel interleave control 410 determines how to "slice up" the transfer by reading the channel interleave size, now 500 bytes, the total transfer count, now 1000 bytes, and the burst size, now 32 bytes, associated with channel 1. Thus, a 500-byte slice in 15 separate 32-byte bursts plus one 16-byte burst and one 4-byte transfer are written into the dual-port memory 420, while the channel sequencer 430 writes "channel 1" as the source channel corresponding to this slice of data.
- channel 1 After channel 1 has written the largest slice of data possible (500 bytes) without violating its channel interleave size of 500 bytes, another channel is allowed to use the ABus 460 to transfer data If a DMA transfer through channel 7, for example, has been granted to use the ABus 460, transfer through channel 7 can interleave at this juncture.
- a computer system may have multiple buffering architecture (not shown in Figure 4 ) to accommodate the DMA transfers such that another DMA channel may request to use a different buffering architecture to transfer.
- channel interleave control 410 continues maintaining channel 1's transfer parameters, i.e. channel interleave size, total transfer size, and current transfer count so that channel 1 may subsequently resume its transfer unaffected by channel 7's interleaving.
- Channel 7 Data transfer through channel 7 proceeds in a similar manner as in channel 1 with the exception that channel 7 may have been programmed to have different channel interleave size, total transfer size, and burst size such that the size of the data "slice" for channel 7 is different from channel 1.
- the channel sequencer 430 When a slice of channel 7 data is written from memory 400 to the dual-port memory 420, the channel sequencer 430 writes "channel 7" as the source channel corresponding to this slice of data written into the dual-port memory 420. If the next slice of transfer is also from channel 7, then channel 7 is written again as the source channel in the channel sequencer 430.
- the ABus 460 is free to whichever channel getting its request granted. Assuming channel 1 gets its request granted, channel 1 can resume its data transfer from the memory 400 to the dual-port memory 420. Another slice of data is written into the dual-port memory 420, while the channel sequencer 430 writes "channel 1" as the source channel.
- Figure 6 illustrates the current status of the dual-port memory 620 and channel sequencer 621.
- the write pointer 625 and read pointer 621 are initially lined up at the first location in the dual-port memory 620 and the source channel pointer 631 and destination channel pointer 635 are also lined up at the first location of the channel sequencer 630.
- channel 1 continues transferring its requested total transfer count by writing a second slice of 500 bytes into locations in the dual-port memory 620 beginning with location 689, suspending its transfer if another channel is allowed to use the bus after channel 1's channel interleave size is reached. If no interleave occurs, channel 1 continues writing the remaining data into the dual-port memory 620, while the channel sequencer 630 records "channel 1" as the source channel for each slice concurrently.
- a read pointer 621 is indicated coupled to the dual-port memory 620.
- the read pointer 621 and write pointer 625 operate independently of each other such that the dual-port memory 620 can be writing and reading simultaneously through its dual write and read pointer mechanism.
- data in the dual-port memory 620 are to be read out, they are read as the read pointer 621 moves along the dual-port memory 620.
- the destination of data is indicated by a destination channel pointer 635 coupled to the channel sequencer 630.
- data is read out of the dual-port memory 620 through its destination channel before the channel interleave size for that channel is violated.
- the destination channel pointer 635 increments to a next location in the channel sequencer 630, which indicates the destination channel of data to be read out of the dual-port memory 620 through the read pointer 621.
- read operations of the the dual-port memory 620 can also be interleaved to support multiple channels. Further, once the total transfer count is achieved in reading data out of the dual-port memory 620, another channel is allowed to read data out of the dual-port memory 620 even though the remaining transfer is less than its channel interleave size. Thus, more efficient bus utilization is achieved by not forcing the other channel to wait when there is no more data to transfer after the remnant is transferred.
- the dual-port memory 620 is implemented by two dual port random-access memory, as illustrated in Figure 5 .
- the circuit architecture can be readily applied to other multiple-device transfer operations.
- the circuit architecture can provide independent read and write operations continuously while maintaining the transfer sequence of each device.
- the transfer resource can be efficiently utilized.
- data for each device are stored in the dual-port memory, while a device identification is registered in the sequencer. Similar to the channel interleave mechanism, data transfer counts can be maintained to monitor the status of data flow for each device.
- the circuit architecture can achieve higher band-width and continuity of operation without the cost of silicon area required by all the individual buffers.
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/814,765 US5386532A (en) | 1991-12-30 | 1991-12-30 | Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels |
US814765 | 1991-12-30 |
Publications (2)
Publication Number | Publication Date |
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EP0550163A1 true EP0550163A1 (fr) | 1993-07-07 |
EP0550163B1 EP0550163B1 (fr) | 1999-08-04 |
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ID=25215952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP92311130A Expired - Lifetime EP0550163B1 (fr) | 1991-12-30 | 1992-12-07 | Architecture de circuit pour l'opération à canaux multiples d'accès direct en mémoire |
Country Status (5)
Country | Link |
---|---|
US (1) | US5386532A (fr) |
EP (1) | EP0550163B1 (fr) |
JP (1) | JP3273202B2 (fr) |
KR (1) | KR0142175B1 (fr) |
DE (1) | DE69229716T2 (fr) |
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WO2002079971A1 (fr) * | 2001-03-30 | 2002-10-10 | Nokia Corporation | Structure tampon d'unite centrale/interface programmable mettant en oeuvre une memoire ram a double acces |
EP1645967A1 (fr) * | 2004-10-11 | 2006-04-12 | Texas Instruments Incorporated | DMA multicanal avec tampon PEPS partagé |
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KR101685407B1 (ko) | 2010-07-29 | 2016-12-13 | 삼성전자주식회사 | 멀티코어 시스템을 위한 다이렉트 메모리 억세스 장치 및 다이렉트 메모리 억세스 장치의 동작 방법 |
US8447897B2 (en) * | 2011-06-24 | 2013-05-21 | Freescale Semiconductor, Inc. | Bandwidth control for a direct memory access unit within a data processing system |
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- 1992-12-07 DE DE69229716T patent/DE69229716T2/de not_active Expired - Fee Related
- 1992-12-28 JP JP35881392A patent/JP3273202B2/ja not_active Expired - Fee Related
- 1992-12-28 KR KR1019920025767A patent/KR0142175B1/ko not_active IP Right Cessation
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Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0668556A2 (fr) * | 1994-02-22 | 1995-08-23 | Motorola, Inc. | Système de mémoire de file d'attente et procédé |
EP0668556A3 (fr) * | 1994-02-22 | 1995-12-06 | Motorola Inc | Système de mémoire de file d'attente et procédé. |
WO1998035301A2 (fr) * | 1997-02-07 | 1998-08-13 | Cirrus Logic, Inc. | Circuits, systemes et procedes pour le traitement de multiples trains de donnees |
WO1998035301A3 (fr) * | 1997-02-07 | 1999-04-01 | Cirrus Logic Inc | Circuits, systemes et procedes pour le traitement de multiples trains de donnees |
US6055619A (en) * | 1997-02-07 | 2000-04-25 | Cirrus Logic, Inc. | Circuits, system, and methods for processing multiple data streams |
DE10050980A1 (de) * | 2000-10-13 | 2002-05-02 | Systemonic Ag | Speicherkonfiguration mit I/O-Unterstützung |
US7143211B2 (en) | 2000-10-13 | 2006-11-28 | Systemonic Ag | Memory configuration with I/O support |
WO2002079971A1 (fr) * | 2001-03-30 | 2002-10-10 | Nokia Corporation | Structure tampon d'unite centrale/interface programmable mettant en oeuvre une memoire ram a double acces |
US7054986B2 (en) | 2001-03-30 | 2006-05-30 | Nokia Corporation | Programmable CPU/interface buffer structure using dual port RAM |
EP1645967A1 (fr) * | 2004-10-11 | 2006-04-12 | Texas Instruments Incorporated | DMA multicanal avec tampon PEPS partagé |
US7373437B2 (en) | 2004-10-11 | 2008-05-13 | Texas Instruments Incorporated | Multi-channel DMA with shared FIFO |
Also Published As
Publication number | Publication date |
---|---|
KR0142175B1 (ko) | 1998-07-01 |
DE69229716T2 (de) | 2000-03-02 |
EP0550163B1 (fr) | 1999-08-04 |
KR930014067A (ko) | 1993-07-22 |
US5386532A (en) | 1995-01-31 |
DE69229716D1 (de) | 1999-09-09 |
JPH06266649A (ja) | 1994-09-22 |
JP3273202B2 (ja) | 2002-04-08 |
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