EP0547814B1 - Circuit symétrique de commande de ligne par réseau local ou similaire - Google Patents

Circuit symétrique de commande de ligne par réseau local ou similaire Download PDF

Info

Publication number
EP0547814B1
EP0547814B1 EP92311090A EP92311090A EP0547814B1 EP 0547814 B1 EP0547814 B1 EP 0547814B1 EP 92311090 A EP92311090 A EP 92311090A EP 92311090 A EP92311090 A EP 92311090A EP 0547814 B1 EP0547814 B1 EP 0547814B1
Authority
EP
European Patent Office
Prior art keywords
switches
outputs
line driver
driver
pairs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP92311090A
Other languages
German (de)
English (en)
Other versions
EP0547814A2 (fr
EP0547814A3 (en
Inventor
Robert Henry Leonowich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of EP0547814A2 publication Critical patent/EP0547814A2/fr
Publication of EP0547814A3 publication Critical patent/EP0547814A3/en
Application granted granted Critical
Publication of EP0547814B1 publication Critical patent/EP0547814B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40039—Details regarding the setting of the power status of a node according to activity on the bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks

Definitions

  • This invention relates to differential line drivers having two outputs.
  • Transmission on a wire pair is usually differential in nature to maximize the signal-to-noise ratio at the far end of the pair. What shape the signals "look like" when transmitted is usually contained by a template which is part of a local area network standard.
  • the transmitted pulse template sets the performance limitations on a transmitted pulse. Because the test load may be reactive and resistive, significant transmitted pulse over/undershoot and ringing can occur with prior art transmitters. The over/undershoot and ringing are usually considered undesirable and the standard places limits on them. Further, an undesirable common mode (DC) shift may occur with prior art transmitters.
  • DC common mode
  • US-A-4,121,118 discloses a bipolar signal generator for generating bipolar signals.
  • the generator includes a converter circuit which is composed of four AND gates and four transistors. One of input terminal of all of the AND gates is connected in common to a control signal supply line. The other input terminals of two of the AND gates are connected to a line and the other input terminals of the other two AND gates are connected to another line. Output terminals of the AND gates are connected to respective bases of the transistors. Collectors of the transistors are connected through a resistor to a direct current source. Emitters of the transistors are connected to ground. An emitter of a first transistor and a collector of a second transistor are connected to one terminal of a primary winding of a transformer and an emitter of a third transistor and a collector of a fourth transistor are connected to the other terminal of the primary winding.
  • a differential line driver embodying the invention has two outputs, first and second pairs of serially coupled switches, and first and second resistors.
  • Each of the first and second pairs of serially coupled switches have first and second outputs, a common output, and two corresponding inputs, the common outputs coupling to the two outputs of the driver.
  • the first resistor has two terminals, one terminal coupling to a first power source and the other terminal coupling to the first outputs of the pairs of switches.
  • the second resistor has two terminals, one terminal coupling to a second power source and the other terminal coupling to the second outputs of the pairs of switches.
  • the arrangement of the switches allows for differential transmission of data when the driver is enabled. When disabled, the switches are all closed, coupling the outputs of the driver together with small common mode shift.
  • switches 10, 11 and 12, 13 each make a pair of serially coupled switches with a common output coupled to the output of a differential driver 1.
  • the pairs of switches 10, 11 and 12, 13 have outputs connected together and to corresponding resistors 14, 15.
  • the resistor 15 couples to a first power source (V CC ) and resistor couples to a second power source (ground). It is understood that the second power source may be another voltage other than ground (zero volts).
  • Resistors 14, 15 may be on-chip or off-chip depending on the application and power dissipation considerations.
  • switches 10 and 13 are the same ( ⁇ ) as well as for switches 11 and 12 ( ⁇ ). This allows for the switches to be switched diagonally to send data differentially to load 20 through DC blocking capacitors 18. Differential switching involves switches 10, 13 open and close together while switches 11, 12 open and close together in complement to switches 10, 13. When driver 1 is disabled (idle), it is desirable to close all the switches 10, 11, 12, 13, thus coupling the outputs together without significant common mode shift.
  • Control of switches 10, 11, 12 and 13 is accomplished by exemplary means of gates 16 and 17.
  • the IDLE/ ACTIVE input (enable) signal is "low", (active)
  • signals on input D passes through gate 16 to control switches 10, 13 while the signals on input D are inverted by gate 17 to control switches 11, 12.
  • the switches 10-13 are diagonally switched, sending data on input D differentially. If, however, the IDLE/ ACTIVE input is "high” (idle), then both outputs from gates 16, 17 are " “high”, causing switches 10- 13 to be closed, as described above.
  • switch 10 is shown in FIG. 2.
  • switch 10 (as well as switches 11-13) is a CMOS transmission gate with transistors suitably sized to handle the current necessary to drive load 20 (FIG. 1) or any other predetermined load. It is noted that, depending on the application, single transistors may be used as a switch.
  • FIG. 1 An integrated circuit version of the driver 1 (FIG. 1) has been fabricated for application driving an AUI network. Resistance values for resistors 14, 15 are approximately 90 ohms. Such a driver 1, without a transformer, more closely met the 802.3 standards for AUI transmission than a prior art driver with or without the transformer 19.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Electronic Switches (AREA)

Claims (5)

  1. Etage d'attaque de ligne différentiel présentant deux sorties,
       des première et deuxième paires de commutateurs couplés en série (10, 11 ; 12, 13), chaque paire présentant des première et deuxième sorties, une sortie commune et deux entrées correspondantes, les sorties communes se couplant aux deux sortie de l'étage d'attaque ;
       une première résistance (14) dotée de deux bornes, une borne se couplant à une source d'énergie et l'autre borne se couplant aux premières sorties des paires de commutateurs (10, 11 ; 12, 13) ;
       une deuxième résistance (15) dotée de deux bornes, une borne se couplant à une deuxième source d'énergie et l'autre borne se couplant aux deuxièmes sorties des paires de commutateurs (10, 11 ; 12, 13), et caractérisé par :
       une circuiterie de commande (16, 17) couplée aux entrées des commutateurs et dotée d'une entrée de données et d'une entrée de validation, la circuiterie de commande servant à commuter les commutateurs (10, 11 ; 12, 13) en réponse à l'entrée de données lorsque l'entrée de validation est active et mettant l'ensemble des commutateurs (10, 11 ; 12, 13) sous tension lorsque l'entrée de validation est inactive.
  2. Etage d'attaque de ligne différentiel selon la revendication 1, dans lequel les entrées aux première et deuxième paires de commutateurs (10, 11 ; 12, 13) sont couplées ensemble de façon à ce que les commutateurs puissent être commutés diagonalement.
  3. Etage d'attaque de ligne différentiel selon la revendication 2, dans lequel les résistances (14, 15) présentent essentiellement la même valeur.
  4. Etage d'attaque de ligne différentiel selon la revendication 3, dans lequel la circuiterie de commande (16, 17) sert à commuter diagonalement les commutateurs lorsque l'entrée de validation est active.
  5. Etage d'attaque de ligne différentiel selon la revendication 3, dans lequel les commutateurs sont des portes de transmission.
EP92311090A 1991-12-18 1992-12-04 Circuit symétrique de commande de ligne par réseau local ou similaire Expired - Lifetime EP0547814B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/810,632 US5285477A (en) 1991-12-18 1991-12-18 Balanced line driver for local area networks or the like
US810632 1991-12-18

Publications (3)

Publication Number Publication Date
EP0547814A2 EP0547814A2 (fr) 1993-06-23
EP0547814A3 EP0547814A3 (en) 1995-04-12
EP0547814B1 true EP0547814B1 (fr) 2001-04-04

Family

ID=25204294

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92311090A Expired - Lifetime EP0547814B1 (fr) 1991-12-18 1992-12-04 Circuit symétrique de commande de ligne par réseau local ou similaire

Country Status (5)

Country Link
US (1) US5285477A (fr)
EP (1) EP0547814B1 (fr)
JP (1) JPH0563124U (fr)
KR (1) KR200155486Y1 (fr)
DE (1) DE69231763T2 (fr)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471498A (en) * 1993-04-15 1995-11-28 National Semiconductor Corporation High-speed low-voltage differential swing transmission line transceiver
US5752190A (en) * 1993-07-30 1998-05-12 Hughes Electronics Supervisory audio tone based carrier-to-interference measurement in a mobile cellular communication system
US5687321A (en) * 1994-12-28 1997-11-11 Maxim Integrated Products Method and apparatus for transmitting signals over a wire pair having activity detection capability
US5869988A (en) * 1997-03-25 1999-02-09 Marvell Technology Group, Ltd. High speed write driver for inductive heads
US6051990A (en) * 1997-11-13 2000-04-18 Quantum Corporation Asymmetric current mode driver for differential transmission lines
US6115468A (en) 1998-03-26 2000-09-05 Cisco Technology, Inc. Power feed for Ethernet telephones via Ethernet link
WO1999053627A1 (fr) 1998-04-10 1999-10-21 Chrimar Systems, Inc. Doing Business As Cms Technologies Systeme de communication avec un equipement electronique sur un reseau
JPH11330937A (ja) * 1998-05-13 1999-11-30 Rohm Co Ltd 信号伝達装置
US6480510B1 (en) * 1998-07-28 2002-11-12 Serconet Ltd. Local area network of serial intelligent cells
US6175255B1 (en) * 1998-11-23 2001-01-16 National Seniconductor Corporation Line driver circuit for low voltage and low power applications
JP3171175B2 (ja) * 1998-12-08 2001-05-28 日本電気株式会社 差動トライステート発生方法及び差動トライステート回路
US6956826B1 (en) * 1999-07-07 2005-10-18 Serconet Ltd. Local area network for distributing data communication, sensing and control signals
US6549616B1 (en) 2000-03-20 2003-04-15 Serconet Ltd. Telephone outlet for implementing a local area network over telephone lines and a local area network using such outlets
US6961303B1 (en) 2000-09-21 2005-11-01 Serconet Ltd. Telephone communication system and method over local area network wiring
TW480817B (en) * 2001-03-15 2002-03-21 Himax Opto Electronics Corp Data transmitter
US7248696B2 (en) * 2002-09-12 2007-07-24 International Business Machines Corporation Dynamic system bus encryption using improved differential transitional encoding
IL152824A (en) 2002-11-13 2012-05-31 Mosaid Technologies Inc A socket that can be connected to and the network that uses it
IL159838A0 (en) * 2004-01-13 2004-06-20 Yehuda Binder Information device
DE102004004488A1 (de) * 2004-01-26 2005-08-18 Siemens Ag Lokales Netz mit übertragerloser Signalübertragung
US20060035487A1 (en) * 2004-08-12 2006-02-16 Acer Inc. Flexible hybrid cable
JP4509737B2 (ja) * 2004-10-28 2010-07-21 株式会社東芝 差動信号生成回路および差動信号送信回路
JP4939339B2 (ja) 2007-08-20 2012-05-23 ルネサスエレクトロニクス株式会社 差動送信回路、差動受信回路、信号伝送回路および信号伝送システム
US8520348B2 (en) 2011-12-22 2013-08-27 Lsi Corporation High-swing differential driver using low-voltage transistors
US10031353B2 (en) * 2016-09-22 2018-07-24 Hewlett Packard Enterprise Development Lp Circuits with delay tap lines

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4121118A (en) * 1976-07-07 1978-10-17 Ohkura Electric Co., Ltd. Bipolar signal generating apparatus

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DK143627C (da) * 1978-10-30 1982-02-15 Rovsing A S Koblingskreds til overfoering af datasignaler med stor hastighed
US4337465A (en) * 1980-09-25 1982-06-29 Burroughs Corporation Line driver circuit for a local area contention network
US4615039A (en) * 1984-10-01 1986-09-30 National Semiconductor Corporation Data network driver
GB8912461D0 (en) * 1989-05-31 1989-07-19 Lucas Ind Plc Line driver
US5012384A (en) * 1990-02-20 1991-04-30 Advanced Micro Device, Inc. Load circuit for a differential driver
DE59007700D1 (de) * 1990-05-16 1994-12-15 Siemens Ag Digitalschaltung mit Potentialausgleich zwischen zwei Signalleitern.
US5077756A (en) * 1990-05-31 1991-12-31 Acculan Ltd. Data network line driver

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4121118A (en) * 1976-07-07 1978-10-17 Ohkura Electric Co., Ltd. Bipolar signal generating apparatus

Also Published As

Publication number Publication date
EP0547814A2 (fr) 1993-06-23
JPH0563124U (ja) 1993-08-20
KR930016683U (ko) 1993-07-29
EP0547814A3 (en) 1995-04-12
DE69231763D1 (de) 2001-05-10
DE69231763T2 (de) 2001-09-06
KR200155486Y1 (ko) 1999-09-01
US5285477A (en) 1994-02-08

Similar Documents

Publication Publication Date Title
EP0547814B1 (fr) Circuit symétrique de commande de ligne par réseau local ou similaire
US7176823B2 (en) Gigabit ethernet line driver and hybrid architecture
US6005438A (en) Output high voltage clamped circuit for low voltage differential swing applications in the case of overload
US5821796A (en) Circuitry for providing a high impedance state when powering down a single port node
EP0651541B1 (fr) Circuit téléphonique d'abonné pourvu d'un élément d'isolation galvanique pour engendrer les états d'ouverture et de fermeture de la ligne téléphonique
US4152541A (en) Full duplex driver/receiver
US4029971A (en) Tri-state logic circuit
EP0375979B1 (fr) Circuit d'attaque BICMOS pour circuits logiques CMOS à haute densité
CA2077602A1 (fr) Circuit mos a tension de sortie a faible excursion servant a executer un circuit ecl
US4974190A (en) Pass-through and isolation switch
US6307402B1 (en) Output buffer for driving a symmetrical transmission line
KR100379884B1 (ko) 3상태비디오버스구동장치및방법
GB2232547A (en) Amplifiers
US4567384A (en) Voltage offset producing circuit for use with a line receiver or the like
US5309036A (en) Driver circuit for an attachment unit interface used in a network system
JP3284015B2 (ja) 半導体集積回路
US20040201401A1 (en) Bi-directional impedance matching circuit
US20020000845A1 (en) Complementary current mode driver for high speed data communications
JP2911465B2 (ja) デジタル加入者制御器装置
US4678939A (en) Output circuit for signal transmission systems
CA1217843A (fr) Circuit de transmission a liaison numerique
JP3496072B2 (ja) 送受信回路
EP0766400B1 (fr) Etage de sortie supportant des surtensions extérieures appliquées sur sa sortie dans l'état haute impédance et non-alimenté
JP2998329B2 (ja) 半導体集積回路
JP3039834B2 (ja) ラインドライバ回路

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE ES FR GB IT

RAP3 Party data changed (applicant data changed or rights of an application transferred)

Owner name: AT&T CORP.

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE ES FR GB IT

17P Request for examination filed

Effective date: 19950929

17Q First examination report despatched

Effective date: 19980430

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE ES FR GB IT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20010404

REF Corresponds to:

Ref document number: 69231763

Country of ref document: DE

Date of ref document: 20010510

ET Fr: translation filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20011030

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20101221

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20120105

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20111222

Year of fee payment: 20

REG Reference to a national code

Ref country code: DE

Ref legal event code: R071

Ref document number: 69231763

Country of ref document: DE

REG Reference to a national code

Ref country code: DE

Ref legal event code: R071

Ref document number: 69231763

Country of ref document: DE

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20121203

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20121203