EP0525986A2 - Gerät mit schneller Kopierung zwischen Rasterpuffern in einem Anzeigesystem mit Doppel-Pufferspeichern - Google Patents

Gerät mit schneller Kopierung zwischen Rasterpuffern in einem Anzeigesystem mit Doppel-Pufferspeichern Download PDF

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Publication number
EP0525986A2
EP0525986A2 EP92305993A EP92305993A EP0525986A2 EP 0525986 A2 EP0525986 A2 EP 0525986A2 EP 92305993 A EP92305993 A EP 92305993A EP 92305993 A EP92305993 A EP 92305993A EP 0525986 A2 EP0525986 A2 EP 0525986A2
Authority
EP
European Patent Office
Prior art keywords
frame buffer
data
frame
display
output display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP92305993A
Other languages
English (en)
French (fr)
Other versions
EP0525986A3 (en
EP0525986B1 (de
Inventor
Curtis Priem
Bruce Mcintyre
Chris Malachowsky
Guy Moffat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of EP0525986A2 publication Critical patent/EP0525986A2/de
Publication of EP0525986A3 publication Critical patent/EP0525986A3/en
Application granted granted Critical
Publication of EP0525986B1 publication Critical patent/EP0525986B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Definitions

  • This invention relates to computer output display apparatus and, more particularly, to methods and apparatus for eliminating frame tearing from a computer output display through the use of inexpensive double buffering.
  • a typical computer system generates data which is displayed on an output display.
  • This output display is typically a cathode ray tube which produces a number of full screen images one after another so rapidly that to the eye of the viewer the screen will appear to display constant motion when a program being displayed is capable of producing such motion.
  • data is written into a frame buffer.
  • the frame buffer stores information about each position on the display which can be illuminated (each pixel) to produce the full screen image.
  • a display may be capable of displaying pixels in approximately one thousand horizontal rows each having approximately one thousand pixels. All of this information in each frame is written to the frame buffer before it is scanned to the display.
  • the frame When data describing an entire picture exists in the frame buffer, the frame may be transferred to the display. Typically, data is transferred from the frame buffer to the display pixel by pixel and line by line beginning at the upper left hand corner of the display and proceeding horizontally from left to right line by line downwardly to the lower right hand corner of the display. In order for the picture to appear continuous on the output display, the successive frames in the frame buffer must be constantly scanned to the output display at a rate of thirty frames per second or more.
  • VRAM video random access memory
  • Double buffering uses two complete frame buffers each of which may store one entire frame. Data is written to one frame buffer and scanned to the display from the other. In its simplest form, this is accomplished using a pair of VRAM frame buffers and multiplexing the data in one or the other to the display. In this form, data is never written to the frame buffer during the time its data is being scanned to the display. Once a frame has been completely written, it may in turn be scanned to the display and all further data written to the other frame buffer. Since data is never written to a frame buffer while its contents are being scanned to the display, frame tearing cannot occur.
  • This simple form of double buffering is somewhat expensive because it uses two entire VRAM frame buffers and includes control signal generating circuitry and a multiplexor for switching between the two frame buffers.
  • One of the primary aims of computer designers is to allow a number of individual programs to run on a computer and be displayed simultaneously on an output display of that computer.
  • a number of individual programs are displayed on a computer output display, each individual program appears in a window, typically a rectangular area of the screen which may be moved about, enlarged and reduced in size, and otherwise manipulated. If a number of programs can be run and displayed in a number of windows simultaneously, the work being accomplished using the computer may be accelerated.
  • information being written to the individual windows by the different individual programs will be written at different rates.
  • the information being directed to a window displaying real time video changes very rapidly while the information typed from the keyboard to a word processor program being displayed in another window changes much more slowly. Consequently, the rate at which frames are changed varies from program to program.
  • the simplest form of double buffering described above is very useful when a single program is being run on the output display.
  • this form of double buffering is insufficient.
  • the simple form of double buffering requires that the entire contents of each frame buffer be scanned to the display. If data is being written to a number of windows at asynchronous rates, then the timing at which writing occurs differs from window to window; and it is very difficult to adjust the timing of the writing so that writing does not occur to a frame buffer being scanned to the display.
  • an advanced form of double buffering has been used which adds another buffer called a window identification (ID) plane.
  • ID window identification
  • the window identification plane provides a storage position for each pixel displayed on the output display. Stored in these positions of the window ID plane are identifications of the window to which each pixel of data is related. Use of this plane allow pixels from any buffer to be selected for display at any time. Thus, the window ID plane may be used to scan to the display data from any window to which data is not being written at the time of the scan. Thus, this form of double buffering allows frame tearing to be eliminated where multiple active windows appear simultaneously on the output display.
  • This second form of double buffering is quite expensive because it not only uses two entire VRAM frame buffers and circuitry for controlling and multiplexing from the two frame buffers to the display, it also adds an ID plane containing memory for each pixel of the display and circuitry for selecting pixels to be displayed based on the windows in which they appear.
  • This form of double buffering is much less expensive than the other forms because a less expensive DRAM replaces one of the VRAM frame buffers and the control circuitry for multiplexing is eliminated.
  • This arrangement is also useful because it works well with software conforming to the X11 standard (X Windows) which does not expect to see more than a single frame buffer and stores information to be transferred to the frame buffer in a section of main memory. To this software, the DRAM frame buffer appears to be a portion of main memory.
  • the arrangement also offers the advantage that individual windows may be transferred from the invisible DRAM frame buffer to the VRAM frame buffer since the central processing unit may selectively control the areas to be transferred.
  • an output display system comprising a first frame buffer; a second frame buffer; means for transferring data from the second frame buffer to an output display device; means for controlling the transfer of data to each of the frame buffers, this last-mentioned means including means for writing new data only to the first frame buffer, and means for both reading data from the first frame buffer and writing the data read to the second frame buffer during the same operation.
  • the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind.
  • the present invention relates to apparatus and to method steps for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.
  • circuit 10 constructed in accordance with the prior art.
  • the circuit 10 includes only the rudiments of the circuitry required to provide data to an output display terminal used in a typical computer system. Other portions necessary for providing the operations of a computer are well known to those skilled in the art and are not shown in the figure. Illustrated are a central processing unit 12 which may control the operation of the entire computer system and which represents in Figure 1 circuitry for providing data to be display on an output display 14. In order to accomplish the transfer of the data from the central processing unit 12 to the output display 14, first and second frame buffers 16 and 17 are utilized.
  • double buffering data is written from the central processing unit 12 to one frame buffer and scanned to the display 14 from the other. In its simplest form, this is accomplished using a pair of VRAM frame buffers and multiplexing the entire frame of data in one of the frame buffers 16 or 17 to the display by means of a multiplexor 19. The data transferred by the multiplexor 19 is converted from digital to analog form by a digital-to-analog converter 20 and scanned to the display. In this form of double buffering, data is never written to a frame buffer 16 or 17 during the time data is being scanned to the display from that frame buffer.
  • the data in that frame buffer may in turn be scanned to the display; and new data may be written to the other frame buffer. Since data is never written to a frame buffer while its contents are being scanned to the display, frame tearing cannot occur.
  • one prior art arrangement has replaced the VRAM used in the frame buffer 16 with DRAM. Since DRAM is single ported, the frame buffer 16 does not provide an output which may be scanned directly to the display 14. Consequently, the lines from the frame buffer 16 to the multiplexor 19 (which are dotted in the figure) are eliminated. Since no output is transferred from the frame buffer 16 to the multiplexor 19, the multiplexor 19 (again shown in dotted outline) is also eliminated. With no multiplexor, the control circuitry for selecting one or the other of the frame buffers 16 or 17 to scan to the display 14 is also unnecessary and is eliminated. This substantially reduces the cost of the system.
  • All new data is written by the central processing unit 12 to the frame buffer 16. All data is scanned to the display 14 from the frame buffer 17. Once a frame stored in frame buffer 16 has been changed, the frame is transferred to the frame buffer 17. To accomplish this transfer, a control circuit 23 within the central processing unit 12 selects a portion of the frame buffer 16 to be read, typically thirty-two bits or some amount usually equivalent to the width of the bus. This data is read and latched into the central processing unit 12. This read typically requires three clock periods for row addressing and four clock periods for column addressing by the control circuit 23. The central processing unit 12 then writes the information read from the frame buffer 16 to the frame buffer 17. This again typically requires three clock cycles for row addressing by the control circuitry 23 in frame buffer 17 and three clock cycles for column addressing in that frame buffer.
  • the additional clock period for column addressing in reading frame buffer 16 during the read operation is actually necessary in order to provide a dead cycle on the bus between the reading by the central processing unit 12 of the frame buffer 16 and the following write cycle to the frame buffer 17 so that two devices are not accessing the bus simultaneously.
  • a total of thirteen or more clock cycles are required to transfer a given amount of information from the frame buffer 16 to the frame buffer 17 in this arrangement.
  • This transfer is repeated a sufficient number of times to transfer the desired amount of data (which may be as large as an entire frame) from the frame buffer 16 to the frame buffer 17.
  • this is a relatively slow process and, when copying entire frames, allows only approximately twenty frames to be transferred per second.
  • a typical display may be receiving information from the frame buffer 17 at a rate of seventy-six frames per second. The scan proceeds at approximately three times the rate of the write to the frame buffer 17.
  • this less expensive arrangement allows the scan to the display to catch up with the writing of data into the frame buffer 17 from the frame buffer 16 so that frame tearing may occur.
  • the arrangement 25 includes a central processing unit 27, a first frame buffer 28 which may be constructed of VRAM, a second frame buffer 29 which may be constructed of DRAM, a digital-to-analog converter 31, and an output display 33.
  • the arrangement 25 functions in the same general manner as does the least expensive arrangement of Figure 1. That is, all new data is written by the central processing unit 27 to the DRAM frame buffer 29. All data is scanned to the display 33 from the VRAM frame buffer 28. Once new data has been written to a frame stored in frame buffer 29, the frame is transferred to the frame buffer 28. To accomplish this transfer, the central processing unit 27 reads a selected portion of the frame buffer 29, typically thirty-two bits, and writes that data to the frame buffer 28. This process is accomplished over and over until the desired amount of data has been transferred.
  • the arrangement of the present invention transfers the data approximately four times as fast.
  • approximately eighty frames per second may be written to the frame buffer 28 from the frame buffer 29; and tearing of frames scanned to the display may be eliminated.
  • the arrangement 25 includes within the central processing unit 27 (or other device controlling the rendering into and reading from the frame buffers 28 and 29) a pair of individual control circuits 34 and 35.
  • the first of these circuits 34 controls the accessing of the frame buffer 29, and the second circuit 35 controls the accessing of the frame buffer 28.
  • both frame buffers 28 and 29 may be accessed simultaneously. Data is still written only to the frame buffer 29 by the central processing unit when rendering.
  • control circuit 34 selects the appropriate row and column addresses in the frame buffer 29, and the control circuit 35 selects the same row and column addresses in the frame buffer 28. Then the control circuit 34 reads the accessed data in the frame buffer 29 and places it on the bus where the information is written to the same accessed addresses in the frame buffer 28. The data is not latched into the central processing unit 27; and, consequently, no dead cycle is needed for bus turn around so that two devices are not attempting to access that bus simultaneously.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Image Input (AREA)
EP92305993A 1991-07-26 1992-06-29 Gerät mit schneller Kopierung zwischen Rasterpuffern in einem Anzeigesystem mit Doppel-Pufferspeichern Expired - Lifetime EP0525986B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US73668691A 1991-07-26 1991-07-26
US736686 1991-07-26

Publications (3)

Publication Number Publication Date
EP0525986A2 true EP0525986A2 (de) 1993-02-03
EP0525986A3 EP0525986A3 (en) 1993-07-21
EP0525986B1 EP0525986B1 (de) 1996-11-13

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EP92305993A Expired - Lifetime EP0525986B1 (de) 1991-07-26 1992-06-29 Gerät mit schneller Kopierung zwischen Rasterpuffern in einem Anzeigesystem mit Doppel-Pufferspeichern

Country Status (4)

Country Link
EP (1) EP0525986B1 (de)
JP (1) JPH06214549A (de)
KR (1) KR100196686B1 (de)
DE (1) DE69215155T2 (de)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1193671A2 (de) * 2000-09-27 2002-04-03 Mitsubishi Denki Kabushiki Kaisha Matrixanzeigegerät
EP1217602A2 (de) * 2000-12-04 2002-06-26 Nokia Corporation Aktualisierung von Rasterbildern in einem Anzeigegerät mit einem Bildspeicher
EP1355487A1 (de) * 2001-01-25 2003-10-22 Sony Corporation Gerät zum übertragen von daten
DE19654766B4 (de) * 1995-12-29 2004-11-18 Wyse Technology, Inc., San Jose Terminal für die Anzeige von Anwendungsinformationen in einer Fensterumgebung
US6873335B2 (en) * 2000-09-07 2005-03-29 Actuality Systems, Inc. Graphics memory system for volumeric displays
US7554551B1 (en) 2000-06-07 2009-06-30 Apple Inc. Decoupling a color buffer from main memory
WO2009092033A1 (en) * 2008-01-18 2009-07-23 Qualcomm Incorporated Multi-buffer support for off-screen surfaces in a graphics processing system
US7720672B1 (en) 1995-12-29 2010-05-18 Wyse Technology Inc. Method and apparatus for display of windowing application programs on a terminal
WO2011142937A1 (en) * 2010-05-11 2011-11-17 Amulet Technologies Llc Auto double buffer in display controller
CN113066450A (zh) * 2021-03-16 2021-07-02 长沙景嘉微电子股份有限公司 图像显示方法，装置，电子设备及存储介质
CN113450733A (zh) * 2021-06-11 2021-09-28 上海跳与跳信息技术合伙企业(有限合伙) 一种屏幕刷新的方法与显示系统、用户设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100469820B1 (ko) 2004-06-29 2005-02-03 엔에이치엔(주) 화면 갱신 방법 및 그 시스템
KR100843615B1 (ko) * 2006-05-24 2008-07-04 엠텍비젼 주식회사 효과적인 듀얼 프레임 버퍼 컨트롤 장치 및 그 방법
KR20230160542A (ko) 2022-05-17 2023-11-24 주식회사 두라스택 흡음 또는 차음이 가능한 적층 블록체

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0312720A2 (de) * 1987-10-20 1989-04-26 Tektronix Inc. Graphik-Entwurfssystem mit Doppel-Pufferspeicher
EP0315321A2 (de) * 1987-11-06 1989-05-10 International Business Machines Corporation Multiprozessorsystem mit mehreren Speichern
GB2215959A (en) * 1988-03-23 1989-09-27 Benchmark Technologies Graphics display system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0312720A2 (de) * 1987-10-20 1989-04-26 Tektronix Inc. Graphik-Entwurfssystem mit Doppel-Pufferspeicher
EP0315321A2 (de) * 1987-11-06 1989-05-10 International Business Machines Corporation Multiprozessorsystem mit mehreren Speichern
GB2215959A (en) * 1988-03-23 1989-09-27 Benchmark Technologies Graphics display system

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19654766B4 (de) * 1995-12-29 2004-11-18 Wyse Technology, Inc., San Jose Terminal für die Anzeige von Anwendungsinformationen in einer Fensterumgebung
US8904362B2 (en) 1995-12-29 2014-12-02 Wyse Technology L.L.C. Method and apparatus for display of windowing application programs on a terminal
US8079021B2 (en) 1995-12-29 2011-12-13 Wyse Technology Inc. Method and apparatus for display of windowing application programs on a terminal
US7720672B1 (en) 1995-12-29 2010-05-18 Wyse Technology Inc. Method and apparatus for display of windowing application programs on a terminal
US7554551B1 (en) 2000-06-07 2009-06-30 Apple Inc. Decoupling a color buffer from main memory
US6873335B2 (en) * 2000-09-07 2005-03-29 Actuality Systems, Inc. Graphics memory system for volumeric displays
EP1193671A3 (de) * 2000-09-27 2003-04-23 Mitsubishi Denki Kabushiki Kaisha Matrixanzeigegerät
US6700571B2 (en) 2000-09-27 2004-03-02 Mitsubishi Denki Kabushiki Kaisha Matrix-type display device
EP1193671A2 (de) * 2000-09-27 2002-04-03 Mitsubishi Denki Kabushiki Kaisha Matrixanzeigegerät
EP1217602A2 (de) * 2000-12-04 2002-06-26 Nokia Corporation Aktualisierung von Rasterbildern in einem Anzeigegerät mit einem Bildspeicher
EP1217602A3 (de) * 2000-12-04 2002-10-30 Nokia Corporation Aktualisierung von Rasterbildern in einem Anzeigegerät mit einem Bildspeicher
US6816163B2 (en) 2000-12-04 2004-11-09 Nokia Corporation Updating image frames on a screen comprising memory
EP1355487A1 (de) * 2001-01-25 2003-10-22 Sony Corporation Gerät zum übertragen von daten
EP1355487A4 (de) * 2001-01-25 2006-01-25 Sony Corp Gerät zum übertragen von daten
WO2009092033A1 (en) * 2008-01-18 2009-07-23 Qualcomm Incorporated Multi-buffer support for off-screen surfaces in a graphics processing system
WO2011142937A1 (en) * 2010-05-11 2011-11-17 Amulet Technologies Llc Auto double buffer in display controller
CN113066450A (zh) * 2021-03-16 2021-07-02 长沙景嘉微电子股份有限公司 图像显示方法，装置，电子设备及存储介质
CN113066450B (zh) * 2021-03-16 2022-01-25 长沙景嘉微电子股份有限公司 图像显示方法，装置，电子设备及存储介质
CN113450733A (zh) * 2021-06-11 2021-09-28 上海跳与跳信息技术合伙企业(有限合伙) 一种屏幕刷新的方法与显示系统、用户设备

Also Published As

Publication number Publication date
EP0525986A3 (en) 1993-07-21
EP0525986B1 (de) 1996-11-13
KR930002926A (ko) 1993-02-23
DE69215155T2 (de) 1997-06-19
JPH06214549A (ja) 1994-08-05
DE69215155D1 (de) 1996-12-19
KR100196686B1 (ko) 1999-06-15

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