EP0513100A1 - Dispositif semi-conducteur et procede de fabrication de ce dernier - Google Patents

Dispositif semi-conducteur et procede de fabrication de ce dernier

Info

Publication number
EP0513100A1
EP0513100A1 EP19910903273 EP91903273A EP0513100A1 EP 0513100 A1 EP0513100 A1 EP 0513100A1 EP 19910903273 EP19910903273 EP 19910903273 EP 91903273 A EP91903273 A EP 91903273A EP 0513100 A1 EP0513100 A1 EP 0513100A1
Authority
EP
European Patent Office
Prior art keywords
layer
substrate
silicon
active
diamond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910903273
Other languages
German (de)
English (en)
Inventor
Per Svedberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB AB
Original Assignee
Asea Brown Boveri AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri AB filed Critical Asea Brown Boveri AB
Publication of EP0513100A1 publication Critical patent/EP0513100A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to a semiconductor device comprising a substrate and an active layer of silicon arranged on the substrate, the active parts of the semiconductor device being produced in this layer.
  • the circuit or device is produced in a layer of a semiconducting material, usually silicon, which is arranged on an electrically insulating substrate.
  • This substrate usually consists of a body of semiconducting material, for example silicon, on which an electrically insulating layer, usually silicon dioxide, is arranged.
  • an electrically insulating layer usually silicon dioxide
  • the silicon dioxide layer has to be made relatively thick, typically with a thickness of at least one or a few ⁇ m.
  • the silicon dioxide has poor thermal properties, especially low thermal conductivity.
  • the invention aims to provide a semiconductor device of the kind mentioned in the introduction, which exhibits high power handling capacity and good radiation hardness and in which the adverse effect of incompletely controlled surface states at the interface between the active layer and the insulating layer is avoided.
  • the invention aims to provide a method for the manuf cture of such a semiconductor device.
  • Figure 1 shows an example of a semiconductor device according to the invention.
  • Figure 2 illustrates an example of the method according to the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Figure 1 shows a semiconductor device according to an embodiment of the invention.
  • the device has a substrate 1 in the form of a monocrystalline silicon wafer.
  • the substrate supports an active silicon layer 5, in which the active parts of the device are produced in a manner known per se.
  • the active layer may, for example, have a thickness of 0.6 ⁇ m. Possibly, the substrate may support several separate active layers located beside each other.
  • a polycrystalline diamond layer 3 is arranged, which provides the necessary electrical insulation and separation between the substrate and the active layer. Between the diamond layer 3 and the active layer 5, a thin layer 4 of silicon dioxide is arranged. Between the diamond layer 3 and the substrate, a thin silicon layer 2 is arranged. This layer serves a certain purpose in the manufacturing method which will be described below but may be omitted, for example if a different manufacturing method is used.
  • the silicon dioxide layer 4 is made as thin as possible, which means that only a small number of charges will be generated in the layer upon irradiation.
  • the thickness of the layer should not exceed 0.05 ⁇ for the desired high radiation hardness to be obtained, and according to a preferred embodiment of the invention, the thickness of the layer is at most 0.02 ⁇ m, which provides exceedingly good radiation hardness.
  • the radiation hardness may be further increased by choosing such a process technique for the manufacture of the silicon dioxide layer that the tendency of this layer to capture charges generated upon irradiation will be small.
  • a suitable process technique is thermal oxidation in moist oxygen gas and subsequent heat treatment in an inert atmosphere, for example 2, at temperatures below 900°C.
  • the thickness of the polycrystalline diamond layer 3 is optimized in view of the desired thermal impedance and in view of the influence on the active layer from the underlying substrate. To obtain optimum power-distributing thermal impedance between the active layer and the substrate, the thickness of the layer 3 should be chosen greater than the thickness of the active layer, but sufficiently low to limit the growth time and mechanical stresses.
  • the substrate consists of silicon. This has proved advantageous since then the substrate has the same thermal coefficient of expansion ⁇ as the active layer, which provides the least possible mechanical stresses on the active layer upon temperature variations. Further, silicon has good thermal conductivity, which is important for an efficient removal of heat from the active layer and hence for being able to allow a high power load on the devices or circuits produced in this layer.
  • the substrate may consist of some other material, for example sapphire.
  • the diamond layer is polycrystalline but it may, alternatively, be monocrystal- line.
  • a semiconductor device In a semiconductor device according to the invention, very good power handling capacity of the devices/circuits produced in the active layer is obtained because of the high thermal conductance and heat capacity of the diamond material.
  • the power handling capacity within a large dynamic range is typically twice as great or several times as great as in prior art circuits.
  • very good radiation hardness is obtained.
  • a reduction is obtained of the influence on the active layer exerted by uncontrolled surface states at that interface of the active layer which faces the substrate, and by charge effects in those insulating layers which are arranged between the active layer and the substrate.
  • Figures 2a-2f show a number of successive steps in a preferred method for the production of a semiconductor device according to the invention.
  • the starting-point for the production is the body A of monocrystalline silicon shown in Figure 2a. That surface of the body A which in the finished device is to face the substrate, is provided, as shown in Figure 2b, with a silicon dioxide layer 4, for example by heat treatment in the presence of oxygen.
  • Figure 2c shows how a polycrystalline diamond layer 3 is generated on the silicon dioxide layer 4, for example by CVD (Chemical Vapour Deposition) , or with the aid of a plasma jet method.
  • Figure 2d shows how a thin layer 2 of silicon is applied on the layer 3, for example with the aid of a CVD method.
  • Figure 2e shows how the body A is brought into concact with the layer 2 against the surface of the substrate 1.
  • the layer 2 is brought to adhere to the substrate, for example by heat bonding.
  • Figure 2f such a quantity of the upper part of the body A in Figure 2f is removed, for example by etching, that of the body remains the active layer 5 with a suitable thickness for producing therein the active devices or circuits.
  • the desired active devices or circuits are produced in the layer 5 in a manner known per se, after which the necessary connection members are produced and the device is enclosed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Un dispositif semi-conducteur est constitué d'un substrat et d'une couche active (5) de silicium disposée sur le substrat et dans laquelle sont formées les parties actives du dispositif. Une couche (3) de diamant est prise entre le substrat (1) et la couche active (5) et une couche (4) de dioxyde de silicium est prise entre la couche de diamant et la couche active.
EP19910903273 1990-01-24 1991-01-17 Dispositif semi-conducteur et procede de fabrication de ce dernier Withdrawn EP0513100A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9000245 1990-01-24
SE9000245A SE465492B (sv) 1990-01-24 1990-01-24 Halvledarkomponent innehaallande ett diamantskikt som aer anordnat mellan ett substrat och ett aktivt skikt och foerfarande foer dess framstaellning

Publications (1)

Publication Number Publication Date
EP0513100A1 true EP0513100A1 (fr) 1992-11-19

Family

ID=20378335

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19910903273 Withdrawn EP0513100A1 (fr) 1990-01-24 1991-01-17 Dispositif semi-conducteur et procede de fabrication de ce dernier

Country Status (4)

Country Link
EP (1) EP0513100A1 (fr)
JP (1) JPH05503812A (fr)
SE (1) SE465492B (fr)
WO (1) WO1991011822A1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993001617A1 (fr) * 1991-07-08 1993-01-21 Asea Brown Boveri Ab Procede de fabrication d'un composant semi-conducteur
US5561303A (en) * 1991-11-07 1996-10-01 Harris Corporation Silicon on diamond circuit structure
US5276338A (en) * 1992-05-15 1994-01-04 International Business Machines Corporation Bonded wafer structure having a buried insulation layer
DE69225911T2 (de) * 1992-12-18 1999-02-11 Harris Corp Silizium-auf-diamant-schaltungsstruktur und herstellungsverfahren dafür
US5272104A (en) * 1993-03-11 1993-12-21 Harris Corporation Bonded wafer process incorporating diamond insulator
US5376579A (en) * 1993-07-02 1994-12-27 The United States Of America As Represented By The Secretary Of The Air Force Schemes to form silicon-on-diamond structure
IT1268123B1 (it) * 1994-10-13 1997-02-20 Sgs Thomson Microelectronics Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione.
US6171931B1 (en) 1994-12-15 2001-01-09 Sgs-Thomson Microelectronics S.R.L. Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication
EP0720223B1 (fr) * 1994-12-30 2003-03-26 STMicroelectronics S.r.l. Procédé de fabrication pour un dispositif semi-conducteur comportant une adhésion améliorée entre les couches diélectriques
FR2767605B1 (fr) * 1997-08-25 2001-05-11 Gec Alsthom Transport Sa Circuit integre de puissance, procede de fabrication d'un tel circuit et convertisseur incluant un tel circuit
US20020089016A1 (en) 1998-07-10 2002-07-11 Jean-Pierre Joly Thin layer semi-conductor structure comprising a heat distribution layer
FR2781082B1 (fr) * 1998-07-10 2002-09-20 Commissariat Energie Atomique Structure semiconductrice en couche mince comportant une couche de repartition de chaleur
US6552395B1 (en) * 2000-01-03 2003-04-22 Advanced Micro Devices, Inc. Higher thermal conductivity glass for SOI heat removal
FR3079662B1 (fr) * 2018-03-30 2020-02-28 Soitec Substrat pour applications radiofrequences et procede de fabrication associe

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9111822A1 *

Also Published As

Publication number Publication date
SE9000245L (sv) 1991-07-25
SE9000245D0 (sv) 1990-01-24
JPH05503812A (ja) 1993-06-17
WO1991011822A1 (fr) 1991-08-08
SE465492B (sv) 1991-09-16

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