EP0492542A2 - Méthode de commande d'affichage - Google Patents

Méthode de commande d'affichage Download PDF

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Publication number
EP0492542A2
EP0492542A2 EP91122013A EP91122013A EP0492542A2 EP 0492542 A2 EP0492542 A2 EP 0492542A2 EP 91122013 A EP91122013 A EP 91122013A EP 91122013 A EP91122013 A EP 91122013A EP 0492542 A2 EP0492542 A2 EP 0492542A2
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EP
European Patent Office
Prior art keywords
voltage
scanning
pixels
electrodes
reloading
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Granted
Application number
EP91122013A
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German (de)
English (en)
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EP0492542A3 (en
EP0492542B1 (fr
Inventor
Takaji Numao
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Sharp Corp
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Sharp Corp
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Publication of EP0492542A3 publication Critical patent/EP0492542A3/en
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Publication of EP0492542B1 publication Critical patent/EP0492542B1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3644—Control of matrices with row and column drivers using a passive matrix with the matrix divided into sections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G09G2310/0227—Details of interlacing related to multiple interlacing, i.e. involving more fields than just one odd field and one even field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/065—Waveforms comprising zero voltage phase or pause
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present invention relates to a method of display control for a ferroelectric liquid crystal (referred to as "FLC” hereinafter) panel.
  • FLC ferroelectric liquid crystal
  • Fig. 26 is a sectional view showing a schematic structure of a FLC panel 26.
  • Two glass substrates 5a and 5b are disposed opposed to each other, one glass substrate 5a is provided on its surface a plurality of signal electrodes S of an indium tin oxide (referred to as "ITO" hereinafter) arranged in parallel to one another, and it is covered with a transparent insulating film 6a of SiO2.
  • the other glass substrate 5b opposed to the signal electrodes S is provided on its surface with a plurality of scanning electrodes L in parallel with one another orthogonal to the signal electrodes S, and it is covered with a transparent insulating film 6b of SiO2.
  • the insulating films 6a and 6b are formed on their respective surfaces with arrangement films 7a and 7b which may be, for example, subjected to a rubbing process and made of polyvinyl alcohol.
  • arrangement films 7a and 7b which may be, for example, subjected to a rubbing process and made of polyvinyl alcohol.
  • the two glass substrates 5a and 5b are stuck together by a sealing material 8, with an inlet alone unstuck.
  • FLC 9 is introduced from the inlet to a space defined by the arrangement films 7a and 7b by vacuum injection, and thereafter, the inlet is closed by the sealing material 8.
  • the two glass substrates 5a and 5b, which are stuck together into a lamination in this way, are sandwiched by deflection plates 10a and 10b which are arranged for their deflection axes to be orthogonal to each other.
  • Fig. 27 is a plan view showing a structure of a FLC display (referred to as an abbreviation "FLCD" hereinafter) where a driving circuit 28 for a scanning side is connected to the above-mentioned scanning electrodes L of a simple matrix configuration FLC panel 26 while another driving circuit 29 for a signal side is connected to the above-mentioned signal electrodes S.
  • the driving circuit 28 is a circuit for applying voltage to the scanning electrodes L
  • the driving circuit 29 is a circuit for applying voltage to the signal electrodes S.
  • Fig. 25 is a block diagram schematically showing an architecture of a display system in which the above mentioned FLCD 27 is employed.
  • information required for an image display is drawn from digital signals which a personal computer 2 applies to a CRT display 3, a control circuit 25 transduces the digital signals into signals used for an image display on the FLCD 27, and FLCD 27 displays an image in accordance with the transduced signals.
  • Fig. 4 is a waveform diagram showing various signals applied by the above-mentioned personal computer 2 to the CRT display 3, in which Fig. 4(1) shows a horizontal synchronizing signal HD which applies a period equivalent to a single horizontal scanning section of an image information output to the CRT display 3, Fig. 4(2) shows a vertical synchronizing signal VD which applies a period equivalent to a single screen of the information, and Fig. 4(3) shows display data "Data" of the information for each single horizontal scanning section, with subscript numerals in correspondence with the scanning electrodes Li of the FLCD 27.
  • Fig. 4(4) is a waveform diagram showing an enlarged single horizontal scanning section of the horizontal synchronizing signal HD, Fig.
  • Fig. 4(5) is a waveform diagram showing an enlarged single horizontal scanning section of the above-mentioned display data Data, with subscript numerals in correspondence with the signal electrodes Sj of the FLCD 27, and Fig. 4(6) is a waveform diagram showing a data transferring clock CLK of the display data Data for each pixel.
  • Fig. 10 is a waveform diagram showing an example of waveforms of voltages applied to the scanning electrodes L and signal electrodes S employed in the driving method.
  • a waveform shown in Fig. 10(1) is a waveform of a selective voltage A which is applied to the scanning electrodes L to reload a state of memory of pixels on the very scanning electrodes L, or a state of a brightness on the display
  • a waveform shown in Fig. 10(2) is a waveform of a non-selective voltage B which is applied to the other scanning electrodes L so as not to reload a state of display of pixels on the very scanning electrodes L.
  • a waveform shown in Fig. 10(3) is a waveform of a reloading dark voltage C for reloading the display state of the pixels on the scanning electrodes L to which the selective voltage A is applied to a brightness state "dark”
  • a waveform shown in Fig. 10(4) is a waveform of a reloading bright voltage D for reloading the display state of the pixels on the scanning electrodes L to which the selective voltage A is applied to a brightness state "bright”
  • a waveform shown in Fig. 10(5) is a waveform of a non-reloading voltage G which is applied to the signal electrodes S for preventing the display state of the pixels on the scanning electrodes L to which the selective voltage A is applied from being reloaded.
  • Figs. 10(6) to (11) show waveforms of effective voltage related to the pixel Aij, in which a waveform A-C shown in Fig. 10(6) is a voltage waveform related to the pixel Aij when the selective voltage A is applied to the scanning electrode Li while the reloading dark voltage C is applied to the signal electrode Sj, a waveform A-D shown in Fig. 10(7) is a voltage waveform related to the pixel Aij when the selective voltage A is applied to the scanning electrode Li while the reloading bright voltage D is applied to the signal electrode Sj, a waveform A-G shown in Fig.
  • 10(8) is a voltage waveform related to the pixel Aij when the selective voltage A is applied to the scanning electrode li while the non-reloading voltage G is applied to the signal electrode Sj
  • a waveform B-C shown in Fig. 10(9) is a voltage waveform related to the pixel Aij when the non-selective voltage B is applied to the scanning electrode Li while the reloading dark voltage C is applied to the signal electrode Sj
  • a waveform B-D shown in Fig. 10(10) is a voltage waveform related to the pixel Aij when the non-selective voltage B is applied to the scanning electrode Li while the reloading bright voltage D is applied to the signal electrode Sj
  • a waveform B-G shown in Fig. 10(11) is a voltage waveform related to the pixel Aij when the non-selective Voltage B is applied to the scanning electrode Li while the non-reloading voltage G is applied to the signal electrode Sj.
  • the selective voltage A shown in Fig. 10(1) is applied to the scanning electrode Li
  • the reloading dark voltage C shown in Fig. 10(3) is applied to the signal electrode Sj when the pixel Aij should be reloaded into a "dark" display state
  • the selective voltage A is applied to the scanning electrodes L0 to L8 in this order, applied to the signal electrodes S0 to S7 are the reloading dark voltage C in correspondence with the character "C" in positions corresponding to the pixels Ai0 to Ai7 on the scanning electrodes Li shown in Fig. 28 to which the selective voltage A is applied, the reloading bright voltage D in correspondence with the character "D", and the non-reloading voltage G in correspondence with the character "H" and a void without character.
  • the reloading dark voltage C is applied to the signal electrodes S1 and S5 while the non reloading voltage C is applied to the other signal electrodes when the selective voltage A is applied to the scanning electrode L2
  • the reloading bright voltage D is applied to the signal electrode S5 while the non-reloading voltage C is applied to the other signal electrodes when the selective voltage A is applied to the scanning electrode L3.
  • the selective voltage is applied to a certain number of the scanning electrodes by the N : 1 skip scanning, the selective voltage is applied to a certain number of the scanning electrodes including the pixels which have been observed to make a change of display in accordance with the driving method described in the Japanese Unexamined Patent Publication No. 59389/1989 to reload the pixels on the scanning electrodes, so that a FLCD which has no conspicuous flicker and can quickly respond to a change in the contents of a display can be obtained.
  • Fig. 29 is a combination of waveforms of voltages applied to scanning electrodes L and signal electrodes S employed as an embodiment disclosed in the gazette of the Japanese Unexamined Patent Publication No. 128044/1989. A combination of voltage waveforms shown in Fig.
  • 29(A) is a combination of waveforms of voltages for reloading pixels on the scanning electrodes into a first stable state, wherein 1) is a selective voltage V CA which allows a state of the pixels on the scanning electrodes to which this voltage is applied to be reloaded into the first stable state, 2)is a non-selective voltage V CB which never allow the state of the pixels on the scanning electrodes to which this voltage is applied to be reloaded into the first stable state, 3) is a reloading dark voltage V SC for reloading the pixels consisting of the signal electrodes to which this voltage is applied and the scanning electrodes to which the voltage V CA is applied into the first stable state, 4) is a non-reloading dark voltage V SG for preventing the pixels consisting of the signal electrodes to which this voltage is applied and the scanning electrodes to which the voltage V CA is applied from being reloaded into the first stable state, 5) is a voltage A-C which is applied to the pixels consisting of the scanning electrodes to which the voltage V CA
  • a combination of voltage waveforms shown in Fig. 29(B) is a combination of waveforms of voltages for reloading pixels on the scanning electrodes into a second stable state, wherein 1) is a selective voltage V CE which allows a state of the pixels on the scanning electrodes to which this voltage is applied to be reloaded into the second stable state, 2)is a non-selective voltage V CF which never allow the state of the pixels on the scanning electrodes to which this voltage is applied to be reloaded into the second stable state, 3) is a reloading dark voltage V SD for reloading the pixels consisting of the signal electrodes to which this voltage is applied and the scanning electrodes to which the voltage V CE is applied into the second stable state, 4) is a non-reloading dark voltage V SH for preventing the pixels consisting of the signal electrodes to which this voltage is applied and the scanning electrodes to which the voltage V CE is applied from being reloaded into the second stable state, 5) is a voltage A-D which is applied to the pixels consisting
  • all the scanning electrodes are divided into four groups by picking up every four of them to make a group (a group is composed of L0, L4, L8 and LC), and in a first field the pixels on the scanning electrodes belonging to a first group are refreshed by the combination of voltage waveforms shown in Fig. 29(A), while the pixels on the scanning electrodes belonging to a third group are refreshed by the combination of voltage waveforms shown in Fig. 29(B).
  • a second field the pixels on the scanning electrodes belonging to a second group are refreshed by the combination of voltage waveforms shown in Fig. 29(A), while the pixels on the scanning electrodes belonging to a fourth group are refreshed by the combination of voltage waveforms shown in Fig. 29(B) in a fourth field.
  • the pixels on the scanning electrodes belonging to a third group are refreshed by the combination of voltage waveforms shown in Fig. 29(A), while the pixels on the scanning electrodes belonging to a first group are refreshed by the combination of voltage waveforms shown in Fig. 29(B).
  • the pixels on the scanning electrodes belonging to a fourth group are refreshed by the combination of voltage waveforms shown in Fig. 29(A), while the pixels on the scanning electrodes belonging to a second group are refreshed by the combination of voltage waveforms shown in Fig. 29(B).
  • FIG. 30 A state of a display of pixels A11 to A42 consisting of the scanning electrodes L1 to L4 and the signal electrodes S1 and S2 is shown in Fig. 30, voltages applied to the scanning electrodes L1 to L4 and the signal electrodes S1 and S2 when this embodiment is employed are shown in Fig. 31, and voltages applied to the pixels A11 to A22 are shown in Fig. 32.
  • 1) is a voltage applied to the scanning electrode L1, 2) is a voltage applied to the scanning electrode L2, 3) is a voltage applied to the scanning electrode L3, 4) is a voltage applied to the scanning electrode L4, 5) is a voltage applied to the signal electrode S1, and 6) is a voltage applied to the signal electrode S2.
  • Fig. 32 1) is a voltage applied to the pixel A11, 2) is a voltage applied to the pixel A12, 3) is a voltage applied to the pixel A21, and 4) is a voltage applied to the pixel A22.
  • a brightness of the FLCD 4 has a peak in a cycle of a single field, and if the field frequency is set to a frequency of 60 Hz or over (30 Hz or over according to another report) in which no flicker is within sight of a person, pixels of the FLCD can be refreshed without flicker.
  • pixels in an area where the contents of a display is changed are reloaded by the N : 1 skip scanning (including the multi-interlace driving method described in the gazette of the Japanese Unexamined Patent Publication No. 128044/1989) before the pixels are reloaded in accordance with the driving method described in the gazette of the Japanese Unexamined Patent Publication No. 59389/1989, because the contents of the display are changed at intervals of several scanning electrodes.
  • a screen of states of pixels to be displayed next and a screen of states of pixels already displayed on the FLC panel are recorded, and both of those data may be used if the pixels should be reloaded in accordance with the driving method described in the gazette of the Japanese Unexamined Patent Publication No. 59389/1989, while the latter data may be used if the pixels should be reloaded by the N : 1 skip scanning.
  • a structure of a control circuit to perform such operations must be too complicated.
  • the number N of the scanning electrodes which can be used for a display must satisfy the following formula: t1 x (1 + P) x N/Q ⁇ 1/60 [ms] (1)
  • This formula can be transformed into Q ⁇ 60 x N x (1 + P) x t1 (2) and assuming now that 100 &Ls is required for reloading the pixels on a single scanning electrode, when a single scanning electrode is picked up on the average to be driven for a partial reloading after a single scanning electrode is picked up to be driven for a refreshment, all the scanning electrodes must be skip-driven every Q scanning electrodes to display the FLCD having 4096 scanning electrodes, where Q
  • the scanning electrodes are skip-driven every so large a number of the scanning electrodes, sometimes so many pixels cannot be within sight of a person at a time, and naturally, the number of the scanning electrodes which can be skip-driven at a time is restricted.
  • the number is approximately 16 to 32, and hence, naturally, the number of the scanning electrodes which can be used for a display with an FLC is restricted.
  • this invention should overcome the above-mentioned disadvantages, and it is an object of the present invention to provide the optimum driving method to the above-mentioned display control method.
  • the purpose of performing the N : 1 skip scanning in this invention is to retain the states of pixels on an FLC panel without conspicuous flicker.
  • a non-reloading voltage is applied to signal electrodes so as not to change the states of a display of the pixels if there is any difference between a state of a display of the pixels on the scanning electrodes to which a selective voltage is applied and data to be displayed through the pixels, a reloading dark voltage is applied to the signal electrodes when data displayed through the pixels are dark while a reloading bright voltage is applied to the signal electrodes when the data displayed through the pixels are bright so as to retain a state of a display of the pixels, if there is no difference between the state of a display of the pixels on the scanning electrodes on the FLC panel to which the selective voltage is applied and data to be displayed through the pixels.
  • the purpose of the driving method in the gazette of the Japanese Unexamined Patent Publication No. 59389/1989 is to reload the states of the pixels on the FLC panel without conspicuous flicker.
  • this driving method in order to avoid a conspicuous flicker, if there is any difference between a state of the pixels on the scanning electrodes to which the selective voltage is applied and data to be displayed through the pixels, a reloading dark voltage is applied to the signal electrodes when the data displayed through the pixels are dark, a reloading bright voltage is applied to the signal electrodes when the data displayed through the pixels are bright, while a non-reloading voltage is applied to the signal electrodes to avoid a conspicuous flicker when there is no difference between the state of a display of the pixels on the scanning electrodes on the FLC panel to which the selective voltage is applied and data to be displayed through the pixels, so as to keep the state of a display of the pixels in an intended state of a display.
  • a control circuit including means for recording states of the pixels to be displayed on the FLC panel, and means for recording if there is any difference between a state of the pixels to be displayed on the FLC panel and the state of the pixels already displayed for every several pixels (recording there is a difference if only a single pixel in a group of several pixels has the difference), and the data recorded by the former means are defined as display data while the data recorded by the latter means are defined as identifying data, when the selective voltage is applied to the scanning electrodes to perform the N : 1 skip scanning in accordance with the above driving method, the non-reloading voltage is applied to the signal electrodes indifferent of the display data if the identifying data show some difference, and if the identifying data show no difference, the reloading dark voltage is applied to the signal electrodes when the display data are dark, while the reloading bright voltage is applied to the signal electrodes when the display data are bright, when the selective voltage is applied to the scanning electrodes to perform the driving method in
  • the reloading dark voltage is applied to the signal electrodes when the display data are dark
  • the reloading bright voltage is applied to the signal electrodes when the display data are bright
  • the non-reloading voltage is applied to the signal electrodes indifferent of the display data, if the selective voltage is applied to a certain number of the scanning electrodes containing the pixels of which display makes some change in accordance with the driving method in the gazette of the Japanese Unexamined Patent Publication No.
  • a skip driving is performed every Q scanning electrodes.
  • Such a driving method can be implemented for the following reasons: When the selective voltage is applied to the scanning electrodes for the purpose of performing the N : 1 skip scanning in accordance with the driving method of this invention, the selective voltage is immediately applied to the scanning electrodes to perform the driving method in the gazette of the Japanese Unexamined Patent Publication No.
  • the reloading dark voltage is applied to the signal electrodes when the display data of the pixels are dark, while the reloading bright voltage is applied to the signal electrodes to reload the pixels when the display data are bright; and hence, there is no necessity of retaining the contents of a display of the pixels which make some change in the N : 1 skip scanning.
  • the driving method disclosed in the Japanese Unexamined Patent Publication No. 59389/1989 can be implemented for the following reasons: Even if the pixels which make some change in a state of a display are reloaded, a variation in brightness due to the reloading cannot be distinguished from a variation in brightness due to a variation in a state of a display, and the variation in brightness due to the reloading cannot be found whether a frame frequency is 60 Hz or 1 Hz.
  • the driving method disclosed in the Japanese Unexamined Patent Publication No. 59389/1989 also makes it possible that the required storing capacity is reduced less than two frames. Reloading one of the pixels which have some difference between a state to be displayed on the FLC panel and a state already displayed, it is certain that the variation in brightness in the very part on the FLC panel can be found without reloading a plurality of adjacent pixels having no difference between the state to be displayed on the FLC panel and the state already displayed, and hence there is no need of recording the identifying data pixel by pixel, but it is possible to record a plurality of pixels at a time.
  • Fig. 34 shows a state of FLC molecules 101 in a smectic C-phase.
  • the FLC molecules 101 move on an inherent circular cone.
  • Fig. 11(A) is a view showing this state seen from above, where angles (tilt angles) of the maximum axis 107 and 106 along which the FLC molecules 101 can move are - ⁇ and ⁇ related to a center axis 103, while angles (memory angles) of the first stable state 105 and the second stable state 104 are - ⁇ and ⁇ related to the center axis 103.
  • the FLC molecules must be moved to the angle 0 in many cases to convert them from the first stable state to the second stable state, while the FLC molecules must be moved to the angle -0 in many cases to convert them from the second stable state to the first stable state.
  • the FLC molecules 101 stay in the first stable state 105.
  • the voltage of the polarity 2 is applied to the FLC molecules 101 to move them from the angle - ⁇ to the angle ⁇ and thereafter the voltage is reduced to zero
  • the FLC molecules 101 return naturally from the angle ⁇ to - ⁇ .
  • the voltage of the polarity 1 is applied to the FLC molecules 101 to move them from the angle - ⁇ to the angle - ⁇ and thereafter the voltage is reduced to zero
  • the FLC molecules 101 return naturally from the angle - ⁇ to - ⁇ . This means that once the FLC molecules 101 stay in the first stable state 105, a restoring force is exerted for the FLC molecules 101 to return to the angle - ⁇ .
  • the center of swinging of the FLC molecules 101 is first close to the angle 0, and soon the center comes almost to the angle - ⁇ because a restoring force is exerted so that the FLC molecules 101 may return to the angle - ⁇ .
  • the center of the swinging of the FLC molecules comes close to the angle - ⁇ .
  • the center close to the angle - ⁇ means that the center comes close to the angle 0 immediately after the application of the voltage of the polarity 2 to the FLC molecules, and if the voltage of the polarity 2 is applied to the FLC molecules lying in this angle, the FLC molecules can be moved closer to the angle &H rather than the voltage of the polarity 2 is applied to the FLC molecules lying in the angle ⁇ .
  • the center of the swinging of the FLC molecules come close to the angle - ⁇ , and the center lies closer to the angle - ⁇ immediately after the application of the voltage of the polarity 1 to the FLC molecules. If the voltage of the polarity 1 is applied to the FLC molecules lying in this angle, the FLC molecules can be moved closer to the angle ⁇ rather than the voltage of the polarity 1 is applied to the FLC molecules lying in the angle - ⁇ .
  • pixels which stays a dark state of a display and are composed of the FLC molecules in the first stable state has an increasingly larger amount of light transmission each time the operations are switched, and an effect that an amount of the light transmission caused when the pixels are reloaded in the refresh driving becomes inconspicuous is observed.
  • Fig. 2 is a sectional view showing a schematic structure of an FLC panel 1 employed in this embodiment, and the description of the FLC panel 1 is omitted because it is almost the same as the FLC panel 26 shown in Fig. 26 except that the FLC panel 1 is provided with sixteen scanning electrodes L and sixteen signal electrodes S.
  • Polyimide subjected to a rubbing process is employed as an arrangement film in the FLC panel 1 while ferroelectric liquid crystal employed in this embodiment is ZL1-4237/000 manufactured by Merck Co., Ltd.
  • Fig. 3 is a plan view showing a structure of an FLCD 4 in which a scanning side driving circuit 11 is connected to the scanning electrodes L of the FLC panel 1 having the above-mentioned 16 x 16 simple matrix configuration while a signal side driving circuit 12 is connected to the signal electrodes S.
  • Fig. 1 is a block diagram schematically showing an architecture of the display system in which the above-mentioned FLCD 4 is employed.
  • the architecture of the display system is similar to a conventional display system, for example, information required for an image display is drawn from digital signals identical to the conventional art in Fig. 4, which a personal computer 2 applies to a CRT display 3.
  • a control circuit 13 converts the digital signals into signals used for an image display on the FLCD 4, and the FLCD 4 displays an image in accordance with the converted signals.
  • Figs. 5 and 6 are data diagrams showing a matrix of display data "Data" of the digital signals shown in Figs. 4(3) and 4(5).
  • the whole 16 x 16 pixels on the FLC panel 1 can be used for a data display although each of the digital signals is equivalent only to 9 x 8 pixels.
  • the 16 x 16 pixels can be virtually divided into four parts which are comprised of a display section "0" consisting of the scanning electrodes L0 to L7 and signal electrodes S0 to S7, a display section "1” consisting of the scanning electrodes L0 to L7 and signal electrodes S8 to SF, a display section “2” consisting of the scanning electrodes L8 to LF and signal electrodes S0 to S7, and a display section "3” consisting of the scanning electrodes L8 to LF and signal electrodes S8 to SF, and as shown in Figs. 5 and 6, commands are issued which display sections "0" to "3" data in the 0-th horizontal scanning section and data in the following first to eighth horizontal scanning sections correspond to.
  • Fig. 7 is a data diagram showing the contents of a display memory for recording display data DA which are made from the above-mentioned 9 x 8 digital signal in accordance with the above-mentioned rule and are to be displayed next on the FLC panel 1, in a 16 x 16 matrix corresponding to each pixel on the FLC panel 1.
  • the variation in the data in the display memory is stored in an identifying memory four pixels on the FLCD 4 together at a time (if one of those pixels is varied).
  • a variation in the data in the display memory in Fig. 8 is stored as identifying data DF in the identifying memory four pixels together at a time corresponding with pixels on the FLC panel 1, Ai0 to Ai3, Ai4 to Ai7, Ai8 to AiB, AiC to AiF, as shown in Fig. 9 (data identified by oblique lines are the data which are varied).
  • a skip scanning is performed at a rate of 4 : 1 in order of the scanning electrodes, L0, L4, L8, LC, L1, L5, L9, LD, L2, L6, LA, LE, L3, L7, LB and LF, and after the selective voltage is applied to one of the scanning electrodes in accordance with the driving method of the N : 1 skip scanning of this invention , the selective voltage is applied to two of the scanning electrodes in accordance with the driving method in the gazette of the Japanese Unexamined Patent Publication No. 59389/1989.
  • the voltage waveforms in Figs. 10(1) to 10(5) are used as the selective voltage, non-selective voltage, reloading dark voltage, reloading bright voltage, and non-reloading voltage.
  • identifying memory in Fig. 9 has a storage of the data of every scanning electrode, it may have a storage of a variation in the display data of a plurality of the scanning electrodes together of each scanning electrode group as shown in Fig. 11.
  • the FLC panel 1 can be structured.
  • tantalum oxide (Ta2O5) is employed for the high dielectric constant insulating film 23 while IT0 is employed for the pixel electrode 24 and conductive electrode 22.
  • Embodiment 1 there is another embodiment of the present invention, which provides a driving method in which the scanning electrodes on the FLC panel 1 are divided into groups each of which includes several scanning electrodes, and the control circuit 13 includes means for foreknowing a group of the scanning electrodes having its identifying memory varied, the selective voltage is successively applied to all the scanning electrodes of of a certain group to perform the driving method in the Japanese Unexamined Patent Publication No.
  • an operation that the selective voltage is applied to a specific scanning electrode to perform the driving method for the N:1 skip scanning of this invention is repeated twice to the same scanning electrode group and the same scanning electrode, first either of two kinds of voltages which reloads or not reload the pixel Aij on the scanning electrode Li, to which the selective voltage is applied, into a dark state is applied to the signal electrode Sj, and second either of two kinds of voltages which reloads or not reload the pixel Aij on the scanning electrode Li, to which the selective voltage is applied, into a bright state is applied to the signal electrode Sj.
  • the FLCD 4 is driven in accordance with the above-mentioned methods. Also in this embodiment, configurations of the FLC panel 1 and FLCD 4 are the same as in Figs. 2 and 3, and a configuration of the display system is similar to Fig. 1.
  • the 0-th scanning electrode group is comprised of the scanning electrodes L0 and L1
  • the first scanning electrode group is comprised of the scanning electrodes L2 and L3
  • the second scanning electrode group is comprised of the scanning electrodes L4 and L5
  • the third scanning electrode group is comprised of the scanning electrodes L6 and L7
  • the fourth scanning electrode group is comprised of the scanning electrodes L8 and L9
  • the fifth scanning electrode group is comprised of the scanning electrodes LA and LB
  • the sixth scanning electrode group is comprised of the scanning electrodes LC and LD
  • the seventh scanning electrode group is comprised of the scanning electrodes LE and LF.
  • the driving method of a 4 : 1 skip scanning is performed in order of the scanning electrodes, L0, L4, L8, LC, L1, L5, L9, LD, L2, L6, LA, LE, L3, L7, LB and LF, and after the selective voltage is applied to two of the scanning electrodes in accordance with the driving method in the Japanese Unexamined Patent Publication No. 59389/1989, the selective voltage is applied to specified one of the scanning electrodes in accordance with the driving method of the 4 : 1 skip scanning. This operation is repeated twice as mentioned above.
  • Figs. 14(A) and 14(B) show combinations of waveforms of voltages to be applied to the scanning electrodes L and signal electrodes S on the FLC panel 1.
  • Fig. 14(A)(1) shows a waveform of a selective voltage A which is applied to the scanning electrodes L so that a state of a display on the pixels on the scanning electrodes L may be reloaded into a "dark" luminance state
  • Fig. 14(A)(2) shows a waveform of a selective voltage B which is applied to the other scanning electrodes L so that a state of a display on the pixels on the scanning electrodes L may not be reloaded.
  • Fig. 14(A)(3) shows a waveform of a reloading dark voltage C which is applied to the signal electrodes S so that a state of a display of the pixels on the scanning electrodes L to which the selective voltage A is applied may be reloaded into a "dark" luminance state
  • Fig. 14(A)(4) shows a waveform of a non-reloading voltage G which is applied to the signal electrodes S so that a state of a display of the pixels on the scanning electrodes L to which the selective voltage A is applied may not be reloaded.
  • Figs. 14(A)(5) to 15(A)(8) show waveforms of effective voltages related to the pixel Aij, of which a waveform A-C in Fig.
  • 14(A)(5) is a waveform of voltage related to the pixel Aij when the reloading dark voltage C is applied to the signal electrode Sj
  • a waveform A-G in Fig. 14(A)(6) is a waveform of voltage related to the pixel Aij when the non-reloading voltage G is applied to the signal electrode Sj
  • a waveform B-C in Fig. 14(A)(7) is a waveform of voltage related to the pixel Aij when the reloading dark voltage C is applied to the signal electrode Sj
  • a waveform B-G in Fig. 14(A)(8) is a waveform of voltage related to the pixel Aij when the non-reloading voltage G is applied to the signal electrode Sj.
  • a waveform shown in Fig. 14(B)(1) is a waveform of a selective voltage E which is applied to the scanning electrodes L may be reloaded into a "bright" luminance state
  • a waveform shown in Fig. 14(B)(2) is a waveform of a non-selective voltage F which is applied to the other scanning electrodes L so that a state of a display of the pixels on the scanning electrodes L may not be reloaded.
  • a waveform shown in Fig. 14(B)(3) is a waveform of a reloading dark voltage D which is applied to the signal electrodes S so that a state of a display of the pixels on the scanning electrodes L to which the selective voltage E is applied may be reloaded into a "bright" luminance state
  • a waveform shown in Fig. 14(B)(4) is a waveform of a non-reloading voltage H which is applied to the signal electrodes S so that a state of a display of the pixels on the scanning electrodes L to which the selective voltage E is applied may not be reloaded.
  • Figs. 14(B)(5) to 14(B)(8) show waveforms of effective voltages related to the pixel Aij, of which a waveform E-D in Fig. 14(B)(5) is a waveform of a voltage related to the pixel Aij when the selective voltage E is applied to the scanning electrode Li while the reloading dark voltage D is applied to the signal electrode Sj, a waveform E-H in Fig. 14(B)(6) is a waveform of a voltage related to the pixel Aij when the selective voltage E is applied to the scanning electrode Li while the non-reloading voltage H is applied to the signal electrode Sj, a waveform F-D in Fig.
  • a waveform F-H in Fig. 14(B)(8) is a waveform of a voltage related to the pixel Aij when the non-selective voltage F is applied to the scanning electrode Li while the non-reloading voltage H is applied to the signal electrode Sj.
  • a configuration of a control circuit 13 is shown in a block diagram in Fig. 15.
  • the control circuit 13 is comprised of an interface circuit 14 receiving a digital signal from a personal computer 2 for distributing to circuits which need it, a display memory circuit 15 recording the display data DA which is to be displayed next on the FLC panell, an identifying memory circuit 17 storing a variation in data of the display memory circuit 15 every four pixels together, a group memory circuit 16 storing a variation in data of the display memory circuit 15 every two scanning electrodes together, an input control circuit 18 for controlling a timing for writing required data in the three memory circuits 15, 16 and 17, an output control circuit 19 and address circuit 20 for controlling a timing for reading data to be output from the three memory circuits 15, 16 and 7 to the FLCD 4, and a drive control circuit 21 receiving data from the display memory circuit 15, identifying memory circuit 17, output control circuit 19 and address circuit 20 for controlling the operation of a scanning side driving circuit 11 and signal side driving circuit 12 of which the FLCD 4 is comprised.
  • Fig. 16 is a diagram showing a structure of the above-mentioned input control circuit 18.
  • the input control circuit 18 is comprised of ten NAND gates 40a to 40j, two AND gates 41a and 41b, ten D-type flip flops 42a to 42j, two shift registers 43a and 43b, a single register 44a with load function, three counters 45a to 45c, two read only memories (ROMs), and three rotary switches 47a to 47c.
  • Fig. 17 is a diagram showing a structure of the above-mentioned output control circuit 19.
  • the output control circuit 19 is comprised of eleven NAND gates 48a to 48k, two AND gates 49a and 49b, eight counters 50a to 50h, two D-type flip flops 51a and 51b, a single shift register 52a, and eight rotary switches 53a to 53h.
  • Fig. 18 is a diagram showing a structure of the above-mentioned address circuit 20.
  • the address circuit 20 is comprised of a single D-type flip flop 54a, and two selectors 55a and 55b.
  • Fig. 19 is a diagram showing a structure of the above-mentioned display memory circuit 15.
  • the display memory circuit 15 is comprised of a single selector 56a, a single shift register 57a, a single register 58a with load function, a single three-valued buffers 59a, two D-type flip flops 60a and 60b, a single parallel/serial converter 61a, a single random access memory (RAM) 62a, four NAND gates 63a to 63d, four AND gates 64a to 64d, four EOR gates 65a to 65d, and a single OR gate 66a.
  • RAM random access memory
  • Fig. 20 is a diagram showing a structure of the above-mentioned group memory circuit 16.
  • the group memory circuit 16 is comprised of a single selector 67a, two three-valued buffers 68a and 68b, four D-type flip flops 69a to 69d, two registers with load function 70a and 70b, a single RAM 71a, three NAND gates 72a to 72c, two OR gates 73a and 73b, and six AND gates 74a to 74f.
  • Fig. 21 is a diagram showing a structure of the above-mentioned identifying memory circuit 17.
  • the identifying memory circuit 17 is comprised of two selectors 75a and 75b, a single three-valued buffers 76a, two D-type flop flops 77a and 77b, a single register with load function 78a, a single RAM 79a, two OR gates 80a and 80b, three NAND gates 82a to 82c, six AND gates 81a to 81f, and a single decoder 83a.
  • the interface circuit 14 and the drive control circuit 21 has a simple configuration, and therefore, configuration diagrams of them are omitted.
  • Figs. 22 and 23 show a process in which a display of "ABCD” shown in Fig. 3 on the FLCD 4 is turned to a display of "EBCD” in Fig. 7.
  • Figs. 22(1) and 23(1) show a synchronizing signal HP of 4t0 period
  • Figs. 22(3) and 23(3) show a drive mode H/R which corresponds to the driving method in the Japanese Unexamined Patent Publication No. 59389/1989 when it turns to "1" ("HIGH” in the drawings) but corresponds to the driving method of the N : 1 skip scanning of this invention when it turns to "0" ("LOW” in the drawings), while Figs.
  • Figs. 22(4) and 23(4) show a voltage mode E/W which are combined with the drive mode H/R to shift a voltage combination between those in Fig. 14(B).
  • Figs. 22(5) and 23(5) show an address identifying the scanning electrodes in the driving method of the N : 1 skip scanning of this invention
  • Figs. 22(6) and 23(6) show an address identifying the scanning electrode groups in the driving method of the Japanese Unexamined Patent Publication No. 59389-1989.
  • Figs. 22(7) and 23(7) show an address OGA outputting to the group memory 16 for searching a state of the scanning electrode groups
  • Figs. 22(8) and 23(8) show an address OAC outputting to the display memory 15 and identifying memory 17 for allowing them to output the display data DA and identifying data DF.
  • Fig. 23 is a signal diagram follows Fig. 22, partially overlaps with it in respect of time. According to a time chart shown in Figs. 22 and 23, an outline is provided below in order of time from 1) to 9).
  • the drive control circuit 21 receives the drive mode H/R, voltage mode E/W, display data DA, identifying data DF, group identifying data RGDF and DGDF, etc. to operate as follows:
  • V CA in Fig. 14(A)(1) is applied as voltage V C0 from the drive control circuit 21
  • V CB in Fig. 14(A)(2) is as voltage V C1
  • V SC in Fig. 14(A)(3) is as voltage V S0
  • V SG in Fig. 14(A)(4) is as voltage V S1 .
  • V CE in Fig. 14(B)(1) is applied as voltage V C0 from the drive control circuit 21
  • V CF in Fig. 14(B)(2) is as voltage V C1
  • V SD in Fig. 14(B)(3) is as voltage V S0
  • V SH in Fig. 14(B)(4) is as voltage V S1 .
  • Fig. 24(1) is a waveform of a voltage applied to the scanning electrode L0
  • Fig. 24(2) is a waveform of a voltage applied to the scanning electrode L1
  • Fig. 24(3) is a waveform of a voltage applied to the scanning electrode L2
  • Fig. 24(4) is a waveform of a voltage applied to the signal electrode S1
  • Fig. 24(5) is a waveform of a voltage applied to the signal electrode S2
  • Fig. 24(6) is a waveform of a voltage applied to the signal electrode S5, Fig.
  • Fig. 24(7) is a waveform of an effective voltage applied to the signal electrode A11
  • Fig. 24(8) is a waveform of an effective voltage applied to the signal electrode A21
  • Fig. 24(9) is a waveform of an effective voltage applied to the signal electrode A22
  • Fig. 24(10) is a waveform of an effective voltage applied to the signal electrode A25.
  • each of the scanning electrode groups is comprised of two scanning electrodes in this embodiment, as more scanning electrodes are employed, accordingly a scanning electrode group may include two to 64 scanning electrodes.
  • one scanning electrode is driven in accordance with the N : 1 skip scanning method of this invention each time all the scanning electrodes in one scanning electrode group are driven in accordance with the method disclosed in the gazette of the Japanese Unexamined Patent Publication No. 59389/1989, more than one scanning electrodes may be driven in accordance with the N : 1 skip scanning method of the present invention.
  • the operator may decide whether one scanning electrode group should be driven by the voltage combination in Fig. 14(A) or the voltage combination in Fig.
  • circuits 50 and 51 can be used.
  • Fig. 50 is a diagram showing a structure of the group memory circuit 16.
  • the group memory circuit 16 is comprised of a single selector 67a, two three-valued buffers 68a and 68b, four D-type flip flops 69a to 69d, two registers with load function 70a and 70b, a single RAM 71a, three NAND gates 72a to 72c, two OR gates 73a and 73b, and six AND gates 74a to 74f.
  • Fig. 51 is a diagram showing a structure of the identifying memory circuit 17.
  • the identifying memory circuit 17 is comprised of two selectors 75a and 75b, a single three-valued buffer 76a, two D-type flip flops 77a and 77b, a single register with load function 78a, a single RAM 79a, two OR gates 80a and 80b, three NAND gates 82a to 82c, six AND gates 81a to 81f, and a single decoder 83a.
  • a sectional view of the FLC panel 1 employed in this embodiment is all the same as that of the conventional embodiment shown in Fig. 2, and a plan view of the FLCD 4 is also the same as in the conventional example in Fig. 3, and hence the description of them is omitted.
  • the FLC panel 1 in this embodiment includes an arrangement film of polyimide subjected to a rubbing process, and ferroelectric liquid crystal CS-1014 manufactured by Chisso Co., Ltd.
  • This embodiment employs the display system of the same structure as the conventional example in Fig. 1, but employs a control circuit 13 different in structure from the conventional embodiment.
  • the control circuit 33 is, as shown in Figs. 35 and 36, comprised of an interface circuit 34 receiving a digital signal "Data”, synchronizing signals HD and VD from the personal computer 2 to distribute them as input data "Din”, synchronizing signals IVD and IHD to circuits which need them, a display memory circuit 35 storing display data "DA" to be displayed next on the FLC panel 1, an identifying memory circuit 27 grouping a variation IDF in data of the display memory circuit 25 every four pixels to store them as identifying data DF, an identifying memory circuit 26 grouping a variation IDF in data of the display memory circuit 15 every two scanning electrodes to store them as identifying data IGDF and OGDF, and input control circuit 28 for controlling addresses IACx and IASx for writing input data in the three memory circuits 25 to 27, output control circuits 29 and address circuit 30 for controlling addresses OACx, OASx
  • this embodiment of the present invention will treat a variation in a display of the FLCD 4 from "ABCD” in Fig. 3 to "EBCD” in Fig. 7.
  • the display data "EBCD” in Fig. 7 is stored in the display memory circuit 25.
  • a difference between the display "ABCD” in Fig. 3 and the display “EBCD” in Fig. 7 is searched every single pixel, and it is detected that there is a variation in a display in a pixel identified by oblique lines in Fig. 8.
  • the variations of pixels are grouped every four pixels as shown in Fig. 9 and they are stored as identifying data (recognized as "varied” if only a single pixel is changed) in the identifying memory circuit 27.
  • the scanning electrodes divided into groups each of which is comprised of two scanning electrodes, and as shown in Fig. 37, and if even a single identifying data is varied as shown in Fig. 37, it is stored as two state data ("varied" if even a single identifying data contained in the scanning electrode group is varied) in the identifying memory circuit 26.
  • the scanning electrode L2 is driven for a refreshment, and the scanning electrodes L0 and L1 are driven for a partial reloading.
  • Fig. 14(A) shows a combination of voltage waveforms for reloading pixels on scanning electrodes into a first stable state, similar to the conventional embodiment in Fig. 29(A), and its description is omitted.
  • a difference between Fig. 14(A) and Fig. 29(A) is that Fig. 14(A) satisfies the requirement of I) because the voltage B-C of 7) and the voltage B-G of 8) are combinations of voltage waveforms where the voltage of positive polarity is followed by the voltage of negative polarity, but Fig. 29(A) does not satisfies the requirement of I) because the voltage B-G of 8) is a combination of voltage waveforms where the voltage of negative polarity is followed by the voltage of positive polarity.
  • Fig. 14(B) is also a combination of voltage waveforms for reloading pixels of scanning electrodes into a second stable state, similar to the conventional embodiment Fig. 29(B), and its explanation is omitted.
  • a difference between Fig. 14(B) and Fig. 29(B) is that Fig. 14(B) satisfied the requirement of II) because the voltage F-D of 7) and the voltage F-H of 8) are combinations of voltage waveforms where voltage of negative polarity is followed by voltage of positive polarity, while Fig. 29(B) does not satisfy the requirement II) because the voltage F-H of 8) is a combination of voltage waveforms where voltage of positive polarity is followed by voltage of negative polarity.
  • Fig. 40 (1) shows a waveform of voltage applied to an pixel A21
  • Fig. 40 (2) shows at which angle FLC molecules are positioned when the pixel A is the first stable state
  • Fig. 40(3) shows an amount of light transmission when a deflection axis of a deflection plate is positioned at an angle - ⁇ .
  • the FLC molecules are positioned closer to an angle - ⁇ rather than the angle - ⁇ since before the time voltage of negative polarity is applied after voltage of positive polarity is applied three times.
  • voltage of positive polarity is applied three times after voltage of negative polarity is applied, as already mentioned, first the FLC molecules swing up to -18°, but at the third time they can swing barely to -16°.
  • the FLC molecules are a little closer to an angle ⁇ rather than an angle - ⁇ , and therefore, after that when voltage of negative polarity is applied after voltage of positive polarity is applied, the FLC molecules can first swing up to an angle 8°. This attains a larger swing than the angle 6° after a time 0 when voltage of negative polarity is applied after voltage of positive polarity is applied at third time.
  • the FLCD having 1024 scanning electrodes were driven every sixteen ones, and when four scanning electrodes were driven for a partial reloading after a single scanning electrode was driven for a refreshment, it took 360 ⁇ s to reload pixels on the single scanning electrode, and a display in which perceptible flickers are hardly caught can be obtained.
  • Fig. 41 shows a combination of voltage wveforms where the smallest voltage V0 in Fig. 14(A)(5) is made smaller in a range to V0/2 at the lowest, and contrarily the third largest voltage V0/2 is made larger in a range to V0 at the highest.
  • Fig. 41 shows a combination of voltage waveforms for reloading pixels on the scanning electrodes into a first stable state, similar to the conventional embodiment in Fig. 29(A), and the description about it is omitted.
  • Fig. 42 shows a waveform of voltage applied to the pixel A21
  • Fig. 42(2) shows at which angle the FLC molecules in Fig. 33 lie when the pixel A21 is in the first stable state
  • Fig. 42(3) shows an amount of light transmission when a deflection axis of a deflection plate is adjusted to the angle - ⁇ . It is found in Fig. 42 that swing of the FLC molecules just after the time 24t0 is considerably smaller than the angle 14° in Fig. 40.
  • Fig. 41(B) shows a combination of the selective voltage applied to a scanning electrodes for a refresh driving, reloading and non-reloading voltages for reloading pixels on the scanning electrodes into a second stable state and not, and a non-selective voltage applied to the scanning electrode
  • a combination of voltage waveforms in Fig. 41(B) can be used, where the first voltage -V0 in Fig. 14(B)(5) is made smaller in a range to -V0/2 at the lowest, and instead the third voltage -V0/2 is made larger in a range to -V0 at the highest.
  • Fig. 41(B) shows, similar to the conventional embodiment in Fig. 29(B), a combination of voltage waveforms for reloading the pixels on the scanning electrodes into a second stable state, and the description about it is omitted.
  • Combinations of voltage waveforms in Figs. 43 to 48(A) are combinations of voltage waveforms for reloading pixels on the scanning electrodes into a first stable state, similar to the conventional embodiment in Fig. 29(A), while combinations of voltage waveforms in Figs. 43 to 48(B) are combinations of voltage waveforms for reloading pixels on the scanning electrodes into a second stable state, similar to the conventional embodiment in Fig. 29(B), and the description about them is omitted.
  • Figs. 43 to 45 can be used.
  • Fig. 43(A) shows a combination of voltage waveforms when the first voltage V0 in Figs. 14(B)(5) is made smaller in a range to V0/2 at the lowest similar to Fig. 41(A) without a later compensation for it
  • Fig. 43(B) shows a combination of voltage waveforms when the lowest voltage -V0 in Fig. 14(B)(5) is made smaller in a range to -V0/2 at the lowest similar to Fig. 41(B) without later compensation for it.
  • Fig. 44 shows a combination of voltage waveforms reversed in polarity to the bias voltage in Fig. 14 for advancing a time when polarity of the bias voltage in Fig. 40 is altered and swing becomes larger by 4t0. In this way, it is also useful to stagger a time of the maximum light transmission when the bias voltage is applied, to make flicker less noticeable.
  • Fig. 44 is an improvement of the concept of Fig. 43, which shows a combination of voltage waveforms where it is intended that a larger amount of light transmission brought with the reloading of the pixels by the refresh driving after the time 24t0 should be absorbed as a high frequency component by slightly raising the bias voltage when the refresh driving is performed.
  • a combination of voltage waveforms in Fig. 46 may be used in the partial reloading drive.
  • the combination of voltage waveforms in Fig. 46 seem to be effective when a dielectric anisotropy of the FLC is negative.
  • Figs. 14 and Figs. 43 to 46 commonly denote that a time 4t0 is required, but actually, a time 3t0 is required and the voltage is zero for the last t0.
  • Fig. 14 is not exclusive but Fig. 43 may be an alternative.
  • control circuit 13 may operate as in Fig. 49 instead of Fig. 8, and the operation can be implemented with a slight variation of a logic formula for obtaining the drive mode H/R and voltage mode E/W.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0541399A2 (fr) * 1991-11-07 1993-05-12 Sharp Kabushiki Kaisha Contrôleur d'affichage pour un panneau d'affichage à cristaux liquides
WO2023216611A1 (fr) * 2022-05-13 2023-11-16 惠科股份有限公司 Procédé de commande de dispositif d'affichage et dispositif d'affichage

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0306822A2 (fr) * 1987-08-31 1989-03-15 Sharp Kabushiki Kaisha Dispositif d'affichage pour cristaux liquides ferroélectriques
EP0316774A2 (fr) * 1987-11-12 1989-05-24 Canon Kabushiki Kaisha Appareil à cristaux à cristaux liquides
EP0318050A2 (fr) * 1987-11-26 1989-05-31 Canon Kabushiki Kaisha Appareil d'affichage

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0306822A2 (fr) * 1987-08-31 1989-03-15 Sharp Kabushiki Kaisha Dispositif d'affichage pour cristaux liquides ferroélectriques
EP0316774A2 (fr) * 1987-11-12 1989-05-24 Canon Kabushiki Kaisha Appareil à cristaux à cristaux liquides
EP0318050A2 (fr) * 1987-11-26 1989-05-31 Canon Kabushiki Kaisha Appareil d'affichage

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0541399A2 (fr) * 1991-11-07 1993-05-12 Sharp Kabushiki Kaisha Contrôleur d'affichage pour un panneau d'affichage à cristaux liquides
EP0541399A3 (fr) * 1991-11-07 1994-01-12 Sharp Kk
US5483255A (en) * 1991-11-07 1996-01-09 Sharp Kabushiki Kaisha Display controller for liquid crystal panel structure
WO2023216611A1 (fr) * 2022-05-13 2023-11-16 惠科股份有限公司 Procédé de commande de dispositif d'affichage et dispositif d'affichage
US11942054B2 (en) 2022-05-13 2024-03-26 HKC Corporation Limited Driving method of display device, and display device

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KR950003982B1 (ko) 1995-04-21
DE69120044D1 (de) 1996-07-11
EP0492542A3 (en) 1993-05-19
KR920013231A (ko) 1992-07-28
EP0492542B1 (fr) 1996-06-05

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