EP0488818B1 - Convertisseur analogique/numérique - Google Patents

Convertisseur analogique/numérique Download PDF

Info

Publication number
EP0488818B1
EP0488818B1 EP91311166A EP91311166A EP0488818B1 EP 0488818 B1 EP0488818 B1 EP 0488818B1 EP 91311166 A EP91311166 A EP 91311166A EP 91311166 A EP91311166 A EP 91311166A EP 0488818 B1 EP0488818 B1 EP 0488818B1
Authority
EP
European Patent Office
Prior art keywords
converter
output
signal
converting means
integrating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP91311166A
Other languages
German (de)
English (en)
Other versions
EP0488818A1 (fr
Inventor
Hiroshi C/O Intell. Property Div. Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0488818A1 publication Critical patent/EP0488818A1/fr
Application granted granted Critical
Publication of EP0488818B1 publication Critical patent/EP0488818B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/42—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in parallel loops

Definitions

  • the present invention relates to an over-sampling type A/D converter and, more particularly, to an A/D converter capable of performing conversion at a high accuracy.
  • an over-sampling type A/D converter represented by a ⁇ - ⁇ modulator has received a great deal of attention as A/D converter in which an A/D conversion characteristic having higher accuracy than that of a conventional A/D converter can be obtained by using 1-bit (binary) A/D & D/A converters.
  • This A/D converter is a high-accuracy A/D converter suitable for an integrated circuit. That is, in this converter, even when an analog circuit element does not have high accuracy, an analog-to-digital conversion characteristic having high accuracy of, e.g., about 16 bits can be obtained.
  • the ⁇ - ⁇ modulator is described in the literature, e.g., "Over-sampling type A/D & D/A conversion technique (first to sixth)", Akira Yukawa, Nikkei Electronics, No. 453-460, 1989.
  • a ⁇ - ⁇ modulation type A/D converter comprising at least two integrators connected in series, a multibit A/D converter connected to a last integrator, and a plurality of D/A converters arranged in a feedback loop constituted by the integrators and the A/D converter, wherein the number of quantization levels of a feedback signal supplied to second and subsequent integrators is larger than the number of quantization levels of a feedback signal supplied to the first integrator.
  • a ⁇ - ⁇ modulation type A/D converter comprising first and second D/A converters for converting a digital signal into an analog signal, a first subtracter for subtracting an output signal from the first D/A converter from an input signal, a first integrator for integrating an output signal from the first subtracter, a second subtracter for subtracting an output of the second D/A converter from an output of the first integrator, a second integrator for integrating an output from the second subtracter, and an A/D converter for converting an output from the second integrator into a digital signal, wherein the output signal from the A/D converter is input to the first and second D/A converters, and output signals from the first and second converters are used as outputs from the ⁇ - ⁇ modulation type A/D converter.
  • an over-sampling type A/D converter includes N (N is an integer of not less than 2) integrators, one multibit A/D converter, and D/A converters.
  • a 1-bit signal is used as only a feedback signal supplied to the first integrator, and a multibit feedback signal having more than 3 values is supplied to the second and subsequent integrators. For this reason, a feedback signal having the highest accuracy is supplied to the first integrator, which influences the accuracy of the D/A converter more than any other integrator, to keep a whole S/N ratio to be high.
  • the multibit feedback signal is supplied to other integrators, which does not almost influences the accuracy of the D/A converter, to decrease output amplitudes of the second and subsequent integrators.
  • Fig. 1 is a view for explaining the principle of an A/D converter according to the present invention, and Fig. 1 shows the arrangement of an improved second-order ⁇ - ⁇ modulator. Note that a digital signal processing circuit is omitted in Fig. 1.
  • an input signal X is supplied to an input signal terminal 1.
  • a first stage integrator 2 is connected to a second stage integrator 3 through an adder 18, and the output terminal of the second stage integrator 3 is connected to the input terminal of a second A/D converter 4.
  • the output terminal of the second A/D converter 4 is connected to the input terminal of a second D/A converter 6 through an adder 21.
  • the output terminal of the second D/A converter 6 is connected to a coefficient multiplier 8 through an adder 19, and the output terminal of the coefficient multiplier 8 is connected to the adder 18.
  • the output terminal of a first A/D converter 9 is connected to the output terminal of the integrator 3, and the output terminal of the first A/D converter 9 is connected to the input terminal of a first D/A converter 11 through an adder 20.
  • Output signals Y1 and Y2 are output through first and second digital output terminals 13 and 14, respectively.
  • a clock CK is supplied to the A/D converters 4 and 9.
  • the first D/A converter 11 is a binary (1-bit) converter
  • the second D/A converter 6 is a multi-valued converter which has more than 3 values.
  • An output from the D/A converter 11 is imaginarily shown in Fig. 1, and the adder 16 adds the output of the D/A converter 11 to a noise signal D1 generated due to distortion generated in the D/A converter 11.
  • the value obtained by this addition is subtracted from the signal X input from the terminal 1, and the value obtained by this subtraction is integrated by the first stage integrator 2.
  • An output from the D/A converter 6 is imaginarily shown in Fig. 1, and the adder 19 adds the output of the D/A converter 6 to a noise signal D2 generated due to distortion generated in the D/A converter 6.
  • the value obtained by this addition is multiplied by a constant (e.g., two) in the coefficient multiplier 8, and the multiplication value is subtracted from the integrated value of the integrator 2 and input to the second integrator 3.
  • An output from the second stage integrator 3 is input to the A/D converters 4 and 9.
  • the digital outputs from the A/D converters 4 and 9 are input to the D/A converter 11 to be converted into analog signals again, and the analog signals are finally input to the integrators 2 and 3 so as to form a feedback loop.
  • Signals Q1 and Q2 respectively represent quantization noise components of the A/D converters 9 and 4, and the signals are imaginarily added to the output signals from the A/D converters 9 and 4 by the adders 20 and 21, respectively.
  • Signals D2 and D1 represent noise components caused by distortion generated in the D/A converters 6 and 11, respectively.
  • the coefficient of the coefficient multiplier is set to be 2.
  • a noise signal Q is output through a filter having second-order high-pass characteristic represented by (1 - Z ⁇ 1), and a noise signal D is output through a filter having characteristic represented by -Z ⁇ 1(2 - Z ⁇ 1). Therefore, although the noise signal Q having a largely attenuated low-frequency component is output, since the amplitude characteristic of the filter through which the noise signal D passes is set to be almost 1 when the angular frequency ⁇ is small, the low-frequency component of the noise signal D is output without being changed. For this reason, an S/N ratio equal to or higher than a finally necessary S/N ratio is required to the noise signal D, i.e., the accuracy of the D/A converter.
  • the signal D1 having the same transfer characteristic as that of the input signal X is output without being changed, the signal D2 is output through a filter having first-order high-pass characteristic represented by -2Z ⁇ 1(1 - Z ⁇ 1).
  • the noise signal D2 in the signal Y1, an influence of the noise signal D2 on low-frequency range noise is smaller than that of the noise signal D1, and the noise signal D2 rarely influences a decrease in S/N ratio of a whole ⁇ - ⁇ modulator, because the magnitude of (1 - Z ⁇ 1) is low when the angular frequency ⁇ is low.
  • the S/N ratio of the whole ⁇ - ⁇ modulator is controlled by the signal D1 but not by the signal D2.
  • the accuracy of the D/A converter 6 may be lower than that of the D/A converter 11. Therefore, in the conventional technique, the D/A converters 11 and 6 are not independently arranged, and a binary D/A converter is used commonly as these converters 11 and 6.
  • a multibit D/A converter can be used as the D/A converter 6 while an S/N ratio is rarely decreased.
  • the D/A converter 11 since the signal D1 is directly output, the D/A converter 11 requires an S/N ratio equal to or higher than a finally necessary S/N ratio.
  • the accuracy of a D/A converter obtained without trimming is about 13 bits at most, when accuracy higher than 13 bits is required, a binary D/A converter must be used even in the present invention.
  • the quantization noise signal Q1 generated by the A/D converter 9 outputs through a filter having high-pass filter characteristic represented by (1 - Z ⁇ ), and the quantization noise signal Q2 generated by the A/D converter 4 outputs through a filter having high-pass characteristic represented by -2Z ⁇ 1(1 - Z ⁇ 1).
  • the noise signal Q1 is compared with the noise signal Q generated by the converter having the conventional arrangement described in item 1, although the signal Q1 outputs to have a second-order differential characteristic, the signal Q1 is outputs to have a first-order differential characteristic.
  • quantization noise is increased compared with that in a conventional arrangement, and the low-frequency component of the quantization noise signal Q1 larger than that of the quantization noise signal Q is output.
  • the quantization noise signal Q2 is output to have the first-order differential characteristic, the quantization noise signal Q1 is generated according to binary A/D conversion, and the quantization noise signal Q2 is generated according to multibit A/D conversion. For this reason, the quantization noise signal Q2 can be easily reduced by increasing the number of bits. Therefore, in order to obtain a higher S/N ratio in the arrangement of the present invention than in the conventional arrangement, it is important that the effect of the quantization noise signal Q1 must be reduced by some method.
  • a method for reducing the effect of the quantization noise signal Q1 will be described below.
  • the A/D converter 9 as a 1-bit converter and the A/D converter 4 as a multibit A/D converter are used.
  • the right-hand side of equation (5) has the same form as that of the right-hand side of the first equation of equation (4), Q2 smaller than Q1 appears in place of Q, D1 appears in the first term of equation (5) in place of D, and D2 appears in the second term in place of D. That is, when the value of the left-hand member of equation (5) is calculated using the arrangement of the present invention, quantization noise can be greatly reduced compared with using the conventional arrangement.
  • D2 is not necessarily smaller than D1, since D2 is output through a first-order high-pass filter, though D1 is directly output, D2 is rarely superposed on output noise.
  • both the signals Y1 and Y2 are desirably obtained from the output from the multibit A/D converter 4.
  • a calculation capable of obtaining an actual method of decreasing an amount of hardware for digital calculation is preferably selected.
  • Fig. 2 obtained by summing up the above results is a block diagram for explaining an arrangement of the first embodiment of the present invention.
  • a description of the same parts as in Fig. 1 will be omitted.
  • an MSB (sign bit) of an output from the A/D converter 4 is used as an input of the 1-bit D/A converter 11, and the output Y2 is subtracted from an MSB (Y1) included in an output Y2 from the A/D converter 4 by a subtracter 22.
  • a value obtained by delaying the resultant signal Y1 - Y2 by 2 clocks in a delay circuit 23 is added to the signal Y2 by an adder 24, and the result is output to an output terminal 25.
  • the output amplitude of the second integrator 3 can be reduced. According to the arrangement of the present invention, since digital signal processing is performed by the adder 22, the delay circuit 23, and the adder 24, quantization noise at the output terminal 25 can be reduced compared with in a conventional arrangement.
  • a block diagram representing an arrangement of a general second-order ⁇ - ⁇ modulation type A/D converter including a coefficient ⁇ is shown in Fig. 3.
  • a digital signal processing circuit 50 shown in Fig. 3 performs digital signal processing for canceling noise.
  • noise caused by ⁇ appears at a level of about 110 dB or less of the full scale.
  • This increase in noise can be neglected, since a S/N ratio in 16 bits for example is about 96 dB. Therefore, when the present invention is applied, it is apparent that an increase in noise caused an error of a coefficient multiplier falls within a negligible range.
  • Fig. 4 is a view for explaining an improvement of the first embodiment of the present invention over the prior art, and Fig. 4 shows comparative simulationed output signal waveforms of a second integrator in a conventional second-order ⁇ - ⁇ modulator using a conventional 1-bit A/D ⁇ D/A converter and the second order ⁇ - ⁇ modulator applying the present invention.
  • the abscissa represents a normalized time, and the ordinate represents an output amplitude.
  • Fig. 4 the abscissa represents a normalized time, and the ordinate represents an output amplitude.
  • reference symbol (a) denotes an input signal waveform; (b), an output waveform of a second integrator when a binary converter as a conventional A/D ⁇ D/A converter; and (c), an output waveform of the second integrator when a 9-valued A/D converter, a 9-valued D/A converter, and a binary D/A converter are used as the A/D converter, the second D/A converter, and the first D/A converter according to the present invention, respectively. Comparing (b) with (c), the maximum value of the output amplitude of the second integrator is decreased to be half. Therefore, even when the 9-valued A/D and D/A converters are used, the effect of the present invention can be obtained.
  • Fig. 5 shows a result obtained by simulating a spectrum of an A/D conversion output obtained with the arrangement in Fig. 2.
  • the ordinate represents a spectrum of an output digital value in decibels
  • the abscissa represents a frequency normalized by a sampling frequency.
  • a noise component is decreased by about 15 dB and 30 dB, respectively, compared with a case wherein the quantization level of the D/A converter 6 is set to be binary.
  • the line spectrum of Fig. 5 is a spectrum generated by a sine-wave input signal having an amplitude of 0.5 V, and spectra other than the line spectrum are regarded as noise components.
  • This simulation is performed assuming that the range of the input full scale of the A/D converter is set to be ⁇ 2 V and that the sine-wave input signal is quantized to a 5-valued signal or 29-valued signal value within this range.
  • An output from the D/A converter 11 is a binary output of ⁇ 1 V, the D/A converter 6 directly converts the digital output from the A/D converter into an analog value. Therefore, in the A/D converter according to this embodiment, the range of the input full scale corresponds to ⁇ 1 V.
  • Fig. 6 is a view for explaining this advantage of the present invention.
  • the abscissa represents an input signal voltage
  • the ordinate represents the S/N ratio of a digital value converted by an A/D converter.
  • the full scale of the multibit converter is set to be twice the full scale of the first D/A converter, not only a total S/N ratio is increased, but saturation of an S/N ratio at a high input level which is characteristic of a conventional ⁇ - ⁇ modulator can be improved.
  • Distortion at a high input signal level can be decreased by setting the full scales of the A/D converter 4 and the D/A converter 6 to be larger than the full scale of the D/A converter 11 because of the following reasons. Since the second problem of the problems for the prior art has been described, i.e., since the output from the first integrator falls within a range about twice the maximum input range, the A/D converter 4 must have a full scale corresponding to this range. In a ⁇ - ⁇ modulation type A/D converter having a structure including a plurality of feedback loops shown in Figs. 1, 2, and 3 and Fig.
  • the A/D converter 4 since the maximum input range is equal to the range of the full scale of the D/A converter included in the outermost feedback loop, the A/D converter 4 must have a full scale having at least a range about twice that of the full scale of the D/A converter 11, and the full scale of the D/A converter 6 must correspond to the full scale of the A/D converter 4.
  • the local A/D converter is a 1-bit A/D converter. That is, since it is sufficient that only the code (polarity) of an output from an integrator is determined, the full scale itself of the A/D converter is meaningless. For this reason, the full scale of the 1-bit local D/A converter is appropriately determined, and a ⁇ - ⁇ modulation type A/D converter having a maximum input range equal to that of the full scale of the 1-bit local D/A converter is obtained.
  • Fig. 7 is a block diagram for explaining an arrangement of the second embodiment of the present invention.
  • an input X 1 is subtracted from an output from a D/A converter 11 by a subtracter 17, and an output from the subtracter 17 is input to an integrator 2 and integrated therein.
  • a subtracter 18 an output signal from the integrator 2 is subtracted from a signal obtained by multiplying an output signal from a D/A converter 6 by a predetermined coefficient in a coefficient multiplier 28.
  • a subtracter 27 After the subtracted signal is input to an integrator 3 and integrated therein, from the signal is subtracted by a subtracter 27 a signal obtained by multiplying an output signal from the D/A converter 6 by a predetermined coefficient in a coefficient multiplier 29.
  • This output signal is integrated in an integrator 26 and then input to an A/D converter 4 to be A/D-converted.
  • This A/D-converted value is fed back to the D/A converter 6 and the D/A converter 11.
  • an output signal from the A/D converter 4 is subtracted from the MSB of an output signal from the A/D converter 4 by a subtracter 22, and an output from the subtracter 22 is input to a delay circuit 23.
  • An output signal from the subtracter 22 is delayed by 3 clocks in the delay circuit 23, and this delayed signal and the output signal from the A/D converter are added to each other in an adder 24, thereby obtaining an output 25 from the adder 24. That is, the a ⁇ - ⁇ modulator described in the second embodiment is a third-order ⁇ - ⁇ modulator.
  • the third-order ⁇ - ⁇ modulator in Fig. 7 is different from the second-order ⁇ - ⁇ modulator shown in Fig. 2 by arranging an integrator 26. That is, according to this embodiment, three integrators are used. Therefore, in order to assure the stability of a feedback loop, the coefficients of the coefficient multipliers 28 and 29 must be set to be appropriate values; In the conventional technique, feedback signals are supplied to three integrators using a 1-bit local D/A comventer or a highly accurate multibit local D/A converter. According to the present invention, a feedback signal for the first integrator is supplied from a binary local D/A converter 11, feedback signals for the second and third integrators 3 and 26 are supplied from the multibit local D/A converter 6.
  • the local D/A converter which requires the highest accuracy and supplies a feedback signal to the first integrator 2 a binary converter which can be high precision even on an integrated circuit can be used.
  • a demand for the accuracy of the multibit local D/A converter 6 for supplying feedback signals to the second and third integrators 3 and 26 is mostly satisfied by the same reason as described in the first embodiment.
  • each of the gains of the coefficient multipliers 28 and 29 is set to be three times in consideration of their stability.
  • Equation (10) is preferably deformed such that an amount of calculation for digital signal processing is decreased, thereby realizing equation (10).
  • equation (11) can be realized by a digital signal processing circuit 50 in Fig. 7.
  • the delay circuit 23 performs 2-clock delay (Z ⁇ ) in the circuit having two integrators in Fig. 2, the delay circuit 23 performs 3-clock delay (Z ⁇ 3) in the second embodiment in Fig. 7.
  • Y1 and Y2 are described as inputs to the digital signal processing circuit 50, since the Y1 is a part of the Y2, it is sufficient to input only the Y2. This is also held in the digital processing section of the digital signal processing circuit 50.
  • the full scales of the A/D converter 4 and the D/A converter 6 are set to be smaller than the full scale of the D/A converter 11, a decrease in S/N ratio near an overloaded portion can be improved.
  • an amount represented by Y1 - (1 - Z ⁇ 3)(Y1 - Y2) is calculated in a digital form using the output (Y2) of the multibit A/D converter 4 and its MSB, i.e., a sign bit (Y1).
  • the second local D/A converter may be sufficiently multi-valued at first.
  • a feedback signal may be supplied from a multibit D/A converter 6 to the third integrator 26 such that 1-bit feedback signals are supplied to the first and second integrators 2 and 3.
  • the quantization noise of the right-hand side (output) can be suppressed to be lower than the noise Q1 of the binary A/D converter, and the error of the multibit D/A converter 6 passes through a second-order high-pass filter to be attenuated and is output. For this reason, influences of the quantization noise and the error are decreased to be smaller than that of the previous embodiment.
  • the second term of the right-hand side represents an error of a binary D/A converter, this value can be decreased to be negligible.
  • the output amplitude of the second integrator 3 cannot be suppressed to be small, and the output amplitude of the third integrator 26 is suppressed to only the same extent to that of the second integrator 3.
  • the digital signal processing circuit 50 has a complicated arrangement as shown in Fig. 8.
  • the 1-bit D/A converter 11 having a very small error is used for the first and second integrators 2 and 3
  • noise occurring due to the error of the D/A converter can be advantageously reduced compared with a case wherein a multibit D/A converter is used for the second and third integrators 3 and 26.
  • Fig. 9 shows a high-order, e.g., fourth or more order, A/D converter according to still another embodiment of the present invention.
  • an input terminal and a plurality of integrators INT1, INT2,... INTn are connected to each other in series through adders ADD1, ADD2,... ADDn.
  • a plurality of feedback loops FBL1, FBL2,... FBLn each of which is constituted by a D/A converter, an A/D converter, and a coefficient multiplier are connected to the adders ADD1, ADD2,... ADDn, respectively.
  • the node between the A/D converter and D/A converter of each of the feedback loops is connected to a digital signal processing circuit 50.
  • the number of quantization levels of each of the D/A converters of the inner feedback loops FBL2 FBLn is set to be equal to or larger than the number of quantization levels (1 bit) of the D/A converter of the outer feedback loop FBL1.
  • two or more feedback loops are arranged.
  • two feedback loops FBL1 and FBL2 are arranged, and the inner feedback loop FBL2 is a feedback loop connected to the outputs of adders ADD2,... ADDn through series-connected multibit A/D and D/A converters 4 and 6 and a plurality of coefficient multipliers.
  • the outer feedback loop FBL2 is a feedback loop connected to the first adder ADD1 through the multibit A/D converter 4, a 1-bit D/A converter 11, and a coefficient multiplier.
  • a digital signal processing circuit 50 is connected to the node between the A/D converter 4 and the D/A converters 6 and 11.
  • a D/A converter having a larger number of quantization levels is assigned as the inner feedback loop rather than as the outer feedback loop of the plurality of feedback loops of a ⁇ - ⁇ modulation type A/D converter.
  • this embodiment has a large degree of freedom of the above assignment, whether this embodiment or the embodiment in Fig. 9 is selected is a matter of design choice, and it may be determined in consideration of a given specification and realizability.
  • each of the integrators 2 and 3 may be constituted by a integrator of a continuous time system such as a normal active RC integrator expressed by variables of the Laplace transform.
  • a feedback signal for the first integrator is supplied from a binary local DAC
  • this local DAC is not actually limited to a binary one, and any highly accurate local D/A converter may be used.
  • a 3-valued D/A converter can be easily used on an integrated circuit with high accuracy.
  • a 3-valued D/A converter having values of ⁇ 1 V and 0 V can be obtained by the circuit shown in Fig. 11.
  • the voltage of a reference voltage supply 32 is set to be 1 V.
  • Capacitors 30 and 31 have the same value for obtaining a simple calculation.
  • Analog switches 34 and 40 are controlled as shown in Fig. 12.
  • switches 34 and 38 are turned on, and other switches are kept off, while a switch 35 periodically ON/OFF-controlled at a duty ratio of 1 : 1 is kept off (the ON and OFF states of the switches 40 and 35 are controlled to be opposite to each other).
  • Only a switch 37 is turned on in a period when the switch 35 is turned on, and other switches are turned off.
  • the capacitor 30 is temporarily charged such that the right (in Fig. 11) electrode is set to be positive.
  • the switch 35 is turned on, all the charges of the electrode are transmitted to the capacitor 31, and an output 34 of an operational amplifier 33 is set to be +1 V.
  • switches 34 and 39 are turned on, and other switches turned off. Only the switch 37 is turned off in a period wherein the switch 35 is turned on. With the above arrangement, the capacitor 30 is not charged.
  • the switch 35 is turned on, since there is no charge to be transmitted, no charge is transfered to the capacitor 31 discharged by the switch 40, and the output 34 of the operational amplifier 33 is set to be 0 V.
  • the switches 34 and 39 are turned off, and other switches are turned off. Only a switch 36 is turned on in a period wherein the switch 35 is turned on, and other switches are turned off.
  • the left electrode (in Fig. 11) of the capacitor 30 is connected to the positive terminal of the reference power supply 32, and the right electrode is connected an inverting input terminal of imaginary ground of the operational amplifier 33. Since the capacitor 30 is set in a discharging state at first, the left and right electrodes of the capacitor are charged by the reference power supply 32 to have voltages of +1 V and 0 V, and the charging currents are integrated by the capacitor 31. Since the capacitors 30 and 31 have the same value, a voltage of -1 V is output to the output terminal 34.
  • the opening and closing operations of the switches 34, 36, 35, 37, and 39 are preferably performed such that a logic circuit is formed to be controlled by a 3-valued signal constituted by an output from the A/D converter.
  • the clock signal 15 can be directly obtained from the switches 35 and 40.
  • a binary D/A converter may be obtained such that the 3-valued D/A converter outputs voltages of +1 V and -1 V except for a voltage of 0 V.
  • a logic circuit must be formed such that a control signal for a switch is controlled by the code bit of an output from an A/D converter.
  • an A/D converter having accuracy higher than that of a conventional A/D converter can be obtained.

Claims (17)

  1. Un convertisseur A/N comprenant :
    un ensemble d'étages de moyens d'intégration (2, 3, 26, INT₁-INRn) ayant des moyens d'intégration de premier étage (2, INT₁) pour recevoir un signal d'entrée, et des moyens d'intégration de dernier étage (26, INTn);
    au moins un moyen de conversion A/N (4) connecté à une borne de sortie des moyens d'intégration de dernier étage;
    au moins une boucle de réaction extérieure (FBL₀, FBL₁) connectée depuis une borne de sortie du moyen de conversion A/N (4) jusqu'aux moyens d'intégration de premier étage, au moins, et comprenant un premier moyen de conversion N/A (11); le convertisseur A/N étant caractérisé par
    un ensemble de boucles de réaction intérieures (FBL₁, FBL₂-FBLn) comprenant un second moyen de conversion N/A connecté entre la borne de sortie du moyen de conversion A/N et l'ensemble d'étages de moyens d'intégration qui sont disposés après les moyens d'intégration de premier étage; et
    un moyen (50), connecté à la borne de sortie du moyen de conversion A/N, pour effectuer un traitement de signal numérique d'un signal de sortie du moyen de conversion A/N, afin d'éliminer un bruit de quantification qui est occasionné par la boucle de réaction extérieure,
    dans lequel le second moyen de conversion N/A qui est incorporé dans la boucle de réaction intérieure a un nombre de niveaux de quantification supérieur à celui du premier moyen de conversion N/A qui est utilisé dans la boucle de réaction extérieure.
  2. Le convertisseur A/N selon la revendication 1, caractérisé en ce que le premier moyen de conversion N/A qui est incorporé dans la boucle de réaction extérieure est constitué par un convertisseur N/A à 1 bit (11), et le second moyen de conversion N/A qui est incorporé dans les boucles de réaction intérieures est constitué par un convertisseur N/A multibit (6).
  3. Le convertisseur A/N selon la revendication 1, caractérisé en ce qu'il comprend en outre un ensemble de multiplieurs de coefficients (Ml, Mn), connectés entre le second moyen de conversion N/A et l'ensemble d'étages de moyens d'intégration, pour multiplier un signal de sortie du moyen de conversion N/A par un coefficent prédéterminé.
  4. Le convertisseur A/N selon la revendication 1, caractérisé en ce que le second moyen de conversion N/A est constitué par un ensemble de convertisseurs N/A multibits (N/A) connectés entre la borne de sortie du moyen de conversion A/N et des bornes d'entrée des moyens d'intégration.
  5. Le convertisseur A/N selon la revendication 4, caractérisé en ce qu'il comprend en outre un ensemble de multiplieurs de coefficents (Ml-Mn), connectés entre l'ensemble d'étages de moyens d'intégration et l'ensemble de convertisseurs N/A multibits, pour multiplier un signal de sortie de chacun des moyens de conversion A/N par un coefficient prédéterminé.
  6. Le convertisseur A/N selon la revendication 1, caractérisé en ce que le premier moyen de conversion N/A est constitué par un convertisseur N/A à 1 bit (11) connecté à une borne d'entrée des moyens d'intégration de premier étage (2), et à une borne d'entrée des moyens d'intégration d'étage suivant (3), placés à la suite des moyens d'intégration de premier étage.
  7. Le convertisseur A/N selon la revendication 1, caractérisé en ce que les moyens d'intégration de premier étage comprennent des moyens (17) pour soustraire le signal d'entrée d'un signal de sortie du premier moyen de conversion N/A (11) et pour fournir en sortie un résultat de soustraction, et un intégrateur (2) pour intégrer le résultat de soustraction, et chacun des autres moyens d'intégration est constitué par un moyen (18) destiné à soustraire un signal de sortie des moyens d'intégration de premier étage (2) d'un signal de sortie du second moyen de conversion N/A (6) et à fournir en sortie un résultat de soustraction, et par un intégrateur pour intégrer le résultat de soustraction.
  8. Le convertisseur A/N selon la revendication 1, caractérisé en ce que le moyen destiné à effectuer un traitement de signal numérique comprend un moyen (50) pour annuler le bruit de quantification qui est occasionné par la boucle de réaction extérieure, par un signal de sortie du moyen de conversion A/N et un signal de bit de signe dans le signal de sortie.
  9. Le convertisseur A/N selon la revendication 1, caractérisé en ce que le moyen destiné à effectuer un traitement de signal numérique comprend un moyen (22) pour soustraire un signal de bit de signe dans un signal de sortie, d'un signal de sortie du moyen de conversion A/N, et pour fournir en sortie un signal de différence, un moyen (23) pour retarder le signal de différence d'une durée prédéterminée et pour fournir en sortie un signal retardé, et un moyen (24) pour additionner le signal de sortie du moyen de conversion A/N et le signal retardé.
  10. Le convertisseur A/N selon la revendication 1, caractérisé en ce que le moyen de conversion A/N (4) a une valeur de pleine échelle supérieure à l'amplitude maximale d'un signal de sortie provenant des moyens d'intégration de dernier étage.
  11. Le convertisseur A/N selon la revendication 1, caractérisé en ce que le moyen de conversion A/N (4) a une valeur de pleine échelle supérieure à celle du premier moyen de conversion N/A qui est incorporé dans la boucle de réaction extérieure.
  12. Le convertisseur A/N selon la revendication 1, caractérisé en ce que le second moyen de conversion N/A (6) utilisé dans les boucles de réaction intérieures a une valeur de pleine échelle supérieure à celle du premier moyen de conversion N/A qui est utilisé dans la boucle de réaction extérieure.
  13. Un convertisseur A/N comprenant :
    un ensemble d'étages de moyens d'intégration ayant des moyens d'intégration de premier étage (INT₁) destinés à recevoir un signal d'entrée, et des moyens d'intégration de dernier étage (INTn);
    un convertisseur A/N multibit (4) connecté à une borne de sortie des moyens d'intégration de dernier étage;
    une boucle de réaction extérieure (FBL0) connectée entre une borne de sortie du convertisseur A/N multibit et une borne d'entrée des moyens d'intégration de premier étage, et comprenant un convertisseur N/A à 1 bit (11); le convertisseur A/N étant caractérisé par :
    une boucle de réaction intérieure (FBL1) comprenant un convertisseur N/A multibit (6) connecté entre la borne de sortie du convertisseur A/N multibit (4) et des bornes d'entrée de l'ensemble de moyens d'intégration d'étages se trouvant après les moyens d'intégration de premier étage (INT₁); et
    des moyens (50), connectés à la borne de sortie du convertisseur A/N multibit (4), pour effectuer un traitement de signal numérique d'un signal de sortie du convertisseur A/N multibit (4), afin d'éliminer du bruit de quantification qui est occasionné par la boucle de réaction extérieure (figure 10).
  14. Le convertisseur A/N selon la revendication 13, caractérisé en ce qu'il comprend en outre un ensemble de multiplieurs de coefficients (M₁-Mn), connectés entre le convertisseur N/A multibit et l'ensemble de moyens d'intégration, pour multiplier un signal de sortie du convertisseur N/A multibit par un coefficient prédéterminé.
  15. Le convertisseur A/N selon la revendication 13, caractérisé en ce que les premiers moyens d'intégration comprennent des moyens (ADD₁) pour soustraire le signal d'entrée d'un signal de sortie qui provient des premiers moyens de conversion N/A (11) et pour fournir en sortie un résultat de soustraction, et un intégrateur (INT₁) pour intégrer le résultat de soustraction, et chacun des autres moyens d'intégration comprend des moyens pour soustraire un signal de sortie des premiers moyens d'intégration, d'un signal de sortie du second moyen de conversion N/A, et pour fournir en sortie un résultat de soustraction, et un intégrateur pour intégrer le résultat de soustraction.
  16. Le convertisseur A/N selon la revendication 13, caractérisé en ce que le moyen destiné à effectuer un traitement de signal numérique comprend un moyen (22) pour soustraire un signal de bit de signe, d'un signal de sortie qui provient du convertisseur A/N, et pour fournir en sortie un signal de différence, un moyen (23) pour retarder le signal de différence d'une durée prédéterminée et pour fournir en sortie un signal retardé, et un moyen (24) pour produire le signal de sortie à partir du convertisseur A/N et du signal retardé.
  17. Le convertisseur A/N selon la revendication 13, caractérisé en ce que le convertisseur N/A multibit (6) qui est utilisé dans les boucles de réaction intérieures a une valeur de pleine échelle supérieure à celle du convertisseur N/A à 1 bit qui est utilisé dans la boucle de réaction extérieure.
EP91311166A 1990-11-30 1991-11-29 Convertisseur analogique/numérique Expired - Lifetime EP0488818B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP32950490 1990-11-30
JP329504/90 1990-11-30

Publications (2)

Publication Number Publication Date
EP0488818A1 EP0488818A1 (fr) 1992-06-03
EP0488818B1 true EP0488818B1 (fr) 1996-01-10

Family

ID=18222114

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91311166A Expired - Lifetime EP0488818B1 (fr) 1990-11-30 1991-11-29 Convertisseur analogique/numérique

Country Status (4)

Country Link
US (1) US5162799A (fr)
EP (1) EP0488818B1 (fr)
JP (1) JP3048452B2 (fr)
DE (1) DE69116324T2 (fr)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329282A (en) * 1992-03-02 1994-07-12 Motorola, Inc. Multi-bit sigma-delta analog-to-digital converter with reduced sensitivity to DAC nonlinearities
DE59205500D1 (de) * 1992-03-12 1996-04-04 Siemens Ag Sigma-Delta-Modulator
JP3310114B2 (ja) * 1994-09-14 2002-07-29 株式会社東芝 周波数変換機能を有するａ／ｄ変換装置およびこれを用いた無線機
US5646621A (en) * 1994-11-02 1997-07-08 Advanced Micro Devices, Inc. Delta-sigma ADC with multi-stage decimation filter and gain compensation filter
US5621675A (en) * 1994-11-02 1997-04-15 Advanced Micro Devices, Inc. Digital decimation and compensation filter system
US5648779A (en) * 1994-12-09 1997-07-15 Advanced Micro Devices, Inc. Sigma-delta modulator having reduced delay from input to output
US5736950A (en) * 1995-01-31 1998-04-07 The United States Of America As Represented By The Secretary Of The Navy Sigma-delta modulator with tunable signal passband
US5760722A (en) * 1995-01-31 1998-06-02 The United States Of America As Represented By The Secretary Of The Navy Distributed quantization noise transmission zeros in cascaded sigma-delta modulators
US5751615A (en) * 1995-11-14 1998-05-12 Advanced Micro Devices, Inc. Implementation of a digital decimation filter and method
US5732004A (en) * 1995-11-14 1998-03-24 Advanced Micro Devices, Inc. DSP architecture for a FIR-type filter and method
US5982313A (en) * 1997-06-06 1999-11-09 Analog Devices, Inc. High speed sigma-delta analog-to-digital converter system
US5936562A (en) * 1997-06-06 1999-08-10 Analog Devices, Inc. High-speed sigma-delta ADCs
US5942999A (en) * 1997-08-08 1999-08-24 International Business Machines Corporation Controllable integrated linear attenuator for a D/A converter
CA2229737A1 (fr) * 1998-02-18 1999-08-18 Philsar Electronics Inc. Convertisseur analogique/numerique pour applications radioelectriques
US6600788B1 (en) * 1999-09-10 2003-07-29 Xilinx, Inc. Narrow-band filter including sigma-delta modulator implemented in a programmable logic device
KR20020059389A (ko) * 2000-07-05 2002-07-12 롤페스 요하네스 게라투스 알베르투스 마이크로폰과 ａ/ｄ 변환기 회로의 결합체
IT1315978B1 (it) * 2000-07-31 2003-03-26 St Microelectronics Srl Metodo per ripristinare la stabilita' di un modulatore sigma-delta ecircuito per mettere in pratica tale metodo.
JP3705098B2 (ja) * 2000-09-01 2005-10-12 日本電気株式会社 マルチビットデルタシグマａｄ変換器
DE60018573T2 (de) * 2000-10-25 2006-01-19 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Verbesserung des Signal/Rausch-Verhältnisses eines Sigma/Delta-Modulators und dieses Verfahren benutzender Schaltkreis
US6683551B1 (en) * 2002-08-15 2004-01-27 Lsi Logic Corporation Digital-to-analog converter and method of operation
US8384559B2 (en) * 2010-04-13 2013-02-26 Silicon Laboratories Inc. Sensor device with flexible interface and updatable information store
JP4840947B2 (ja) * 2010-06-07 2011-12-21 ルネサスエレクトロニクス株式会社 Ａ／ｄ変換回路を内蔵した半導体集積回路
US8325073B2 (en) * 2010-11-30 2012-12-04 Qualcomm Incorporated Performing enhanced sigma-delta modulation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2523756B2 (ja) * 1988-02-01 1996-08-14 日本電信電話株式会社 Ａ／ｄ変換器
EP0399738A3 (fr) * 1989-05-26 1991-05-08 Gec-Marconi Limited Convertisseur analogique-numérique

Also Published As

Publication number Publication date
DE69116324T2 (de) 1996-06-13
JP3048452B2 (ja) 2000-06-05
US5162799A (en) 1992-11-10
EP0488818A1 (fr) 1992-06-03
DE69116324D1 (de) 1996-02-22
JPH053436A (ja) 1993-01-08

Similar Documents

Publication Publication Date Title
EP0488818B1 (fr) Convertisseur analogique/numérique
US5084702A (en) Plural-order sigma-delta analog-to-digital converter using both single-bit and multiple-bit quantizers
KR0181953B1 (ko) 단일 비트 및 다중 비트 양자화를 이용하는 복수차 시그마-델타 아날로그-디지탈 변환기
EP0368610B1 (fr) Méthode pour mettre en cascade plusieurs modulateurs sigma delta et un système modulateur sigma delta
EP0513241B1 (fr) Modulateur sigma delta
US5181032A (en) High-order, plural-bit-quantization sigma-delta modulators using single-bit digital-to-analog conversion feedback
US6744392B2 (en) Noise shapers with shared and independent filters and multiple quantizers and data converters and methods using the same
US6150969A (en) Correction of nonlinear output distortion in a Delta Sigma DAC
KR100928406B1 (ko) 증분-델타 아날로그-대-디지털 변환
JP2001094429A (ja) アナログデジタル混在δς変調器
JPH07283736A (ja) シグマ−デルタ形アナログ−ディジタル変換器の分解能の延長方法および装置
JP2995907B2 (ja) アナログ・デジタル変換器および出力補正方法
JP3362718B2 (ja) マルチビット−デルタシグマａｄ変換器
USRE42387E1 (en) Method for compensating non-linearity of a sigma-delta analog-to-digital converter
EP1442526A1 (fr) Procede et dispositif de conversion de taux d'echantillonnage
JP2001077692A (ja) Ｄ／ａ変換回路
JP3965475B2 (ja) Ｄ／ａ変換器
JP2003209472A (ja) デルタシグマ変調回路およびデルタシグマ変調型ｄａコンバータ
JPH08162961A (ja) Ａ／ｄ変換器
Adams et al. A novel architecture for reducing the sensitivity of multibit sigma-delta ADCs to DAC nonlinearity
KR940009102B1 (ko) 비대칭 신경회로망을 이용한 오버샘플링 아날로그/디지탈 변환기
Neitola et al. Study of fully digital error correction in multibit delta-sigma A/D converters
Wulff et al. Analog Modulo Integrator For Use In Open-Loop Sigma-Delta Modulators
Márkus et al. 16 Converters
JPH06291667A (ja) Ａｄ変換器

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19911220

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 19950317

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 69116324

Country of ref document: DE

Date of ref document: 19960222

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: 746

Effective date: 19980917

REG Reference to a national code

Ref country code: FR

Ref legal event code: D6

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20021108

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20021127

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20021205

Year of fee payment: 12

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20031129

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20040602

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20031129

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20040730

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST