US6683551B1 - Digital-to-analog converter and method of operation - Google Patents
Digital-to-analog converter and method of operation Download PDFInfo
- Publication number
- US6683551B1 US6683551B1 US10/219,638 US21963802A US6683551B1 US 6683551 B1 US6683551 B1 US 6683551B1 US 21963802 A US21963802 A US 21963802A US 6683551 B1 US6683551 B1 US 6683551B1
- Authority
- US
- United States
- Prior art keywords
- controllable current
- digital
- current sources
- state
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005070 sampling Methods 0.000 claims abstract description 48
- 230000007704 transition Effects 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 11
- 230000008859 change Effects 0.000 claims description 40
- 230000004044 response Effects 0.000 claims description 10
- 230000001934 delay Effects 0.000 claims 2
- 239000002674 ointment Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 32
- 230000000694 effects Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 8
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000002301 combined effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
Definitions
- the present invention may relate to a digital-to-analog converter (DAC), and may be directed to reducing a settling time of an analog output from the DAC.
- DAC digital-to-analog converter
- the invention may be suitable for implementation in an integrated circuit.
- the settling time is the time for the analog output to stabilize to within a certain tolerance, or margin, for example, to within a certain percentage of the final output value.
- FIG. 1 depicts schematically a conventional integrated circuit DAC 10 , and parasitic impedances at the analog output which increase the settling time undesirably.
- the DAC 10 includes a semiconductor die 12 including an arrangement of current sources 14 whose outputs are summed.
- the summed output current i.e., I S
- I S The summed output current
- An analog voltage is developed in a circuit 20 external to the integrated circuit DAC 10 by passing the current through a load resistor 22 .
- the current sources 14 are controlled simultaneously so that, when the output current changes, the current sources produce a substantial step change in I S .
- the parasitic capacitance 24 limits a slew rate of the generated analog voltage.
- the parasitic capacitance 24 includes the output capacitance of the DAC 10 , and capacitances of the external circuit 20 .
- the parasitic capacitance slows the rate at which a current (i.e., I L ) in the load resistor 22 can change.
- I L a current
- the change in I L takes the form of an exponential change, defined by an RC time constant where R is the value of the load resistor 22 and C is the value of the parasitic capacitance 24 .
- a high value of the load resistor 24 is often used to enable a reasonable voltage to be developed despite the low current.
- a high load resistor 24 increases the RC time constant, and hence the settling time, undesirably.
- the parasitic inductance 26 For high frequency applications having rapid changes, a higher current is often used to enable the value of the load resistor 24 (and thus the RC time constant) to be reduced. However, for high current applications, a parasitic inductance 26 resulting from the leadwire 16 becomes significant. The parasitic inductance 26 , coupled with the parasitic capacitance 24 , forms a resonant circuit which creates ringing in the output current I L . Referring to FIG. 3, for a step change in I S , the change in I L takes the form of an exponentially decreasing ringing superimposed on the exponential change of FIG. 2 . The magnitude of the ringing can often be as much as several bits of the DAC resolution. The settling time is adversely affected, because the output I L does not stabilise until the ringing has decayed.
- the invention may relate to a digital to analog converter.
- the digital to analog converter may comprise a plurality of controllable current sources and a control circuit.
- the plurality of controllable current sources may include a first and a second controllable current source. Each of the plurality of controllable current sources may be controllable between a first state and a second state.
- the control circuit may be coupled to the plurality of controllable current sources.
- the control circuit may be configured to control digital to analog conversion at sampling intervals.
- the control circuit may be configured to control a first state transition of the first controllable current source at a timing in the sampling interval different from a second state transition of the second controllable current source.
- FIG. 1 is a schematic diagram illustrating the sources of parasitic impedances in a conventional DAC
- FIG. 2 is a schematic diagram showing the effect of parasitic capacitance at the output of the conventional DAC
- FIG. 3 is a schematic diagram showing the combined effect of parasitic capacitance and parasitic inductance at the output of the conventional DAC;
- FIG. 4 is a schematic block diagram illustrating a DAC in accordance with a preferred embodiment of the invention.
- FIG. 5 is a schematic circuit diagram showing a switchable current source used in the DAC of FIG. 4;
- FIG. 6 is a schematic illustration of signals in the DAC of FIG. 4 showing the effect of a momentary boost current
- FIG. 7 is a schematic block diagram showing a detail of the DAC in a second embodiment
- FIG. 8 is a schematic illustration of signals in the DAC of FIG. 4 showing the effect of staggered timing
- FIG. 9 is a schematic block diagram showing a detail of the DAC in a third embodiment.
- FIG. 10 is a schematic block diagram showing a detail of the DAC in a fourth embodiment
- FIG. 11 is a schematic representation of output simulations to compare the effect of staggered and non-staggered timings.
- FIG. 12 is a more detailed view of a portion of FIG. 11 .
- an integrated circuit 50 may generally comprise a housing or package 52 containing a semiconductor die 54 .
- a circuit including a DAC 56 On the die 54 may be formed a circuit including a DAC 56 .
- the circuit may also include other circuit elements, such as a processor (not shown), memory (not shown) and other interface circuits (not shown), or the circuit may be primarily the DAC 56 .
- the DAC 56 may generally comprise an arrangement of controllable current sources 58 controlled by respective control signals 60 from a decoder 62 .
- the controllable current sources 58 may be controllable between first and second states. One state may be an “on” state, and the other state may be an “off” state.
- the controllable current sources 58 may be switchable current sources, as referred to below. For the sake of illustration, only two specific switchable current sources 58 a and 58 b are shown in FIG. 4, although the number of switchable current sources 58 may be tens, hundreds or thousands.
- the decoder 62 may be operative to sample a digital input signal 64 and to decode the digital input signal 64 into the plurality of control signals 60 for controlling the current sources 58 .
- the magnitude of the current from each switchable current source 58 may be equal, or the magnitude may vary from one switchable current source 58 , or group of switchable current sources 58 , to another.
- the output currents from the current sources 58 may be summed to provide an output current (e.g., I S ) at terminal 66 of the semiconductor die.
- the magnitude of the current I S at the terminal 66 may be proportional to the magnitude of the digital value of the digital input signal 64 .
- the decoder 62 , and a clock signal/timing controller 63 may control the DAC 56 to perform digital to analog conversion at sampling intervals.
- Each switchable current source 58 may generally be of a current-steering type, as illustrated in FIG. 5 .
- each switchable current source 58 may generally have a first current terminal 73 , a second current terminal 74 and a third current terminal 75 .
- the first current terminal 73 may, for example, be coupled to a first voltage supply, for example, VDD.
- the second and third current terminals 74 and 75 may be terminals to which a current to or from the first terminal 73 is selectively steered.
- Each switchable current source 58 may generally comprise a differential transistor pair 68 a and 68 b coupled to a constant or stable current source 70 .
- a current (e.g., I R ) delivered by the stable current source 70 from the first terminal 73 may be set by an external reference.
- the current I R may be steered through either one or the other of the differential transistors 68 a and 68 b , depending on differential control signals (e.g., Q and not Q) applied to the differential transistors 68 a and 68 b from switching logic 72 .
- the current I R may be fed to the second terminal 74 coupled to the output summing terminal 66 to contribute to the output current I S from the DAC 56 .
- the switchable current sources 58 may be referred to as switched “on” while contributing to the output current I R .
- the current I R When the current I R is steered through the other transistor 68 a , the current I R may be sunk internally within the DAC 56 , and may not contribute to the output current I S from the DAC 56 .
- the current I R may be fed via the third terminal 75 to a second supply voltage, for example, to ground.
- the switchable current sources 58 may be referred to as switched “off” while not contributing to the output current I S .
- Such a current-steering circuit may be preferred as “steering” using a differential transistor pair may be faster than switching a stable current source on or off.
- the switching logic 72 may generally comprise an input latch 76 for latching the control signal 60 from the decoder 62 , and a flip-flop 78 coupled between the input latch 76 and the differential transistors 68 a and 68 b .
- the flip-flop 78 may receive a clock signal 80 from the decoder 62 for controlling a timing of the application of the control signal 60 to the differential transistors 68 a and 68 b .
- the use of such a clock signal 80 may enable the timing of the switchable current sources 58 to be controlled independently of the timing of the control signal 60 .
- a leadwire or a leadwire network 82 may couple the output terminal 66 of the semiconductor die 54 to a connector pin 84 of the package 52 for connection to an external circuit 86 .
- the external circuit 86 may generally include a resistor 88 for developing a voltage proportional to the output current I S from the DAC 56 .
- the resistor 88 may be implemented on the semiconductor die 54 .
- the settling time of the output from the DAC (as observed by a current I L through the resistor 88 ) may be adversely affected by one or more parasitic impedances, for example, a parasitic inductance 90 and/or parasitic capacitances 92 .
- the parasitic inductance 90 may result from the effect of the leadwire 82 .
- the parasitic capacitance 92 may be a combination of capacitances in the external circuit 86 , the package 52 , and an output capacitance of the DAC 56 .
- the timing of one of more of the switchable current sources 58 may be controlled to at least partly compensate for the effect of the parasitic impedances.
- One or more of the switchable current sources 58 a may be controlled at a timing different from one or more other switchable current sources 58 b .
- the timing may include switching “on” one or more switchable current sources 58 a at a timing different from one of more other switchable current sources 58 b , and/or switching “off” one or more switchable current sources 58 a at a timing different from one or more other switchable current sources 58 b.
- one or more of the switchable current sources may be used to provide a short duration impulse current, also referred to herein as a “boost” current, which may compensate for the effect of parasitic capacitances 92 .
- the boost current may be generated at or near the beginning of a sampling interval.
- the boost current may reduce the time taken for the parasitic capacitances 92 to charge/discharge.
- the “boost” current may be turned “on” when initially changing the output current I S , and may be turned off a short period thereafter.
- the decoder 62 may generate a respective control signal 60 b for controlling the second switchable control source 58 b to transition at time (e.g., T 0 ) at the beginning of a sampling interval, from an “off” state to an “on” state, to generate a respective current (e.g., I 2 ).
- the second switchable current source 58 b may remain in its switched state for at least the majority of the remainder of the sampling interval.
- the decoder 62 may generate a respective control signal 60 a to control the first current source 58 a to turn “on” momentarily between time T 0 and a later time (e.g., T 1 ), to generate a momentary boost signal (e.g., I 1 ).
- the output signal I S may be I 1 +I 2 during the period T 0 to T 1 , and may be I 2 after the time T 1 .
- the current IL through the resistor 88 may rise more quickly as a result of the combined currents I 2 , +I 2 than merely from the current I 2 , to provide a shorter settling time.
- the broken line 102 may indicate the current I L resulting merely from the current I 2 , the broken line 102 having a longer settling time.
- the switchable current sources 58 used to provide the momentary boost signal may be one or more of the switchable current sources 58 which may be normally be used to create a stable output current I S .
- the switchable current sources 58 available to generate the boost signal may be restricted to only those switchable current sources 58 which are not currently in use to generate the stable output signal.
- one or more switchable current sources 58 may be dedicated only for generating a momentary boost signal, and not for use in generating a stable output signal.
- FIG. 7 illustrates a second embodiment, similar to the first embodiment, in which dedicated boost or impulse current sources 104 a and 104 b are provided for generating a momentary boost current signal to supplement the current provided by the switchable current sources 58 a and 58 b used for generating stable output currents.
- the boost current sources 104 a and 104 b may be coupled so that one of the boost current sources 104 a may be operative to generate a boost current in a first sense, and the other boost current source 104 b may be operative to generate a boost current in an opposite sense.
- One boost current source 104 a may add a boost current to the output current I S , and the other boost current source 104 b may be operative to sink a boost current relative to the output current I S .
- the first boost current source 104 a may be coupled with its first terminal ( 73 in FIG. 5) coupled to a first supply voltage (e.g.,VDD) and its third terminal ( 75 in FIG. 5) coupled to a second supply voltage (e.g., ground), and the second boost current source 104 b may be coupled with its first terminal ( 73 in FIG. 5) coupled to the second supply voltage (e.g., ground) and its third terminal coupled to the first supply voltage (e.g., VDD).
- the decoder 62 may include a first control section 62 a for generating respective control signals 60 for controlling the switchable current sources 58 a and 58 b for generating stable output signals.
- the control signals 60 may vary in response to the magnitude of the digital input signal 64 .
- the decoder 62 may further include a second control section 62 b for generating respective control signals 106 a and 106 b for controlling the dedicated boost current sources 104 a and 104 b .
- the second control section 62 b may generally include a register 108 to provide a digital input 110 delayed by one sampling interval, and detection and/or comparison logic 112 for comparing the actual digital input 64 with the delayed input 110 .
- the comparison logic 112 may function to detect whether there may be a change in the value of the digital input signal 64 from one sampling interval to the next, and to detect the magnitude and/or direction of change (for example, whether the change will result in an increase or decrease in the desired stable output current I S ) If the change results in an increase in I S , the control signal 106 a may be generated to cause the first boost current source 104 a to provide a boost signal to increase the current I S momentarily. The boost current may help to charge the parasitic capacitances 92 quickly, and thereby reduce the settling time of the increased current. If the change results in a decrease in I S , the control signal 106 b may be generated to cause the second boost current source 104 b to sink current from I S momentarily. The boost-sink may help to discharge the parasitic capacitances 92 quickly, and thereby reduce the settling time of the decreased current. In general, the control signals 106 a and 106 b may not be turned on concurrently with each other.
- the magnitude of the boost effect may be preset or controlled variably.
- the magnitude of the boost effect may be controlled by controlling the magnitude of the currents supplied or sunk by the boost current sources 104 a and 104 b .
- multiple boost current sources 104 a and multiple boost current sources 104 b may be provided.
- the magnitude of the boost current may be controlled by controlling a number of the multiple boost current sources 104 a or 104 b which are turned on.
- the magnitude of the boost effect may be controlled by controlling a duration for which either of the boost current sources 104 a and 104 b may be turned on.
- the second control section 62 b may generate control signals 106 a and 106 b for controlling the magnitude of the boost effect variably depending on the magnitude of the change in the digital input 64 .
- the magnitude of the boost effect may be fixed, and the second control section 62 b may determine whether or not to turn on either of the boost current sources 104 a and 104 b depending on whether the magnitude of the change in the digital input 64 exceeds a certain threshold.
- a mode of operation of the section control section 62 b and of the boost current sources 104 a and 104 b may be fixed in the design of the control section 62 implemented in the integrated circuit 50 or controllable programmably.
- the boost current sources 104 a and 104 b may be of the same current steering type as the current sources 58 described above, or the boost current sources 104 a and 104 b may be of a different circuit design. Less importance may be placed on the boost current sources 104 a and 104 b to deliver a stable current than for the other current sources 58 .
- a function of the boost current sources may be to deliver or sink an “impulse” current. Therefore, boost current sources 104 a and 104 b may be configured for an impulse current rather than for a stable current.
- the principle of applying a short duration boost or impulse current at the output may enable a low current DAC 56 to be used with a high value load internal or external resistor 88 , without sacrificing settling time.
- the impulse current may therefore enable a desired settling time to be achieved for a low current, with the consequent advantage of low average power dissipation.
- the boost or impulse currents may be applied only for short durations when needed in response to a change of the digital input 64 .
- the duration of the boost currents may typically be of the order of nanoseconds (ns). For example, the duration may be between 1 and 100 ns.
- FIG. 8 illustrates a further example of turning “on” or “off” the switchable current sources 58 a and 58 b of the first embodiment, at different timings.
- the example may be suitable for situations in which the effects of the parasitic inductance 90 and the parasitic capacitances 92 combine to produce ringing in the output current I L in the load resistor 88 .
- ringing may occur in relatively high current and/or high frequency DAC applications, for example, for video applications, certain communications and television applications, or where the DAC 56 is generally intended for operation at a clock frequency of about 100 megahertz (MHz) or more.
- the clock frequency may be of about 135 MHz or more, or of about 200 MHz of more, or of about 250 MHz or more.
- FIG. 8 may represent a situation in which two or more of the switchable current sources 58 a and 58 b are to be turned on in the same sampling interval in response to a change in the digital input 64 .
- a first control signal 120 a may control the first current source 58 a to be turned on at a time (e.g., T 1 ) at or near a beginning of the sampling interval. The first current source 58 a may remain on at least for at least a majority of the remainder of the sampling interval.
- a second control signal 120 b may control the second current source 58 b to be turned on at a time (e.g., T 2 ) later than T 1 . The second current source 58 b may remain on for at least the majority of the remainder of the sampling interval.
- One or more other current sources 58 intended to be turned on during the same sampling interval may also be turned on at one or more other timings, near or at the beginning of the sampling interval, but staggered with respect to T 1 and/or to T 2 .
- the other current sources 58 may remain on for at least the majority of the remainder of the sampling interval.
- each time a current source 58 is turned on the output current I S may increase by a corresponding small step amount 122 . Since at least some of the current sources 58 may be turned on at a staggered timing, the step amounts 122 may be significantly smaller than the single step change that would occur if the same current sources 58 were turned on simultaneously (as in the conventional arrangement of FIG. 3 ).
- each step change 122 in I S may produce ringing 124 as a result of effect of the parasitic inductance 90 and the parasitic capacitance 92 .
- the ringing 124 resulting from each step change 122 may also be comparatively small in magnitude.
- the ringing 124 from one step change 122 may be at least partly out of phase with the ringing from another step change 122 , and may tend to cancel the ringing at least partly.
- FIG. 8 generally shows the time axis in a very expanded sense, to illustrate the principles and the effect of the staggering of the timing of the current sources 58 .
- the current sources 58 to be turned on are all turned on at staggered, but closely adjacent times. In general, the times may be spread of a duration which may be less than the equivalent settling time that would be produced were all of the current sources 58 to be turned on simultaneously.
- Staggering the timing of plural current sources 58 may therefore produce the surprising result that the ringing may decay more quickly than the corresponding ringing that would be produced by a single step change were the plural current sources 58 to be controlled with the same timing.
- the quick decay may be surprising because of expectations that staggering the timing of the current sources 58 over a certain period may be counter intuitive to achieving a rapid change in the output.
- staggering the timing at which plural current sources 58 are turned on the same principles may be applied equally to turning off plural current sources 58 at or near the beginning of a sampling interval.
- An aim may be to stagger the timing to avoid a single large step change that may generate large amplitude ringing in the output.
- the control signals 120 may be the control signals 60 from the decoder 62 described previously. Alternatively, the control signals 120 may be distinct from the control signals 60 . Distinct control signals 60 and 120 may permit the timing of the switchable current sources 58 to be controlled independently of the addressing of the switchable current sources 58 for controlling whether each current source is to be on or off during the sampling interval. For example, the control signals 120 may be the timing signals 80 described previously.
- FIG. 9 illustrates a third embodiment showing an implementation of a portion of the circuit of FIG. 4, in more detail.
- a clock generating circuit 130 may generate one or more clock signals for controlling the timing of the DAC 56 .
- a first clock output 132 may control the timing of the decoder 62 for performing decoding operations at predetermined sampling intervals, and for presenting the control signals 60 a-b to the switchable current sources 58 a-b for determining whether each switchable current source 58 a-b will be on or off during the sampling interval.
- a second clock output 134 may provide the control signals 120 a-b (or 80 a-b ) for controlling the timing at which the control signals 60 a-b presented to the switchable current sources 58 a-b are acted upon at each switchable current source 58 a-b .
- the second clock output 134 may be fed through a staggered delay network in the form of a non-balanced clock tree path 136 to generate the respective control signals 120 a-b with staggered timings.
- FIG. 10 illustrates a fourth embodiment showing an implementation of a portion of the circuit of FIG. 4, in more detail.
- the decoder 62 may directly generate the control signals 60 a-b for addressing each switchable current source 58 a-b , and the timing control signals 120 / 80 a-b for controlling the timing of the switchable current sources 58 a-b.
- FIGS. 11 and 12 may illustrate simulated output responses of an output voltage measured at the internal or external resistor 88 , in response to a change in the digital input 64 .
- a first line 140 may represent the output in a first case in which a number (for example, eight) current sources 58 are turned on substantially simultaneously.
- the first line 140 may include a significant ringing component 142 .
- Levels 148 and 150 may represent two analog voltage levels corresponding to a difference of one bit of precision of the DAC 56 .
- the output 140 may settle to within one bit of precision (e.g., between the levels 148 and 150 ) at a time B.
- a second line 144 may represent the output in a second case in which plural current sources 58 (for example, eight current sources) are turned on progressively over a certain time period.
- the time period may be less than about 10 nanoseconds (ns), preferably less than about 5 ns, for example, about 2 ns.
- the second line 144 may include substantially less ringing than the first line 140 .
- the second line 144 may settle towards a stable value significantly more quickly than the first line 140 .
- the output 144 may settle to within one bit of precision (e.g., between the levels 148 and 150 ) at a time A earlier than time B.
- 11 and 12 may demonstrate how, in the second case, staggering the timing of plural current sources 58 may result in a reduced settling time compared to the first case in which the current sources 58 are switched simultaneously.
- the settling time to B may be about 10 ns, whereas the settling time to point A may be about only 5 ns, an improvement of about 50%.
- a third line 146 may represent a corresponding output in a third case in which a slew rate of a hypothetical single large current source (not shown) is slowed to provide a switching time of about 2 ns (similar to the switching time of the plural current sources 58 in the second case).
- the third line 146 may be very close to the second line 144 .
- staggering the timing of plural current sources 58 may have an effect similar to that of slowing a slew rate of a single current source. The result may be less of an instantaneous step change in the output, and consequently less ringing in the output.
- the various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0).
- the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation.
- inverters may be added to change a particular polarity of the signals.
- the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
Claims (25)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/219,638 US6683551B1 (en) | 2002-08-15 | 2002-08-15 | Digital-to-analog converter and method of operation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/219,638 US6683551B1 (en) | 2002-08-15 | 2002-08-15 | Digital-to-analog converter and method of operation |
Publications (1)
Publication Number | Publication Date |
---|---|
US6683551B1 true US6683551B1 (en) | 2004-01-27 |
Family
ID=30115270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/219,638 Expired - Fee Related US6683551B1 (en) | 2002-08-15 | 2002-08-15 | Digital-to-analog converter and method of operation |
Country Status (1)
Country | Link |
---|---|
US (1) | US6683551B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180287599A1 (en) * | 2014-11-12 | 2018-10-04 | Sony Semiconductor Solutions Corporation | Controller, control method, ad converter, and ad conversion method |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4393370A (en) * | 1980-04-30 | 1983-07-12 | Nippon Electric Co., Ltd. | Digital to analog converter using matrix of current sources |
US4843390A (en) * | 1988-02-24 | 1989-06-27 | Motorola, Inc. | Oversampled A/D converter having digital error correction |
US5027120A (en) * | 1989-05-26 | 1991-06-25 | Gec-Marconi Limited | Delta-sigma converter with bandpass filter for noise reduction in receivers |
US5162799A (en) * | 1990-11-30 | 1992-11-10 | Kabushiki Kaisha Toshiba | A/d (analog-to-digital) converter |
US5392040A (en) * | 1992-02-24 | 1995-02-21 | Sanyo Electric Co., Ltd. | Bit compression circuit used for a delta sigma type digital-to-analog converter |
US5942999A (en) * | 1997-08-08 | 1999-08-24 | International Business Machines Corporation | Controllable integrated linear attenuator for a D/A converter |
US6157335A (en) * | 1998-01-30 | 2000-12-05 | Fujitus Limited | Voltage generating circuit |
US6590516B2 (en) * | 2001-05-30 | 2003-07-08 | Matsushita Electric Industrial Co., Ltd. | Current steering type D/A converter |
-
2002
- 2002-08-15 US US10/219,638 patent/US6683551B1/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4393370A (en) * | 1980-04-30 | 1983-07-12 | Nippon Electric Co., Ltd. | Digital to analog converter using matrix of current sources |
US4843390A (en) * | 1988-02-24 | 1989-06-27 | Motorola, Inc. | Oversampled A/D converter having digital error correction |
US5027120A (en) * | 1989-05-26 | 1991-06-25 | Gec-Marconi Limited | Delta-sigma converter with bandpass filter for noise reduction in receivers |
US5162799A (en) * | 1990-11-30 | 1992-11-10 | Kabushiki Kaisha Toshiba | A/d (analog-to-digital) converter |
US5392040A (en) * | 1992-02-24 | 1995-02-21 | Sanyo Electric Co., Ltd. | Bit compression circuit used for a delta sigma type digital-to-analog converter |
US5942999A (en) * | 1997-08-08 | 1999-08-24 | International Business Machines Corporation | Controllable integrated linear attenuator for a D/A converter |
US6157335A (en) * | 1998-01-30 | 2000-12-05 | Fujitus Limited | Voltage generating circuit |
US6590516B2 (en) * | 2001-05-30 | 2003-07-08 | Matsushita Electric Industrial Co., Ltd. | Current steering type D/A converter |
Non-Patent Citations (1)
Title |
---|
Dedic et al, Switching Circuitry, Mar. 6, 2003, Pub. No. US 2003/0043062A1. * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180287599A1 (en) * | 2014-11-12 | 2018-10-04 | Sony Semiconductor Solutions Corporation | Controller, control method, ad converter, and ad conversion method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100780758B1 (en) | Reducing jitter in mixed-signal integrated circuit devices | |
US7449936B2 (en) | Open-loop slew-rate controlled output driver | |
KR100228756B1 (en) | Gradual turn-on cmos driver | |
US5097149A (en) | Two stage push-pull output buffer circuit with control logic feedback for reducing crossing current, switching noise and the like | |
JP3076300B2 (en) | Output buffer circuit | |
US6525587B2 (en) | Semiconductor integrated circuit device including a clock synchronous type logical processing circuit | |
US6486719B2 (en) | Flip-flop circuits having digital-to-time conversion latches therein | |
US20030058023A1 (en) | Level shift circuit | |
WO1999059248A1 (en) | Cmos low-voltage comparator | |
US20040150438A1 (en) | Frequency multiplier capable of adjusting duty cycle of a clock and method used therein | |
US6154078A (en) | Semiconductor buffer circuit with a transition delay circuit | |
US7023254B2 (en) | Duty ratio corrector, and memory device having the same | |
US6317374B2 (en) | Method for operating a current sense amplifier | |
Kohno et al. | A 350-MS/s 3.3-V 8-bit CMOS D/A converter using a delayed driving scheme | |
US20230298656A1 (en) | Internal voltage generation circuit and semiconductor memory apparatus including the same | |
US6614278B2 (en) | Pulsed signal transition delay adjusting circuit | |
JPH01200819A (en) | Data output presetting circuit | |
US6683551B1 (en) | Digital-to-analog converter and method of operation | |
US5339078A (en) | Digital to analog converter switch circuit | |
US6118261A (en) | Slew rate control circuit | |
US6285228B1 (en) | Integrated circuit for generating a phase-shifted output clock signal from a clock signal | |
US8035433B2 (en) | Process insensitive delay line | |
US5180930A (en) | Method and apparatus for reducing the effects of feedback switch charge injection into a plurality of serially connected sample data comparators | |
JPH03162011A (en) | Current limit output driver | |
US5254890A (en) | Ground bouncing reducing circuit and method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: LSI LOGIC CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TESTER, DAVID;WILSON, TIMOTHY;REEL/FRAME:013206/0522 Effective date: 20020814 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031 Effective date: 20140506 |
|
AS | Assignment |
Owner name: LSI CORPORATION, CALIFORNIA Free format text: CHANGE OF NAME;ASSIGNOR:LSI LOGIC CORPORATION;REEL/FRAME:033102/0270 Effective date: 20070406 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI CORPORATION;REEL/FRAME:035390/0388 Effective date: 20140814 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
AS | Assignment |
Owner name: LSI CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20160127 |