EP0483642B1 - Circuit for electronic control systems with switch steps for acquisition and adaptation - Google Patents
Circuit for electronic control systems with switch steps for acquisition and adaptation Download PDFInfo
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- EP0483642B1 EP0483642B1 EP91117973A EP91117973A EP0483642B1 EP 0483642 B1 EP0483642 B1 EP 0483642B1 EP 91117973 A EP91117973 A EP 91117973A EP 91117973 A EP91117973 A EP 91117973A EP 0483642 B1 EP0483642 B1 EP 0483642B1
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- 238000004891 communication Methods 0.000 claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims abstract description 13
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
Definitions
- the invention describes a circuit arrangement with switching stages for detection and adaptation, as well as switching means for providing electrical input signals, which are offered to the control level with a floating reference to the input level, in that the input information and the control signals of the information transmission are transported to and from a microprocessor via optical coupling elements, one of which numerical expansion of the information inputs is achieved by upgrading the switching stages and switching means.
- peripheral assemblies so-called input interfaces, are used to supply and provide digital input signals from external control devices such as switches, buttons, relays and sensors to electronic control systems.
- the circuit arrangements are applied to a printed circuit board and bring the input signal to a processing level that can be used for the control logic.
- a typical circuit arrangement of an input / output card is published in the technical documentation of EAStorz GmbH + Co KG (document. Vers. 1.0, edition 09.89, author H.Muffler).
- the circuits have a filter circuit for suppression of interference signals for each input and a comparator for defining the switching level, which relates the input signal to a reference voltage.
- An optocoupler is used for each input to isolate the control level from the external environment. This measure is dependent on the component ago complex and uneconomical.
- the invention has for its object to provide a circuit arrangement for electronic control systems, which causes a galvanic separation of the control level from the control periphery, the component requirement always being the same regardless of the number of physical inputs.
- the circuit arrangement is designed as an input module which can be cascaded with one or more input modules, a communication module being required per cascade, regardless of the number of cascaded input modules, by the clock inputs, the reset inputs and the data outputs of the Input modules are connected to each other and are connected to the respective clock output, the reset output and the data input of the communication module and the cycle end output of the first input module with the cycle enable of the second Input module is connected and that the same procedure is followed for each additional input module, and that the end-of-cycle output of the last cascaded input module is connected to the end-of-cycle input of the communication module, the communication module transmitting the data stream from and the control signals for the input modules Opto-coupler transported to and from the microprocessor, and that the EM's contain a multiplexer, the task of which is to use the control signals to transmit the parallel input signals serially to the data output.
- the sub-claims 2 to 5 characterize useful and advantageous embodiments of the invention. It is particularly expedient according to claim 2 that one or more comparison elements are available for each input, which provide one or more input information at the inputs of a multiplexer with reference to one or more reference levels.
- a reset signal emanating from the microprocessor via an opto-coupler of the communication module causes control logic to start the information recognition of the multiplexer at a defined input input. It is also advantageous that the microprocessor generates an internal clock and places it on the clock input of the control logic via an optocoupler, and that the clock determines the course of the transmission cycle over time.
- FIG. 1 shows a schematic representation of an input module and the communication module using the invention Circuit arrangement.
- FIG. 2 shows the cascading of the first input module with a further input module for numerically expanding the inputs.
- FIG. 3 shows the functional flow diagram of a transmission cycle using the circuit arrangement according to the invention.
- the input module EM has eight inputs IN0 - IN7, each of which has digital input information. Comparative elements EV0 to EV7 and diagnostic elements DV0 to DV7 are assigned to each input. The output levels of the input and diagnostic elements are in parallel at the inputs 4 of the multiplexer 1.
- the multiplexer is aligned at the beginning of the transmission cycle by the reset signal RES of the microprocessor 10, so that the first digital input information to be transmitted is defined.
- the reset signal RES would set the pointer of the multiplexer to the output level of the input element EV0.
- the IN0 input would therefore be queried first.
- the pointer of the multiplexer 1 is cycled further with a clock generated by the microprocessor 10 and transmitted by the control logic 2 so that all 16 inputs 4 of the multiplexer 1 are sampled in succession.
- the control logic 2 takes over synchronization function for the entire transmission cycle.
- a serial data stream results at the output 11 of the multiplexer 1 and is supplied to a serial-parallel converter 3 via the galvanic isolating element - preferably an optocoupler. This converts the serial data stream back into, in this case, 16-bit-wide data word and makes this available to the microprocessor 10.
- To The signal transmission of the last output signal DV7 ends the first transmission cycle and the control logic 2 sends the signal DCQ to the microprocessor.
- the prerequisite for this is that no cascading of several input modules was intended. If this is the case, however, the DCQ signal of the EM input module is switched to the DCI input of the input module to be cascaded.
- FIG. 2 shows the cascading of the first input module with a further input module for the numerical expansion of the inputs.
- two input modules EM1 and EM2 are cascaded. Each input element has 8 inputs IN0-IN7 and IN8-IN15.
- the multiplexer of the input module EM1 first queries the signal state of the input IN0. This happens because the signal DC1 from the input module EM1 is at low potential and EM1 is thus released.
- the microprocessor With the falling edge of the clock CLK generated by the microprocessor 10, the microprocessor reads the bit offered to it via the data line DATA. This is followed by further clocking to input IN1 and reading in the corresponding bit.
- FIG. 3 shows the functional flow diagram of a transmission cycle using the circuit arrangement according to the invention.
- the information cycle is clarified once again using this functional flow diagram. Further explanations are unnecessary, since the functional flow diagram supplements the above description in a self-commenting manner.
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- Time-Division Multiplex Systems (AREA)
Abstract
Description
Die Erfindung beschreibt eine Schaltungsanordnung mit Schaltstufen zur Erfassung und Anpassung sowie Schaltmittel zur Bereitstellung elektrischer Eingangssignale, die der Steuerungsebene mit potentialfreiem Bezug zur Eingangsebene angeboten werden, indem die Eingangsinformationen und die Steuersignale der Informationsübertragung von und zu einem Mikroprozessor über optische Koppelelemente transportiert werden, wobei eine zahlenmäßige Erweiterung der Informationseingänge durch Aufrüstung der Schaltstufen und Schaltmittel erreicht wird.The invention describes a circuit arrangement with switching stages for detection and adaptation, as well as switching means for providing electrical input signals, which are offered to the control level with a floating reference to the input level, in that the input information and the control signals of the information transmission are transported to and from a microprocessor via optical coupling elements, one of which numerical expansion of the information inputs is achieved by upgrading the switching stages and switching means.
Nach dem Stand der Technik werden Peripheriebaugruppen, sogenannte Eingangsinterfaces, zur Zuführung und Bereitstellung digitaler Eingangssignale von systemexternen Befehlsgeräten wie beispielsweise Schalter, Taster, Relais und Sensoren an elektronische Steuerungssysteme benutzt.According to the prior art, peripheral assemblies, so-called input interfaces, are used to supply and provide digital input signals from external control devices such as switches, buttons, relays and sensors to electronic control systems.
Die Schaltungsanordnungen sind auf einer Leiterplatte aufgebracht und bringen das Eingangssignal auf ein für die Steuerungslogik verwendbares Verarbeitungsniveau. In der Technischen Dokumentation von E.A.Storz GmbH + Co KG (Dokument. Vers. 1.0, Ausgabe 09.89, Verfasser H.Muffler) ist eine typische Schaltungsanordnung einer Ein-/Ausgabekarte veröffentlicht. Die Schaltungen weisen zur Unterdrückung von Störsignalen für jeden Eingang eine Filterschaltung und zur Definierung des Schaltpegels einen Komparator auf, der das Eingangssignal auf eine Referenzspannung bezieht. Zur Potentialtrennung der Steuerungsebene von der externen Umgebung wird pro Eingang ein Optokoppler eingesetzt. Diese Maßnahme ist vom Bauteilbedarf her aufwendig und unwirtschaftlich.The circuit arrangements are applied to a printed circuit board and bring the input signal to a processing level that can be used for the control logic. A typical circuit arrangement of an input / output card is published in the technical documentation of EAStorz GmbH + Co KG (document. Vers. 1.0, edition 09.89, author H.Muffler). The circuits have a filter circuit for suppression of interference signals for each input and a comparator for defining the switching level, which relates the input signal to a reference voltage. An optocoupler is used for each input to isolate the control level from the external environment. This measure is dependent on the component ago complex and uneconomical.
In der DE-Z-: Design &Elektronik, H. 14, 5.Juli, 1988, Seiten 68, 69 wird eine galvanisch trennenden Datenerfassung beschrieben. Es wird dabei eine Schaltungsanordnung beschrieben, die elektrische Eingangssignale erfasst und bereitstellt und an das Steuerungssystem anpasst. Eine Erweiterung der Grundschaltung um acht Eingänge, benötigt jeweils einen zusätzlichen Opto-Koppler. Die Anzahl der Schaltmittel wächst mit steigender Anzahl der zu verarbeitenden Eingangssignale.DE-Z-: Design & Elektronik, H. 14, July 5, 1988, pages 68, 69 describes a galvanically isolating data acquisition. A circuit arrangement is described which detects and provides electrical input signals and adapts them to the control system. An expansion of the basic circuit by eight inputs requires an additional opto-coupler. The number of switching devices increases with an increasing number of input signals to be processed.
Aus der DE-A 35 32 661 ist eine Schaltungsanordnung bekannt, bei der die Signalanpassungsschaltung mit einer kompletten Schaltung für einen Kanal aufgebaut ist. Um z.B. eine Anordnung mit n Kanälen realisieren zu können, muß die o.g. Schaltung n fach aufgebaut werden.From DE-A 35 32 661 a circuit arrangement is known in which the signal matching circuit is constructed with a complete circuit for one channel. To e.g. To be able to implement an arrangement with n channels, the above Circuit n be built up.
Der Erfindung liegt die Aufgabe zugrunde, eine Schaltungsanordnung für elektronische Steuerungssysteme zu schaffen, die eine galvanischen Trennung der Steuerungsebene von der Steuerungsperipherie bewirkt, wobei der Bauteilebedarf unabhängig von der Anzahl der physikalischen Eingänge immer der gleiche bleibt.The invention has for its object to provide a circuit arrangement for electronic control systems, which causes a galvanic separation of the control level from the control periphery, the component requirement always being the same regardless of the number of physical inputs.
Erfindungsgemäß wird diese Aufgabe dadurch gelöst, daß die Schaltungsanordnung als Eingangsmodul ausgeführt ist, das mit einem oder mehreren Eingangsmoduln kaskadierbar ist wobei pro Kaskade, unabhängig von der Anzahl der kaskadierten Eingangsmoduln, ein Kommunikationsmodul erforderlich ist, indem die Takteingänge, die Rücksetzeingänge und die Datenausgänge der Eingangsmoduln jeweils miteinander verbunden sind und mit dem jeweiligen Taktausgang, dem Rücksetzausgang und dem Dateneingang des Kommunikationsmoduls verbunden sind und der Zyklus-Ende Ausgang des ersten Eingangsmoduls mit der Zyklusfreigabe des zweiten Eingangmoduls verbunden wird und daß bei jedem weiteren Eingangsmodul gleichermaßen verfahren wird, und daß der Zyklus-Ende-Ausgang des letzten kaskadierten Eingangsmoduls mit dem Zyklus-Ende-Eingang des Kommunikationsmoduls verbunden wird, wobei das Kommunikationsmodul den Datenstrom von und die Steuersignale für die Eingangsmoduln über Opto-Koppler zum und vom Mikroprozessor transportiert, und daß die EM's einen Multiplexer enthalten, dessen Aufgabe es ist, mit Hilfe der Steuersignale die parallelen Eingangssignale seriell auf den Datenausgang zu übertragen.According to the invention, this object is achieved in that the circuit arrangement is designed as an input module which can be cascaded with one or more input modules, a communication module being required per cascade, regardless of the number of cascaded input modules, by the clock inputs, the reset inputs and the data outputs of the Input modules are connected to each other and are connected to the respective clock output, the reset output and the data input of the communication module and the cycle end output of the first input module with the cycle enable of the second Input module is connected and that the same procedure is followed for each additional input module, and that the end-of-cycle output of the last cascaded input module is connected to the end-of-cycle input of the communication module, the communication module transmitting the data stream from and the control signals for the input modules Opto-coupler transported to and from the microprocessor, and that the EM's contain a multiplexer, the task of which is to use the control signals to transmit the parallel input signals serially to the data output.
Die Unteransprüche 2 bis 5 kennzeichnen zweckmäßige und vorteilhafte Ausgestaltungen der Erfindung.
Dabei ist es nach Anspruch 2 besonders zweckmäßig, daß ein oder mehrere Vergleichselemente für jeden Eingang zur Verfügung stehen, die mit Bezug auf ein oder mehrere Referenzpegel eine oder mehrere Eingangs informationen an den Eingängen eines Multiplexers bereitstellen. Nach Anspruch 3 veranlaßt ein vom Mikroprozessor ausgehendes Rücksetzsignal über ein Opto-Koppler des Kommunikationsmoduls eine Steuerlogik dazu, die Informationserkennung des Multiplexers an einem definierten Eingang der Eingänge zu starten. Von Vorteil ist es weiterhin, daß der Mikroprozessor einen internen Takt erzeugt und über ein Opto-Koppler auf den Takteingang der Steuerlogik legt, und daß der Takt den zeitlichen Verlauf des Übertragungszyklus bestimmt.The
It is particularly expedient according to
Nachfolgend wird die erfindungsgemäße Schaltungsanordnung anhand von Ausführungsbeispielen unter Bezugnahme auf die Zeichnung näher beschrieben.The circuit arrangement according to the invention is described in more detail below on the basis of exemplary embodiments with reference to the drawing.
Es zeigenShow it
Fig.1 eine schematische Darstellung eines Eingangsmoduls und des Kommunikationsmoduls unter Verwendung der erfindungsgemäßen Schaltungsanordnung.1 shows a schematic representation of an input module and the communication module using the invention Circuit arrangement.
Fig.2 die Kaskadierung des ersten Eingangmoduls mit einem weiteren Eingangsmodul zur zahlenmäßigen Erweiterung der Eingänge.2 shows the cascading of the first input module with a further input module for numerically expanding the inputs.
Fig.3 das Funktionsablaufdiagramm eines Übertragungszyklus unter Verwendung der erfindungsgemäßen Schaltungsanordnung.3 shows the functional flow diagram of a transmission cycle using the circuit arrangement according to the invention.
Die Fig.1 zeigt eine schematische Darstellung eines Eingangsmoduls und des Kommunikationsmoduls unter Verwendung der erfindungsgemäßen Schaltungsanordnung. In diesem Beispiel weist das Eingangsmodul EM acht Eingänge IN0 - IN7 auf, an denen je eine digitale Eingangsinformation ansteht. Jedem Eingang sind Vergleichselemente EV0 bis EV7 und Diagnoseelemente DV0 bis DV7 zugeordnet. Die Ausgangspegel der Eingangs- und Diagnoseelemente liegen parallel an den Eingängen 4 des Multiplexers 1. Der Multiplexers wird zu Beginn des Übertragungszyklus durch das Rücksetzsignal RES des Mikroprozessor 10 ausgerichtet, so das die erste zu übertragene digitale Eingangsinformation definiert wird. In diesem Beispiel würde das Rücksetzsignal RES den Zeiger des Multiplexers auf den Ausgangspegel des Eingangselementes EV0 setzen. Somit würde zuerst der Eingang IN0 abgefragt. Mit einem von dem Mikroprozessor 10 erzeugten und von der Steuerlogik 2 übermittelten Takt wird der Zeiger des Multiplexers 1 zyklisch weitergetaktet so daß nacheinander alle 16 Eingänge 4 des Multiplexers 1 abgetastet werden. Die Steuerlogik 2 übernimmt Synchronisationsfunktion für den gesamten Übertragungszyklus. Am Ausgang 11 des Multiplexers 1 ergibt sich ein serieller Datenstrom, der über das galvanische Trennelement - vorzugsweise ein Optokoppler - einem Seriell-Parallel-Wandler 3 zugeführt wird. Dieser wandelt den seriellen Datenstrom wieder in ein, in diesem Fall, 16-bit-breites Datenwort und stellt dies dem Mikroprozessor 10 zur Verfügung. Nach der Signalübertragung des letzten Ausgangssignals DV7 endet der erste Übertragungszyklus und die Steuerlogik 2 sendet das Signal DCQ zum Mikroprozessor. Der sendet das Rücksetzsignal RES, wodurch der Zeiger des Multiplexers wieder auf das Ausgangssignal von EV0 ausgerichtet wird. Voraussetzung hierfür ist, daß keine Kaskadierung mehrerer Eingangsmodule vorgesehen war. Ist dies aber der Fall, wird das Signal DCQ des Eingangsmoduls EM auf den Eingang DCI des zu kaskadierenden Eingangsmoduls geschaltet.1 shows a schematic representation of an input module and the communication module using the circuit arrangement according to the invention. In this example, the input module EM has eight inputs IN0 - IN7, each of which has digital input information. Comparative elements EV0 to EV7 and diagnostic elements DV0 to DV7 are assigned to each input. The output levels of the input and diagnostic elements are in parallel at the inputs 4 of the multiplexer 1. The multiplexer is aligned at the beginning of the transmission cycle by the reset signal RES of the
Die Fig.2 zeigt die Kaskadierung des ersten Eingangmoduls mit einem weiteren Eingangsmodul zur zahlenmäßigen Erweiterung der Eingänge. In dieser beispielhaften Anordnung sind zwei Eingangsmodule EM1 und EM2 kaskadiert. Jedes Eingangselement weist 8 Eingänge IN0-IN7 bzw. IN8-IN15 auf. Nachdem nun der Mikroprozessor 10 das Rücksetzsignal RES gesendet hat fragt der Multiplexer des Eingangsmoduls EM1 zunächst den Signalzustand des Einganges IN0 ab. Dies geschieht, weil das Signal DC1 von dem Eingangsmodul EM1 auf Low-Potential liegt und EM1 damit freigegeben wird. Mit der abfallenden Flanke des vom Mikroprozessor 10 erzeugten Taktes CLK liest der Mikroprozessor das ihm über die Datenleitung DATA angebotene Bit. Danach erfolgt die Weitertaktung auf den Eingang IN1 und das Einlesen des entsprechenden Bits. Dies wiederholt sich solange, bis das letzte Bit, nämlich von Eingang IN7, des Eingangsmoduls EM1 gelesen wurde. Mittels des Signals DCQ1 wird das Eingangsmodul freigegeben. Der Multiplexer von Eingangsmodul EM2 wurde genau wie EM1 mit dem Rücksetzsignal RES auf seinen ersten Eingang gesetzt. Der weitere Taktablauf setzt die Abfrage der Eingänge IN8-IN15 fort. Nach der letzten Bitabfrage von Eingang IN15 meldet DCQ2 das Ende des Übertragungszykluses. Dem Mikroprozessor 10 liegt nun ein komplettes Datenwort vor, das ihm mittels des Seriell-Parallel-Wandlers aus dem Kommunikationszyklus übergeben wurde. Mit dem nächsten Takt von CLK wird das Rücksetzsignal RES gesendet und das Eingangsmodul EM1 aktiviert und ein neuer Übertragungszyklus kann beginnen. Durch die Erfindung wird der Verbindungsaufbau und der Bauteilebedarf, wie aus Fig.1 und Fig.2 zu ersehen ist, wesentlich optimiert.2 shows the cascading of the first input module with a further input module for the numerical expansion of the inputs. In this exemplary arrangement, two input modules EM1 and EM2 are cascaded. Each input element has 8 inputs IN0-IN7 and IN8-IN15. Now that the
Die Fig.3 zeigt das Funktionsablaufdiagramm eines Übertragungszyklus unter Verwendung der erfindungsgemäßen Schaltungsanordnung. Anhand dieses Funktionsablaufdiagramms wird der Informationszyklus noch einmal verdeutlicht. Weitere Erläuterungen erübrigen sich dabei, da das Funktionsablaufdiagramm selbstkommentierend die vorgenannte Beschreibung ergänzt.3 shows the functional flow diagram of a transmission cycle using the circuit arrangement according to the invention. The information cycle is clarified once again using this functional flow diagram. Further explanations are unnecessary, since the functional flow diagram supplements the above description in a self-commenting manner.
Claims (5)
- Circuit arrangement allowing the connection of a (signal-) input level with a control level in electronic control systems, including switching stages for registration and adaptation, as well as means for switching allowing the provision of electrical input signals which are proposed to the control level with a reference to the input level that is free from potential in such a way that the input signals and the control signals of information transmission are transmitted to and from a microprocessor via optical coupling elements, while an extension in terms of the numbers of information inputs is achieved by means of additional switching stages and switching means, wherein the circuit arrangement is designed as an input module (EM) which can be connected in cascade with one or several input modules, while one communication module (KM) is required by cascade irrespectively of the number of input modules (EM1-EMn) connected in cascade and while the clock inputs (CLK1, CLK2), the reset inputs (RES1, RES2) and the data outputs (DATA1, DATA2) of the input modules (EM1, EM2) are connected each with one another in this communication module (KM) and with the respective clock output (CLKA), reset output (RESA) and data input (DATAI) of the communication module and while the cycle-end output (DCQ1) of the first input module is connected with the cycle release (DCI2) of the second input module, and wherein the same procedure is adopted for any additional input module, and wherein the cycle-end output (DCQ2) of the last input module switched in cascade is connected with the cycle-end input (DCQI) of the communication module (KM), while the communication module (KM) carries the data flow (DATA) and the control signals (DCQ, RES, CLK) for the input modules to the microprocessor and away from it using opto-couplers (OK1, OK2, OK3, OK4), and wherein the input modules include a multiplexer which has the function of transmitting the parallel input signals in a serial way to the data output (DATA1, DATA2), using the control signals.
- Circuit arrangement as claimed in claim 1, wherein one or several comparison elements (EV0 - EV7, DV0 - DV7) are available for every input (IN 1 - IN 7) and provide one or several input information elements at the inputs (4) of a multiplexer (1), referring to one or more reference levels (REF 1, REF 2).
- Circuit arrangement as claimed in any claim 1 or 2, wherein a reset signal (RES) given by a microprocessor (10) via the opto-coupler (OK3) of the communication module (KM) determines a control logic (2) to start the information recognition of the multiplexer (1) at a defined input of inputs (4).
- Circuit arrangement as claimed in any claim 1 through 3, wherein the microprocessor (10) generates an internal clock pulse and feeds it into the clock input (CLK) of the control logic (2) via opto-coupler (OK4) and wherein the clock determines the timing of the transmission cycle (fig. 3).
- Circuit arrangement as claimed in any claim 1 through 4, wherein the end of a transmission cycle (fig. 3) is fed to the microprocessor via opto-coupler (OK2) and by means of a cycle-end signal (DCQ) transmitted by the control logic (2).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4034373A DE4034373C1 (en) | 1990-10-29 | 1990-10-29 | |
| DE4034373 | 1990-10-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0483642A1 EP0483642A1 (en) | 1992-05-06 |
| EP0483642B1 true EP0483642B1 (en) | 1996-03-13 |
Family
ID=6417262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP91117973A Expired - Lifetime EP0483642B1 (en) | 1990-10-29 | 1991-10-22 | Circuit for electronic control systems with switch steps for acquisition and adaptation |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0483642B1 (en) |
| AT (1) | ATE135484T1 (en) |
| DE (1) | DE4034373C1 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3532661A1 (en) * | 1985-09-13 | 1987-03-26 | Wilfried Saenger & Co Ing Buer | Signal matching circuit |
| DD264532A1 (en) * | 1987-10-19 | 1989-02-01 | Senftenberg Braunkohle | CIRCUIT ARRANGEMENT FOR CYCLIC METERING SWITCHING FOR ANALOG INPUT MODULES |
| DE3905735A1 (en) * | 1989-02-24 | 1990-08-30 | Pierburg Gmbh | Method for evaluating an input signal |
-
1990
- 1990-10-29 DE DE4034373A patent/DE4034373C1/de not_active Expired - Lifetime
-
1991
- 1991-10-22 EP EP91117973A patent/EP0483642B1/en not_active Expired - Lifetime
- 1991-10-22 AT AT91117973T patent/ATE135484T1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| DE4034373C1 (en) | 1992-05-27 |
| ATE135484T1 (en) | 1996-03-15 |
| EP0483642A1 (en) | 1992-05-06 |
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