EP0477100B1 - Circuit échantillonneur-bloqueur pour écran d'affichage à cristal liquide - Google Patents

Circuit échantillonneur-bloqueur pour écran d'affichage à cristal liquide Download PDF

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Publication number
EP0477100B1
EP0477100B1 EP91402495A EP91402495A EP0477100B1 EP 0477100 B1 EP0477100 B1 EP 0477100B1 EP 91402495 A EP91402495 A EP 91402495A EP 91402495 A EP91402495 A EP 91402495A EP 0477100 B1 EP0477100 B1 EP 0477100B1
Authority
EP
European Patent Office
Prior art keywords
capacitor
sampling
sample
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP91402495A
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German (de)
English (en)
French (fr)
Other versions
EP0477100A1 (fr
Inventor
Patrice Senn
Alan Lelah
Gilbert Martel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
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Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Publication of EP0477100A1 publication Critical patent/EP0477100A1/fr
Application granted granted Critical
Publication of EP0477100B1 publication Critical patent/EP0477100B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation

Definitions

  • the present invention relates to a sample-and-hold circuit for a liquid crystal display screen.
  • a liquid crystal display screen generally takes the form illustrated in FIG. 1.
  • the screen proper ECR consists of rows L and addressing columns C, of a matrix of pixels P, each connected to a TFT transistor whose state is controlled by the line L and the associated column C.
  • Such a screen is controlled by a line control circuit CCL, which sequentially applies an addressing voltage to the lines (for example a few volts) and by a column control circuit CCC, which applies voltages reflecting all the columns. the light intensity of the points to be displayed on the addressed line. The overall image is thus displayed line by line.
  • a line control circuit CCL which sequentially applies an addressing voltage to the lines (for example a few volts) and by a column control circuit CCC, which applies voltages reflecting all the columns. the light intensity of the points to be displayed on the addressed line.
  • CCC column control circuit
  • the column control circuit CCC receives a video signal SV delivered by a video circuit CV.
  • This signal generally consists of three components corresponding to the three primary components of a color image.
  • the circuit CCC includes 162 elementary column control circuits, arranged in parallel, and 162 outputs connected to the different columns.
  • Each elementary column control circuit (also called “column driver” in the technical literature) comprises a sample-and-hold circuit, the function of which is to sample the video signal at a determined time. corresponding to the column to be ordered and to maintain this sample on the column for the entire duration of addressing a row ("sample-and-hold" function in English terminology).
  • the present invention relates to such a sample-and-hold circuit.
  • sampler-blocker circuits of the prior art all have drawbacks.
  • the circuit marketed by the company HITACHI under the reference HD 66300T for example, use is made of four sampler-blockers per column, working alternately.
  • the circuit thus contains 480 sample-and-hold circuits for a screen of 120 columns.
  • the power consumption is therefore very large.
  • it is not possible to correct the offset voltage.
  • EP-A-0 381 429 and GB-2 146 479 disclose display screen control circuits comprising a first sampling stage consisting of a sampling capacitor and a second stage comprising a sampling capacitor maintenance.
  • a first capacitor (sampling) with a much larger capacity than that of the second (holding) is required. The charging time of the first capacitor is thereby increased.
  • the output voltage is linked to the input voltage by the ratio C1 / C1 + C2 (where C1 and C2 are the capacitances of the first and second capacitors), at best, is the output voltage equal at the input voltage. Furthermore, the large value of the first capacitor leads to excessive congestion and seriously limits the possibilities of integration of the circuit. Finally, the load impedance of the video amplifiers is considerably increased.
  • the object of the present invention is to remedy these drawbacks. To this end, it offers a low-consumption sample-and-hold circuit (less than 50 ⁇ A at rest), with a low charge time (the circuit is capable of charging an external capacity of 150pF per 6V in 2 ⁇ s) and its output dynamics is close to the difference in bias voltages (V DD -V SS ) (in reality slightly lower than this value, i.e. approximately V DD -V SS -0.3V). Finally, by adding a simple capacitor, it is possible to easily correct the offset voltage.
  • an offset correction capacitor is associated with the sampling capacitor to correct the offset produced by the amplifier located downstream. This capacitor is put into service during the time of transfer of the sample in the amplifier.
  • FIG 2 we see a sample-and-hold circuit CEB with a general input E and a general output S.
  • the input E is connected to a video bus BV connected to a video circuit CV.
  • Output S is connected to a column C.
  • CEB circuits There are as many CEB circuits as there are columns for a global control circuit.
  • the video circuit CV is not part of the invention. It suffices to indicate briefly that it comprises a video input 20, capacitors 22, 24, a switch 26 for "clamping” (leveling), controlled by a CCL signal, a transfer switch 28, controlled by a signal. transfer device TRD, an amplifier 30 for shaping and a framing circuit 32.
  • the circuit may also include, but not necessarily, a fourth electronic output switch T4 connected to the output s of the amplifier A and controlled by a TRS signal.
  • a general control circuit CC delivers control signals ECH, TRD, TRS, RESET for the various switches of the sample and hold units.
  • this circuit can be better understood in the light of the timing diagram of FIG. 3.
  • the video signal V two successive lines Ln-1 and Ln are illustrated, of rank n-1 and n
  • the second line shows the ECH sampling signal (one pulse corresponds to a sample-and-hold circuit, the others to the other circuits of the screen);
  • the third line shows the reset signal RESET;
  • the transfer signal TRD is shown on the fourth line and the transfer signal TRS on the last.
  • the sampling signal ECH acts first on the first switches T1, T′1 and causes the charging of the first sampling capacitor Ce.
  • the transfer signal TRS is at the high level and acts on the fourth output switch T4 and allows the voltage previously blocked in the storage capacitor Cs of the amplifier A to be transferred to the general output S.
  • the reset signal RESET acts on the second switch T2 to reset the voltage blocked in the storage capacitor Cs of amplifier A, while the signal TRS is set to zero to decouple the output of the amplifier A of the general output S.
  • the signal TRD acting on the third switches T3, T′3 causes the transfer of the sampled voltage in the first capacitor sampling point Ce to amplifier A and its storage capacitor Cs.
  • the circuit also comprises an additional capacitor Cc which allows an offset correction.
  • This capacitor has an armature connected to the input E through a fifth electronic switch T5 controlled by the transfer signal TRD and at a point brought to the average voltage of the bias voltages Vpm through a sixth electronic switch T6.
  • the voltage Vpm represents the average between the two extreme polarization voltages V SS and V DD .
  • the correction capacitor Cc has another armature connected to the sampling capacitor Ce.
  • Switch 28 and its transfer signal TRD are used for offset compensation (at least in the production of the video part with "clamping" system).
  • the offset compensation concerns the offset of the video channel. With the device of the switch 28, this offset is introduced into the video buses at the same time as the samples are transferred to the output of the control circuits (during TRD). The transfer is therefore done by two paths: by the capacitor C c , which transfers the inverse of the offset to C s , and also by C e which transfers the sample of the signal, uncompensated in offset, so -inverted towards C s .
  • the output result is the sampled value with offset compensation.
  • FIG. 4 illustrates the mounting of a plurality of sample-and-hold units conforming to that which has just been described, in a circuit for controlling the columns of a display screen with 162 columns.
  • the global circuit CCC includes 162 sample-and-hold circuits CEB1, CEB2, ..., CEB162 with 162 output pads S1, S2, ..., S162 connected to the 162 columns, C1, C2, ..., C162.
  • a video circuit CV supplies three video buses BV1, BV2, BV3 corresponding to the three primary red, green, blue.
  • a shift register R DEC with 162 cells delivers 162 sampling signals ECH for the 162 sample-and-hold circuits CEB1, ..., CEB162.
  • a polarization source POL supplies the video circuit CV and the amplifiers A of the sample and hold units.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
EP91402495A 1990-09-21 1991-09-19 Circuit échantillonneur-bloqueur pour écran d'affichage à cristal liquide Expired - Lifetime EP0477100B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9011682 1990-09-21
FR9011682A FR2667188A1 (fr) 1990-09-21 1990-09-21 Circuit echantillonneur-bloqueur pour ecran d'affichage a cristal liquide.

Publications (2)

Publication Number Publication Date
EP0477100A1 EP0477100A1 (fr) 1992-03-25
EP0477100B1 true EP0477100B1 (fr) 1994-11-30

Family

ID=9400531

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91402495A Expired - Lifetime EP0477100B1 (fr) 1990-09-21 1991-09-19 Circuit échantillonneur-bloqueur pour écran d'affichage à cristal liquide

Country Status (5)

Country Link
US (1) US5252956A (enrdf_load_stackoverflow)
EP (1) EP0477100B1 (enrdf_load_stackoverflow)
JP (1) JPH05150217A (enrdf_load_stackoverflow)
DE (1) DE69105432T2 (enrdf_load_stackoverflow)
FR (1) FR2667188A1 (enrdf_load_stackoverflow)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5495192A (en) * 1992-02-10 1996-02-27 Yozan Inc. Sample hold circuit
JP3067059B2 (ja) * 1992-07-09 2000-07-17 シャープ株式会社 サンプルホールド回路
FR2698202B1 (fr) * 1992-11-19 1995-02-03 Alan Lelah Circuit de commande des colonnes d'un écran d'affichage.
KR0161361B1 (ko) * 1993-04-28 1999-03-20 사또 후미오 구동 회로 장치
JP3102666B2 (ja) * 1993-06-28 2000-10-23 シャープ株式会社 画像表示装置
FR2734075B1 (fr) * 1995-05-11 1997-07-18 Matra Mhs Amelioration des performances d'un dispositif d'affichage a cristaux liquides par application d'un niveau de reference directement dans les circuits d'attaque
JPH11509937A (ja) * 1995-07-28 1999-08-31 リットン システムズ カナダ リミテッド アクティブマトリックス液晶ディスプレイ用集積化アナログソースドライバ
US5798747A (en) * 1995-11-17 1998-08-25 National Semiconductor Corporation Methods and apparatuses for high-speed video sample and hold amplification for analog flat panel display
JP3171091B2 (ja) * 1996-02-14 2001-05-28 日本電気株式会社 液晶画像信号制御方法及び制御回路
KR100192429B1 (ko) * 1996-10-24 1999-06-15 구본준 액정표시소자의 구동장치
FR2801750B1 (fr) * 1999-11-30 2001-12-28 Thomson Lcd Procede de compensation des perturbations dues au demultiplexage d'un signal analogique dans un afficheur matriciel
CN113314084B (zh) * 2021-05-31 2022-03-22 惠科股份有限公司 一种显示面板的驱动方法、驱动装置及显示面板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2458117A1 (fr) * 1979-05-28 1980-12-26 Suwa Seikosha Kk Systeme d'affichage a cristaux liquides et circuit d'attaque en courant alternatif pour ce systeme
JPS6059389A (ja) * 1983-09-12 1985-04-05 シャープ株式会社 液晶表示装置の駆動回路
US4578646A (en) * 1984-02-08 1986-03-25 Hitachi, Ltd Integral-type small signal input circuit
JPS60257683A (ja) * 1984-06-01 1985-12-19 Sharp Corp 液晶表示装置の駆動回路
JPS6132093A (ja) * 1984-07-23 1986-02-14 シャープ株式会社 液晶表示装置の駆動回路
US4978872A (en) * 1984-12-17 1990-12-18 Hughes Aircraft Company Integrating capactively coupled transimpedance amplifier
JPH0654961B2 (ja) * 1985-04-10 1994-07-20 松下電器産業株式会社 サンプルホ−ルド回路
DE3641556A1 (de) * 1985-12-09 1987-06-11 Sharp Kk Steuerschaltung fuer eine fluessigkristallanzeige
US4763088A (en) * 1986-04-30 1988-08-09 Silicon Systems, Inc. Switching scheme for switched capacitor filters
JPH0750389B2 (ja) * 1987-06-04 1995-05-31 セイコーエプソン株式会社 液晶パネルの駆動回路
US4781437A (en) * 1987-12-21 1988-11-01 Hughes Aircraft Company Display line driver with automatic uniformity compensation
US5111195A (en) * 1989-01-31 1992-05-05 Sharp Kabushiki Kaisha Driving circuit for a matrix type display device

Also Published As

Publication number Publication date
EP0477100A1 (fr) 1992-03-25
FR2667188B1 (enrdf_load_stackoverflow) 1994-12-23
JPH05150217A (ja) 1993-06-18
US5252956A (en) 1993-10-12
DE69105432T2 (de) 1995-06-14
FR2667188A1 (fr) 1992-03-27
DE69105432D1 (de) 1995-01-12

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