EP0473789A1 - Steuergerät für eine bitkartierte anzeige - Google Patents
Steuergerät für eine bitkartierte anzeige Download PDFInfo
- Publication number
- EP0473789A1 EP0473789A1 EP19910904650 EP91904650A EP0473789A1 EP 0473789 A1 EP0473789 A1 EP 0473789A1 EP 19910904650 EP19910904650 EP 19910904650 EP 91904650 A EP91904650 A EP 91904650A EP 0473789 A1 EP0473789 A1 EP 0473789A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- video memory
- address
- addresses
- data
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
Definitions
- the present invention relates to a bit map display controlling apparatus used with a word processor, personal computer, data terminal equipment or the like.
- addresses of a video memory are assigned sequentially in the order of raster scanning, and a display controller accesses the video memory in the order of addresses to perform a refresh display of the contents of the video memory.
- Fig. 4 shows the structure of a conventional bit map display controlling apparatus.
- a display controller 1 generates addresses a2 for writing to the video memory 2 sequentially in the order of raster scanning and supplies them to a video memory 2 storing the raster scan type display contents.
- the video memory 2 outputs display data d2 in the order of raster scanning.
- CPU 3 accesses, when necessary, the video memory 2 fixedly assigned with the addresses in the order of raster scanning, and changes the data in the video memory 2 to a data d1.
- Fig. 5 shows an example of an address map of the video memory 2 of a conventional bit map display controlling apparatus. This example of Fig. 5 is applied to a bit map display controlling apparatus wherein 1024 dots are scanned in the horizontal direction, and 512 dots are repeatedly scanned (having 512 scan lines) in the vertical direction. Byte addresses are sequentially assigned in the horizontal direction on the 8 dots (bits) unit basis. Numbers in Fig. 5 represent the byte addresses.
- the numbers of dots in the horizontal and vertical directions may vary depending upon a bit map display controlling apparatus.
- the address assignment of a conventional bit map display controlling apparatus is in the order of raster scanning such as shown in Fig. 5.
- the above-described conventional bit map display controlling apparatus is, however, associated with a problem that in writing data into the video memory 2 under control of CPU 3, an address translation calculation to be executed by a program may sometimes become complicated depending upon the contents of the data, because the addresses of the video memory 2 are fixedly assigned, thereby increasing the processing time and the quantity of program.
- the present invention solves such conventional problems and aims at providing a bit map display controlling apparatus wherein in writing data in a video memory by using a program of CPU, the addresses generated by a display controller sequentially in the order of raster scanning can be translated as desired depending upon the contents of the data so as to satisfy the program, thereby reducing the load on the program of CPU.
- an address translator for reducing the load of a program of CPU. There is written in the address translator a translation data for an address from CPU for accessing a video memory, and the translation data is outputted to the video memory as a translated address of the address from CPU.
- the load of program of CPU can be reduced.
- an address from CPU for accessing the video memory is translated by the address translator, and thereafter the video memory is accessed using the translated address. Therefore, in writing data in a video memory using a program of CPU, the video memory address can be accessed most properly for the program of CPU in accordance with the contents of the data to be written.
- Fig. 1 is a block diagram showing a bit map display controlling apparatus according to an embodiment of the present invention
- Fig. 2 is a diagram illustrating the correspondence between addresses and their contents in an address memory of the address translator of the apparatus shown in Fig. 1
- Fig. 3(a) is a diagram showing addresses and their contents read from a character generator of the apparatus shown in Fig. 1
- Fig. 3(b) is a diagram showing addresses of a video memory corresponding to the addresses shown in Fig. 3(a), and their contents
- Fig. 4 is a block diagram showing a conventional bit map display controlling apparatus
- Fig. 5 illustrates an address assignment of a video memory in a conventional bit map display controlling apparatus.
- Fig. 1 shows the structure of an embodiment of the present invention.
- reference numeral 1 represents a display controller which generates an address signal a2 sequentially in the order of raster scanning for accessing a video memory 2 storing the raster scan type display contents, and supplies it to the video memory 2 to access it.
- d2 represents a display data outputted from the video memory 2 when the display controller 1 accesses the video memory 2.
- Reference numeral 3 represents a stored-program type CPU which outputs a data d1 to be written in the video memory 2.
- Reference numeral 4 represents an address translator which is constructed of a random access memory.
- CPU 3 writes in advance an address translation data d3 for an address a1 to be outputted from CPU 3 for accessing the video memory 2.
- the address translator 4 outputs an address a3 as a translated address of the address a1 for accessing the video memory 2.
- Fig. 2 shows the contents of the address translation data d3 outputted from CPU 3 and written in the address translator 4 for addresses "0" to "7" designated by the address a1 outputted from CPU 3.
- Fig. 3(a) shows the contents of a character "A" to be read from a character generator read-only memory (not shown) at addresses from “0" to "7".
- Fig. 3(b) shows the read-out contents of Fig. 3(a) written in the video memory 2 at addresses from "0" to 894 at the interval of every 128-th addresses.
- the addresses from "0" to "894" shown in Fig. 3(b) correspond to the addresses of the video memory 2 assigned with byte addresses on the 8 bits unit basis in the horizontal direction shown in Fig. 5.
- the display controller 1 generates the address a2 in the order of caster scanning for accessing the video memory 2.
- the video memory 2 outputs the display data d2 in the order of caster scanning.
- CPU 3 changes the data assigned fixedly and in the order of raster scanning to the video memory 2, to the data d1.
- the above operation is the same as that of a conventional apparatus.
- the address translator 4 In writing data in the video memory 2 using a program of CPU 3, the address translator 4 translates the address al accessed by CPU 3 to the address a3 such that the address generated by the display controller 1 in the order of raster scanning can be translated as desired in accordance with the contents of the data to be written so as to satisfy the program of CPU 3.
- CPU 3 writes in advance the address translation data d3.
- This pre-process allows the following operation.
- CPU 3 reads a character (e.g., "A") composed of 8 bits in the horizontal direction and 8 bits in the vertical direction as shown in Fig. 3(a) from a character generator memory at addresses “0" to "7”, and writes it in the video memory 2 at addresses from "0" to "894" at the interval of every "128-th” addresses as shown in Fig. 3(b).
- the address translator 4 outputs the address a3 to the video memory 2 so that the video memory 2 can be accesses by using consecutive addresses for the addresses from "0" to "7".
- CPU 3 reads the character generator read-only memory at addresses from “0" to “7”, and writes the data d1 in the video memory 2 at the addresses from “0" to "894" at the interval of every "128-th” addresses.
- the consecutive 8 bytes are accessed, and also in writing into the video memory 2, the consecutive addresses for the addresses from "0" to "7” can be accessed.
- the address translator 4 constructed of a random access memory may be written such that address translation data is provided for the character display area as in the above embodiment, and address translation data is not provided for the image display area.
- translated addresses corresponding to the positions of characters to be displayed can be properly determined as desired in accordance with the sizes of characters and stored in the address translator 4.
- the pattern or image can be copied not by accessing the video memory 2 but by accessing only the address translator 4 constructed of a random access memory.
- n lines of 8 x 8 dot characters are displayed on the upper area of a display screen, and a figure is displayed on the area under the upper area.
- such a preferable condition can be easily realized by properly writing the contents of the address translator 4 constructed of a random access memory.
- addresses those starting from 0 and following integer multiples of 128 such as explained with Fig. 2 are written in the address translator 4 constructed of a random access memory.
- the address translator 4 constructed of a random access memory for the display area other than the character display area, the same addresses for the video memory are written.
- the order of addresses of the video memory 2 can be changed as desired most properly for an image display program. Easy programming and high speed processing can be effectively realized for a bit map display controlling apparatus which displays freely a complicated combination of characters of desired sizes, figures, and graphics images.
- CPU in writing data in a video memory using a program of CPU, writes a translation data of an address from CPU for accessing the video memory, into an address translator.
- the address translator outputs a translated address of the address from CPU to the video memory.
- the address from CPU can be changed as desired so as to satisfy the program, thereby reducing the load of the CPU program.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Digital Computer Display Output (AREA)
- Controls And Circuits For Display Device (AREA)
- Memory System (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9044890A JPH03246596A (ja) | 1990-02-26 | 1990-02-26 | ビットマップディスプレイ制御装置 |
JP448/90 | 1990-02-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0473789A1 true EP0473789A1 (de) | 1992-03-11 |
Family
ID=12704080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19910904650 Withdrawn EP0473789A1 (de) | 1990-02-26 | 1991-02-26 | Steuergerät für eine bitkartierte anzeige |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0473789A1 (de) |
JP (1) | JPH03246596A (de) |
WO (1) | WO1991013428A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0568078A1 (de) * | 1992-04-30 | 1993-11-03 | Toshiba America Information Systems, Inc. | Aussenschnittstelle für einen hochleistungsfähigen Graphikadapter, die die graphische Kompatibilität gewährt |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS607474A (ja) * | 1983-06-27 | 1985-01-16 | 株式会社東芝 | Crt表示装置 |
JPS60191349A (ja) * | 1984-03-13 | 1985-09-28 | Toshiba Audio Video Eng Corp | 表示メモリのアドレス制御回路 |
JPS638690A (ja) * | 1986-06-30 | 1988-01-14 | ブラザー工業株式会社 | Crt表示回路 |
-
1990
- 1990-02-26 JP JP9044890A patent/JPH03246596A/ja active Pending
-
1991
- 1991-02-26 EP EP19910904650 patent/EP0473789A1/de not_active Withdrawn
- 1991-02-26 WO PCT/JP1991/000246 patent/WO1991013428A1/ja not_active Application Discontinuation
Non-Patent Citations (1)
Title |
---|
See references of WO9113428A1 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0568078A1 (de) * | 1992-04-30 | 1993-11-03 | Toshiba America Information Systems, Inc. | Aussenschnittstelle für einen hochleistungsfähigen Graphikadapter, die die graphische Kompatibilität gewährt |
US5438663A (en) * | 1992-04-30 | 1995-08-01 | Toshiba America Information Systems | External interface for a high performance graphics adapter allowing for graphics compatibility |
Also Published As
Publication number | Publication date |
---|---|
WO1991013428A1 (en) | 1991-09-05 |
JPH03246596A (ja) | 1991-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4682161A (en) | Variable size character display without loss of obscured character positions | |
US5940087A (en) | Graphic processing apparatus and method | |
EP0422298A1 (de) | Anzeigesystem | |
US5696947A (en) | Two dimensional frame buffer memory interface system and method of operation thereof | |
KR19980703654A (ko) | 종방향 배향의 디스플레이를 위하여 화상을 회전시키는 하드 웨어 | |
US4570161A (en) | Raster scan digital display system | |
US4566000A (en) | Image display apparatus and method having virtual cursor | |
EP0525986B1 (de) | Gerät mit schneller Kopierung zwischen Rasterpuffern in einem Anzeigesystem mit Doppel-Pufferspeichern | |
US5619721A (en) | Controlling font data memory access for display and non-display purposes using character content for access criteria | |
US5526128A (en) | Image producing apparatus with memory unit having an image memory area of changeable storage capacity | |
KR950020279A (ko) | 그래픽스 컴퓨터 | |
US5416499A (en) | Bit map display controlling apparatus | |
EP0473789A1 (de) | Steuergerät für eine bitkartierte anzeige | |
EP0245504A1 (de) | Bildbehandlung | |
JPH0562348B2 (de) | ||
EP0258825A2 (de) | Vorrichtung zur Anzeigesteuerung mit verbesserter Attribut-Funktion | |
JPS59143194A (ja) | 画像表示装置 | |
JPH06161420A (ja) | 文字信号発生装置 | |
JPS597115B2 (ja) | アドレス作成方法 | |
EP0420291B1 (de) | Anzeigesteuergerät | |
KR920002109Y1 (ko) | 고해상도 비디오장치 | |
JPH0570833B2 (de) | ||
JPS61137191A (ja) | スクロ−ル表示装置 | |
JPS6151316B2 (de) | ||
JPH0337025Y2 (de) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19911022 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
18W | Application withdrawn |
Withdrawal date: 19920928 |
|
R18W | Application withdrawn (corrected) |
Effective date: 19920925 |