WO1991013428A1

WO1991013428A1 - Bit map display controller

Info

Publication number: WO1991013428A1
Application number: PCT/JP1991/000246
Authority: WO
Inventors: Kenji Otsu
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 1990-02-26
Filing date: 1991-02-26
Publication date: 1991-09-05
Also published as: JPH03246596A; EP0473789A1

Abstract

A controller capable of changing arbitrarily the order of address of a video memory (2) in a bit map display. The controller is provided with an address translator which writes translation data for the address for making access from a CPU (3) to the video memory (2) in accordance with the write content of the address in the order of a luster scanning generated by a display controller (1) and outputs the data as the conversion address for the address from the CPU (3) to the video memory (2).

Description

Specification

Title of invention

Bitmap display controller

Technical field

The present invention relates to a bitmap display control device used for a word processor, a personal computer, a data terminal, and the like.

Background art

Conventionally, this type of bitmap display controller assigns video memory addresses in the order of raster scan, and the display controller accesses the video memory in this order. The video is refreshed according to the contents of the video memory.

The addresses seen from the central processing unit (CPU) are also as described above.

Fig. 4 shows the configuration of a conventional bitmap display control device. In Figure 4, the display co emissions collected by filtration over La 1, La is te liked address a ₂ of catcher down method for sequentially writing the Rasutasuki catcher on to Bideome mode Li 2 storing the display contents of the generated, The video memory ₂ outputs the display data d2 in this order.

Further, the CPU 3 accesses the data of the video memory 2 to which the address is fixedly assigned in the order of the raster scan with the address a if necessary, to the data d〗. Rewrite.

FIG. 5 is an example showing the address arrangement of the video memory 2 of the conventional bitmap display control device. The example in Fig. 5 shows a bitmap display that has 1024 dot scans (scanning) in the horizontal direction and 512 dot scanning in the vertical direction (it has 512 scanning lines). This is an example applied to a control device, in which byte addresses are sequentially assigned in units of 8 dots (8 bits) in the horizontal direction, and the numbers in Fig. 5 indicate the addresses. .

The number of dots in the horizontal and vertical directions is determined by the bitmap display control unit. Although the address varies depending on the location, the order of address allocation is as shown in Fig. 5, which is generally arranged in raster scan order as a conventional bitmap display controller.

However, in the above-mentioned conventional bitmap display control device, since the address of the video memory 2 is fixed, when writing data to the video memory 2 from the CPU 3, depending on the contents of the data, Computation for dress conversion may be complicated when performed by a program, and the processing time and the amount of programs may be increased.

For example, the program of CPU 3 uses the character “A” of 8 bits horizontally and 8 bits vertically as shown in Fig. 3 (a) as a character generator lead. When reading from address 0 to address 7 in the memory and writing data to the address 894 every 0 to 128 in the video memory shown in Fig. 3 (b), the character When reading from the memory only, continuous 8 bytes are accessed, but when writing to video memory, the address is not continuous, so every byte is read. Requires address addition by program.

The present invention solves such a conventional problem. When a CPU program writes data to video memory, a display controller is generated according to the contents of the data. It is an object of the present invention to provide an excellent bitmap display control device which can arbitrarily convert addresses in scan order according to a program and can reduce a load on a CPU program.

Disclosure of the invention

The present invention achieves the above object by accessing a video memory from a CPU according to a data content for writing an address in a raster scan order generated by a display controller to the video memory. An address conversion device is provided which writes conversion data for the address to be converted and outputs the converted data to the video memory as a conversion address for the address from the CPU. It is designed to reduce the load on the PU program. Therefore, according to the present invention, since the address for accessing the video memory from the CPU is converted by the address conversion device to access the video memory, the video memory is accessed by the CPU program. When data is written, it has the effect that the video memory address can be accessed most conveniently in the CPU program depending on the content of the data to be written.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a bit map display control device according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing correspondence of address memory contents in an address converter of the device. Fig. 3 (a) is an explanatory diagram showing the address read from the character generator and its contents, and Fig. 3 (b) is the address shown in Fig. 3 (a). An explanatory diagram showing the address and contents of the corresponding video memory, FIG. 4 is a block diagram of a conventional bit map display controller, and FIG. 5 is a video memory of the conventional bit map display controller. FIG. 5 is an explanatory view showing an address arrangement of a memory o

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows the configuration of one embodiment of the present invention. Oite in Figure 1, 1 generates § de-less signal a ₂ to A click Seth this Bideome mode Li 2 Bideome mode Li 2 La is te scans order of storing the display contents of Rasutasuki catcher down method It is a display controller.

d2 is display data output from the video memory 2 when the display controller 1 accesses the video memory 2.

Reference numeral 3 denotes a stored program type CPU which outputs data to be written to the video memory 2.

Reference numeral 4 denotes an address conversion device, which is composed of random access memory. This address conversion device 4 is an address converter output from CPU 3 when CPU 3 accesses video memory 2 in advance. Less & i advance by writing conversion add-less data d ₃ for the conversion § de a § De-less a ₃ when the add-less a add-less converter 4 to the to § click cell scan the Bideome mode Li 2 Output to access video memory 2.

Fig. 2 shows the address output from the CPU 3 by the address converter 4! Based of the designated shows the contents of writing the conversion add-less data d ₃ to be output from the CPU 3 to the "7" from address "0" address.

Fig. 3 (a) shows a character generator lead (not shown) for reading the character "A" from address "0" to address "7" in the memory. As shown in Fig. 3 (b), the contents read out from Fig. 3 (a) are written to the address 894 at every 128th address from "0" in video memory 2, as shown in Fig. 3 (b). Is shown.

Addresses “0” to “894” in Fig. 3 (b) correspond to the addresses of video memory 2 shown in Fig. 5, where byte addresses are allocated in 8-bit units in the horizontal direction. are doing.

Next, the operation of the above embodiment will be described. In the above embodiment, the display controller 1 generates an address a2 for accessing the video memory ₂ in the order of the raster scan, and the video memory ₂ generates the address a2. The display data d ₂ is output in the order of the buttons.

Further, the CPU 3 transfers the data of the video memory 2 fixedly assigned in the order of the raster scan to the data d! To be rewritten. The operation described above is the same as the operation of the conventional example shown in FIG.

Next, the operation of the address conversion device 4 will be described. When data is written to the video memory 2 by the program of the CPU 3, the address of the raster scan order generated by the display controller 1 depending on the content of the data to be written is processed by the CPU 3 program. Ni Let 's that can be converted to any in the g convenience, is § de-less converter 4 to convert § de-less for CPU 3 Karaa click Seth to add-less a _3.

In this case, the CPU 3 writes the conversion address data d in advance. Get in.

At the time of this writing, as shown in FIG. 2, the address is written to the address conversion device 4 from address “0” to address “7” so as to correspond to the address of the video memory 2. deep.

By performing such pre-processing, the CPU 3 characterizes 8-bit wide and 8-bit vertical characters (for example, “A”) as shown in FIG. 3 (a). Reads from address 0 to address 7 of the generator memory, and positions from address 0 to address 894 every 128 addresses in video memory 2 as shown in Fig. 3 (b). to come and write to, the add-less a ₃ to be output to Bideome mode Li 2 from add-less conversion equipment 4, the video Note Li 2, successive "0" from the address to "7" address § You can access the dress.

That is, the CPU 2 reads the character generator read-only memory from address "0" to address "7", and reads out the address "0" to address 128 of video memory 2 When data d, is written to the location at address 894, reading of this character generator read-only memory accesses a series of 8 bytes. Also, when writing to video memory 2, a continuous address from address "0" to address "7" can be accessed.

Therefore, in the present embodiment, for example, when characters and image data are to be largely divided into display areas and the simultaneous display is to be performed, the character portions are arranged in the same manner as in the above-described embodiment. The part can be written in the random access memory constituting the address conversion device 4 so that the arrangement is such that the address conversion is not performed.

Also, when simultaneously displaying characters having different character sizes, the address corresponding to the position where the character is displayed according to the size of each character is arbitrarily stored in the address conversion device 4. It can be conveniently converted.

Also, the same character pattern or image can be displayed in another position on the same display screen. Copying to the location is also possible only with the random access memory of the address converter 4 instead of the video memory 2. Next, the above embodiment will be further described as a concrete example close to an actual screen display example.

At the top of the display screen, an 8 x 8 dot character is displayed for n lines, and a screen is drawn underneath. (The address of video memory 2 is as shown in Fig. 5.)

In this case, for the CPU 3 program, it is preferable that the character pattern can be written in a character-by-character manner in a continuous address, and the graphic part can be written in the original video program. It is preferable that the address of the memory 2 be maintained (preferably, in general, it is easy to understand and to increase the access speed when constructing the program. It says:).

In the present invention, this favorable state can be easily realized by writing the contents of the above-mentioned random access memory of the address conversion device 4 conveniently.

In other words, regarding the address of the video memory 2 for the character display area for n lines, the contents of the random access memory of the address conversion device 4 are considered as an extension of FIG. Write an integer multiple of 128.

As for the address of the video memory 2 other than the character area, the contents of the random access memory of the address conversion device 4 described above are the same as those of the video memory.

As described above, according to the random access memory of the address conversion device 4, the present invention is most convenient for the screen display program, and the address of the video memory 2 can be obtained. The order can be changed freely, and easy programming and high-speed processing are realized for a bitmap display control device that can freely display characters of any size and graphics and images in a complex and free manner. It is effective for Industrial applicability

As is clear from the above embodiment, when writing data to the video memory by the CPU program, the present invention provides an address for the CPU to access the video memory. The conversion data is written in the address conversion device, the conversion address is output to the video memory from the address conversion device for this address, and the address is arbitrarily selected for the convenience of the CPU program. It can be converted and has the effect of reducing the load on the CPU program.

Claims

The scope of the claims

The data can be arbitrarily replaced by the stored program central processing unit, and video memory for storing the display contents of the raster scan system and a fixed amount of data synchronized with the above raster scan The display controller generates a signal and an address for accessing the video memory in order, and the central processing unit sends data to the video memory by a program of the central processing unit. When writing, an address conversion device is provided that converts the address in raster scan order arbitrarily according to the above program according to the content of the data and generates an address to access the video memory. Bitmap display controller.