EP0440691A1 - Circuits electriques affines - Google Patents

Circuits electriques affines

Info

Publication number
EP0440691A1
EP0440691A1 EP19890911825 EP89911825A EP0440691A1 EP 0440691 A1 EP0440691 A1 EP 0440691A1 EP 19890911825 EP19890911825 EP 19890911825 EP 89911825 A EP89911825 A EP 89911825A EP 0440691 A1 EP0440691 A1 EP 0440691A1
Authority
EP
European Patent Office
Prior art keywords
receptive
substrate
conductor pattern
mask
covering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19890911825
Other languages
German (de)
English (en)
Inventor
Peter Anthony Guest
Ian Arthur Betteridge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MORGAN MATERIALS TECHNOLOGY Ltd
Original Assignee
MORGAN MATERIALS TECHNOLOGY Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MORGAN MATERIALS TECHNOLOGY Ltd filed Critical MORGAN MATERIALS TECHNOLOGY Ltd
Publication of EP0440691A1 publication Critical patent/EP0440691A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0236—Plating catalyst as filler in insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/422—Plated through-holes or plated via connections characterised by electroless plating method; pretreatment therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal

Definitions

  • This invention relates to the manufacture of electrical circuits and is particularly, though not exclusively, applicable to the manufacture of flexible electrical circuits.
  • United Kingdom Patent Specification No. 1261578 discloses a method of producing a circuit board by the steps of:- i) using an insulating board of catalysed base material; ii) providing a non-catalysed layer on the insulating board, which layer will not retain metal when placed in an electroless metal depositing bath; iii) removing the non-catalysed layer from the base material over those areas which are to accommodate the metallic conductor; and iv) depositing copper on the exposed areas of the catalysed base material in an electroless deposition bath.
  • the means described for removing the non-catalysed layer include mechanical machining (e.g. milling or drilling) and, in an unexemplified statement, laser beams, UV radiators, hot bulbs, ultrasonic radiators, chemical etchants.
  • ultra-violet radiation is strongly absorbed by polymeric and glass materials and so does not penetrate such materials very far, this means that the ablative effect is limited to a thin skin on the surface of an exposed object (the thickness of this layer varies from material to material and with the UV flux but is typically 0.1 - 0.5 ⁇ m thick).
  • ultra-violet lasers do not affect copper or other metal layers on polymeric substrates unless the metal layer is very thin (e.g. less than 3 ⁇ m).
  • a critical radiation intensity must be exceeded for the material to be processed. If the radiation intensity is below this critical intensity the energy is deposited as heat. This allows the use of masks, having a high critical intensity (such as most metals), to give imagewise processing of materials having a lower critical intensity. This is in contradistinction to the conventional use of e.g. C0 2 lasers which x write' using a focused spot. This imagewise processing allows short processing times.
  • scanning of a line of ultra-violet laser radiation is advantageous in that it allows lasers of low UV flux to be used without the problems of overlap or discontinuity provided by scanning of a spot of ultra-violet laser radiation.
  • the present invention provides a method of forming electrical circuits by the process of electroless deposition of conductive material onto a substrate having receptive and non-receptive areas such that the conductive material is deposited on the receptive areas and not on the non-receptive areas thereby forming a desired conductor pattern, comprising sequentially the steps of:- i) taking a substrate comprising a receptive body formed of insulating material receptive to, or treatable so as to be receptive to, electroless deposition of conductive material; and a non-receptive covering of insulating material overlying the receptive body; ii) removing material by stepwise machining through the depth of the non-receptive covering by ultra-violet induced ablation so as to expose the receptive body in the form of a desired conductor pattern; and iii) electrolessly depositing conductive material on the exposed receptive body.
  • Figs. 1-3 comprise a series of sectional views illustrating the manufacture of a circuit in accordance with the invention
  • Figs. 4-9 comprise a series of sectional views illustrating the manufacture of a double-sided circuit in accordance with the invention.
  • Fig. 10 shows in sectional view an intermediate step in manufacturing a multi-layer circuit in accordance with the invention .
  • a substrate f or a c ircuit i s provided comprising a base 1 of a material receptive to the electroless depositi on of metal .
  • a suitable material is a polyethersulphone seeded with a palladium catalyst. Such can be obtained from LNP Engineering Plastics of Wilmington , De laware , under the trade mark VICTREX
  • PES 3609ML20 ( CATALYTIC ) (Trade Mark)
  • Suitable materials include :- an unseeded polyethersulphone such as (VICTREX ( PES ) supplied by ICI Americas Inc. , of Wilmington, Delaware; a polyimide such as KAPTON (TM) , supplied by El Dupont de
  • Nemours and Company polyethyleneterephthalate ; or indeed any material that proves ablatable under UV radiation and is compatible with other processing steps used.
  • An alternative material comprises a pair of KAPTON layers sandwiching a catalysed polyimide layer. Attachments of the layers to each other may be by means of adhesive, by in situ polymerisation, or by mechanical attachment such as by heat fusing of the layers. Many other suitable materials and arrangements may be envisaged.
  • Fig. 2 shows the substrate of Fig. 1 after exposure to an- excimer laser (such as a KrF/Ar filled QUESTEK 2840 (Trade Mark) supplied by Questek, of Billerica, Massachusetts, which gives ultra-violet radiation of a wavelength 248nm).
  • an- excimer laser such as a KrF/Ar filled QUESTEK 2840 (Trade Mark) supplied by Questek, of Billerica, Massachusetts, which gives ultra-violet radiation of a wavelength 248nm.
  • the exposure is through a mask (not shown) which may either be full-size and in contact with the substrate, or a greater-than-full-size mask with optical reduction to the desired size.
  • the masks are easier to make, having coarser features than the final product: ii) if a full sized mask is in contact with the substrate localised damage can occur both mechanically and due to heat conducted from the mask to the substrate: and iii) using a greater-than-full-size mask allows the mask to be made of materials having a lower critical radiation intensity than the material of the substrate.
  • An alternative to using a mask is to use a hologram to produce either a spot to be tracked over a circuit path, or even to produce an image of a circuit directly.
  • the exposure to UV radiation through a mask results in holes or trenches 3 being formed in the layer 2 to expose the base material 1.
  • ultra-violet radiation processing it is possible to machine down stepwise through layer 2 to the surface of base 1 in steps of e.g. 0.1 - 0.5 ⁇ m at a time.
  • a critical threshold intensity for the material of base l it is possible to provide the bottom 4 of trench 3 with a roughened finish suitable for mechanical keying to deposited conductor.
  • the critical threshold intensity is «0.75 Jem "2 . Above this threshold a clean cut results; below it imperfections are left, somewhat volcano-like in form. Tables 1 and 2 below show respectively the cutting time and imperfection densities obtained on cutting 75 ⁇ m thick polyimide films when imaging an area 40mm x 40mm.
  • the imperfections produced are, as mentioned above, volcano-like in form comprising steep sided cones standing proud of the surface; sometimes the peaks of the cones are slumped to one side giving a hooked appearance that further improves adhesion. Formation of these imperfections is presumed to be due to a shadowing effect; impurities or regions of improved chemical bonding at the surface not ablating and forming a mask for material below.
  • Fig. 3 shows the results of electroless deposition of e.g. copper in the machined substrate of Fig. 2 to form a conductor 5.
  • the conductor 5 may be applied using conventional electroless deposition apparatus as is available from Cirquip Limited, of Leamington Spa, England.
  • a suitable electroless deposition system comprises a Macudep 54 or Macudep 900 (Trade Marks) system supplied by MacDermid GB Ltd.,of Telford, England. It is noteworthy that using this process it is possible to produce conductors having " narrow widths (e.g. 20-50 ⁇ m) and having straight sidewalls.
  • narrow widths e.g. 20-50 ⁇ m
  • the fine controllability of electroless deposition it is possible to deposit conductor to lie flush with the surface of layer 2. This is important for multi-layer circuits since it allows further layers to be applied simply without the need for special pressing techniques (coating by conformally bonding).
  • a process is shown for making a double layer flexible circuit.
  • a substrate is shown comprising a base 1 and covering layer 2, the base 1 being in the form of a sheet approximately 15 ⁇ m thick and having a lower covering layer 6. Both covering layers 2 and 6 being approximately lO ⁇ thick.
  • a first machining step by excimer laser
  • through holes 7 (Fig. 5) are formed through the substrate where vias are required from a top circuit layer to a lower circuit layer.
  • Fig. 6 shows the substrate after two further machining steps in which surface 2 and 6 are machined (by excimer laser) to form holes or trenches 8,9 respectively for top and bottom circuit layers.
  • Figs. 7 and 8 show the progress of electroless deposition of conductor 10 on the layer 1 which can lead to the formation of conductor 11 comprising the conductors of the top and bottom layers, and vias therebetween, as an integral whole and lying flush with the surface of layers 2 and 6.
  • Fig. 9 shows the circuit with applied covercoats 12 and 13 of suitable insulating material (e.g. polyimide or polyether sulphone).
  • the covercoats 12 and 1 can be machined through by further ultra-violet machining to expose conductor 11 where contacts are required. By further exposure to ultra-violet radiation the completed circuits can be cut away from unwanted substrate. Since the metal conductor 11 will not be affected by the ultra-violet radiation these two steps (exposing conductor 11 and cutting free from unwanted substrate) may be combined as one step.
  • Figure 10 shows a route to further multi-layering of circuits.
  • further layer pairs 14, 16 and 15, 17 of receptive and non-receptive materials to layers 2 and 6 respectively of the circuit of Fig. 8 further machining steps allow extra circuit layers to be formed in an analogous manner.
  • metals e.g. copper
  • do not ablate in the same way as the polymeric materials of the substrate it is possible to machine down to copper to make vias or contacts with no fear of destroying already formed conductors.
  • the machining step need not be accurate to finish at the original surface of the receptive body as would be the case were, for example, the material of EP 0273376 used. It is also possible however to have an extremely thin receptive area and machine accurately to that layer.
  • a suitable way of providing a thin layer is to use a receptive adhesive to join two non-receptive covercoats.
  • the adhesive can be made receptive by incorporating submicron particles of palladium doped clays.
  • the optical system can be arranged to produce a line of sufficient width to cover the mask, and hence the circuit, that is scanned over the mask. This has the advantage over a spot scanning system that only a single pass over the mask is required so that problems of overlap or discontinuity are avoided.
  • the pulse rate of the UV laser and the scanning rate of the line are chosen appropriately each area to be ablated will receive the same flux and so will be cut to the same depth.
  • contact masks may be used (made of stainless steel or the like) but these have disadvantages in that the size of feature attainable is limited by the size of feature that can be formed on the mask; and further, damage to the substrate may result both through mechanical contact and due to heating of the mask by the ultra-violet radiation.
  • an optically reduced mask may be used.
  • a direct contact mask may be preferable as it allows larger circuit areas to be made and also damage from the mask is less of a problem if the features concerned are coarser.
  • one piece of apparatus could be used in at least two modes:- i) Direct contact mask to produce large circuits having features of the same scale as the features attainable for the mask material; ii) optically reduced mask allowing features finer than are attainable for mask materials to be attained on limited sized circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

On a mis au point un procédé de formation de circuits électriques par dépôt autocatalytique de matière conductrice sur un substrat comportant des surfaces réceptrices et non réceptrices, de sorte que la matière conductrice soit déposée sur les surfaces réceptrices et non sur les surfaces non réceptrices, formant ainsi une configuration conductrice désirée, comprenant en séquence les étapes consistant i) à prendre un substrat comprenant un corps (1) récepteur formé de matière isolante réceptrice, ou traitable de manière à être réceptrice au dépôt autocatalytique de matière conductrice, ainsi qu'une couverture (2, 6) non réceptrice de matière isolante recouvrant le corps récepteur; ii) à éliminer de la matière par usinage par étapes à travers la profondeur de la couverture non réceptrice par ablation induite par rayons ultraviolets, de manière à exposer le corps récepteur sous la forme d'une configuration conductrice voulue; iii) à procéder au dépot autocatalytique de matière conductrice (11) sur le corps récepteur exposé afin de former la configuration conductrice. On peut appliquer davantaage de couches de matière réceptrice (14, 15) et de matière non réceptrice (16, 17) afin de permettre la fabrication d'autres couches de circuits. Un laser excimeur est une source de rayonnement ultraviolet adéquate.
EP19890911825 1988-10-27 1989-10-27 Circuits electriques affines Withdrawn EP0440691A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB888825219A GB8825219D0 (en) 1988-10-27 1988-10-27 Fine featured electrical circuits
GB8825219 1988-10-27

Publications (1)

Publication Number Publication Date
EP0440691A1 true EP0440691A1 (fr) 1991-08-14

Family

ID=10645911

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890911825 Withdrawn EP0440691A1 (fr) 1988-10-27 1989-10-27 Circuits electriques affines

Country Status (5)

Country Link
EP (1) EP0440691A1 (fr)
JP (1) JPH04501487A (fr)
AU (1) AU4421589A (fr)
GB (1) GB8825219D0 (fr)
WO (1) WO1990004911A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077085A (en) * 1987-03-06 1991-12-31 Schnur Joel M High resolution metal patterning of ultra-thin films on solid substrates
DE4417245A1 (de) * 1994-04-23 1995-10-26 Lpkf Cad Cam Systeme Gmbh Verfahren zur strukturierten Metallisierung der Oberfläche von Substraten

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1918186A1 (de) * 1968-05-04 1970-10-15 Licentia Gmbh Verfahren zur Herstellung von metallischen Leiterbildern mit Durchmetallisierungen auf einer aus katalysiertem Basismaterial bestehenden,unkaschierten Leiterplatte
US4432855A (en) * 1982-09-30 1984-02-21 International Business Machines Corporation Automated system for laser mask definition for laser enhanced and conventional plating and etching
US4414059A (en) * 1982-12-09 1983-11-08 International Business Machines Corporation Far UV patterning of resist materials
EP0164564A1 (fr) * 1984-05-18 1985-12-18 Siemens Aktiengesellschaft Agencement pour la fabrication de trous borgnes dans une construction laminée
JPS61108195A (ja) * 1984-11-01 1986-05-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 基板上に電気的に連続した層を形成する方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9004911A1 *

Also Published As

Publication number Publication date
GB8825219D0 (en) 1988-11-30
WO1990004911A1 (fr) 1990-05-03
JPH04501487A (ja) 1992-03-12
AU4421589A (en) 1990-05-14

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