EP0416669A2 - Logik-Kompilator zum Entwurf von Schaltungsmodellen - Google Patents

Logik-Kompilator zum Entwurf von Schaltungsmodellen Download PDF

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Publication number
EP0416669A2
EP0416669A2 EP90202055A EP90202055A EP0416669A2 EP 0416669 A2 EP0416669 A2 EP 0416669A2 EP 90202055 A EP90202055 A EP 90202055A EP 90202055 A EP90202055 A EP 90202055A EP 0416669 A2 EP0416669 A2 EP 0416669A2
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European Patent Office
Prior art keywords
model
circuit
circuit model
user
generating
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Granted
Application number
EP90202055A
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English (en)
French (fr)
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EP0416669A3 (en
EP0416669B1 (de
Inventor
Jeffrey A. Werner
Daniel R. Watkins
Jimmy S. Wong
Yen C. Chang
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LSI Corp
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LSI Logic Corp
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Publication of EP0416669A3 publication Critical patent/EP0416669A3/en
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Publication of EP0416669B1 publication Critical patent/EP0416669B1/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • This invention relates to logic compilers which are used in the computer aided design of logic circuits, and in particular, to an improved logic compiler which incorporates improved software verifying techniques, improved user interface techniques, and improved circuit model generation techniques.
  • Logic compilers also known as functional generators, are software tools used to create logic models, or circuit models.
  • the model describes the mathematical or logical relationships between inputs into the model and outputs outputted from the model.
  • the logic complier may also design the actual circuit represented by the circuit model.
  • the resulting circuit models may be then incorporated into a system model whose performance can then be verified.
  • the system model may be used to develop the actual hardware corresponding to the system model.
  • prior art logic compilers generally require the user to have a relatively detailed knowledge of the logic compiler in order to properly instruct the logic compiler to generate a desired circuit model.
  • the invention is a logic compiler system which creates, in real time, a desired circuit model, selected by the user via a menu driven display, from one or more types of circuit building blocks.
  • the menu driven display provides a selection of options and features to the user through which the user instructs the logic compiler to develop the desired circuit model.
  • the logic compiler in real time, generates the desired circuit model, which includes the circuit design itself.
  • the user does not simply select one circuit model out of literally thousands of possible circuit models stored in a library.
  • the logic compiler builds circuit models from one or more types of circuit building blocks, wherein algorithms in the logic compiler, generally associated with each feature selectable by the user, generate the required building blocks and connect the building blocks together to create the selected circuit model. Since each algorithm associated with a feature to be added to a circuit model may be used to modify many different circuit configurations, the compiler enables the generation of thousands of different types of circuit models without requiring a commensurate increase in software.
  • Verification of each of the perhaps thousands of different circuit models which may be developed using a single logic compiler is done automatically by the logic compiler.
  • the logic compiler in real time, creates a circuit model for each of the possible circuit models one at a time and also generates a corresponding behavior model, which is simply a mathematical model of the actual circuit selected.
  • a simple mathematical model representing the actual operation of the circuit is also created which provides the correct output of the circuit in response to an input.
  • a circuit model and corresponding behavior model is generated, a pattern of input signals is generated and automatically applied to both the behavior model and the circuit model.
  • the software programmer reviews the flags identifying that the software related to that particular circuit model must be debugged.
  • test pattern In some cases more than one test pattern is required to verify all operation capabilities of each circuit model.
  • the verification process using this inventive automated means is now one of the least labor intensive of all the tasks required to develop a logic compiler.
  • a novel menu driven user interface is described.
  • the user interface of this invention enables the user to efficiently develop a circuit model and enables the user to obtain the performance characteristics of each of the circuit models capable of being generated by the logic compiler. Generating the performance characteristics is accomplished by the logic compiler, in real time, by analyzing a particular circuit model chosen by the user and displaying the specific performance characteristics of the chosen circuit. The user may also verify the selected circuit model using the user's chosen input signals.
  • Fig. 1 shows the main menu of the logic compiler displayed to a user.
  • the logic compiler actually consists of a number of logic compilers, each dedicated to creating a certain general class of logic circuits.
  • the various classes of logic circuits which may be created with the preferred embodiment logic compiler described herein are adders, counters, multiplexers, incrementers/­decrementers, decoders, shift registers, and fall-through FIFOs.
  • the user then inputs into a keyboard a desired general class of logic circuits, resulting in the particular logic compiler dedicated to that class being accessed.
  • Fig. 2 the menu shown in Fig. 2 is displayed giving the various types of adders which may be created by the logic compiler.
  • the types of adders which may be chosen are carry select adder, carry look-ahead adder, carry skip adder, and ripple adder. These general types of adders are well known in the art.
  • the hardware technology is a selection of either CMOS10K or LCB15, where CMOS10K and LCB15 correspond to a particular silicon implementation of the circuitry which will form the adder.
  • the user is then prompted to provide an identifying name to the circuit model being created.
  • the user is prompted to input the desired bit width of the adder.
  • the desired bit width of the adder For purposes of illustration, assume the user has selected a four bit adder circuit with look-ahead carry. The logic compiler will then generate the selected circuit.
  • a novel feature of the logic compiler of this invention is that the logic compiler generates the various selected circuit models in real time without simply choosing the final selected circuit from a library containing all possible permutations of circuit models.
  • an algorithm within the logic compiler is called upon to generate the various connections and circuit building blocks required for a four bit adder circuit with look-ahead carry.
  • a larger bit width of the selected adder circuit increases the number of logic gates needed for the adder circuit, the connections between these building blocks of the adder circuit are systematic so that a single algorithm can generate adder circuits having a wide range of bit widths.
  • This algorithm may be readily developed by one of ordinary skill in the art given the established and well-­known logic design techniques for determining the systematic connections between the building blocks comprising the adder circuit to create an adder circuit of any bit width having look-ahead carry.
  • This type of software approach is used in the preferred embodiment logic compiler to generate all the adder circuit models available to the user.
  • a total of 256 different adders are enabled by the adder logic compiler using algorithms which systematically generate all the permutations of possible adders without the use of a library. Consequently, the compiler requires much less memory than a compiler which, to create 256 adder circuit models, must store all 256 different adders in a library.
  • Fig. 4 shows certain general classes of logic devices and certain features available to a user. It will be apparent to one of ordinary skill in the art of software programming how to incorporate each of the offered features into a selected logic circuit having a selected bit width so that, generally, each feature may be considered as a signal subroutine in the logic compiler software program which is accessed each time that particular feature is selected. Developing the software for the logic compiler using independent subroutines enables the logic compiler to be debugged more quickly and in a more efficient manner.
  • the logic compiler is menu based so as to provide the user with clear options in the most efficient order as determined by the software programmer.
  • the user may request help by pressing a key of the keyboard which causes a help subroutine associated with the menu to be displayed on the screen.
  • the various menus and queries put to the user are dependent upon the user's previous input so that only relevant menus and options are displayed.
  • the software used is platform independent, which means the logic compiler can be used on a variety of computer systems. This is accomplished by using an interpreter which translates and executes each line of the computer program before the next line of the computer program is considered. Although an interpreted program is slow, as much as 20 times slower than an assembled program, the interpreted program speeds up program development because the effect of the source code changes can be seen immediately.
  • a NET file indicates all the interconnections between the building blocks used in a particular circuit model and, as such, represents the actual circuit design.
  • a NET file may represent a simple eight bit ripple adder, wherein each of the various building blocks in the NET file would be a full adder. Each full adder would have three inputs, one input being a carry bit, represented by three variables. Each full adder would also have two outputs (a sum bit and a carry bit), represented by two variables. An output of one full adder is applied to the input of another full adder where the same variable is shown in the NET file as being both an input and an output variable. Thus, by viewing the NET file, all the interconnections between the full adders may be known.
  • the NET file is eventually used to implement the particular circuit into hardware.
  • a variety of types of building blocks may be used by the logic complier in the creation of a selected circuit.
  • Various building blocks which may be used include: transistor or component level; logic gate level; functional level (e.g., full adders, incrementers); or Register Translation Language, wherein a building block is represented by its operation (e.g., "input+1") and a circuit corresponding to that operation is utilized.
  • the circuit models may be created using one or more types of building blocks, as chosen by the programmer as being the most expedient means of creating a particular circuit model.
  • each possible type of logic circuit model which may be created by the logic compiler must be verified by the programmer to determine if the circuit models accurately model the circuit selected by a user.
  • a programmer had to apply a test pattern input to the input of each possible circuit model and compare the output to an expected value manually.
  • the verification portion of the development of the logic compiler was the most labor intensive portion in the development of the compiler.
  • verification of each circuit model is verified automatically in a continuous verification process.
  • the programmer After the software programmer has completed the algorithms necessary for the generation of all circuit models to be generated by the compiler, the programmer implements the verification program represented by the flowchart of Fig. 5, which verifies the accuracy of each circuit model which may be created by the logic compiler.
  • step 1 of the verification process of Fig. 5 the logic compiler automatically selects a technology (CMOS10K or LCB15) in which to build the circuits in silicon.
  • CMOS10K or LCB15 a technology in which to build the circuits in silicon.
  • this step can also apply to circuits formed in other semiconductor materials, such as gallium arsenide.
  • the logic compiler uses a global look-up table to enable the NET file generator to create circuit models having characteristics of the actual corresponding circuit implemented in the particular technology selected.
  • the verification program After the particular technology is selected the verification program generates in step 2 a first NET file associated with a first circuit model.
  • a simulation file is generated for the particular circuit model associated with the NET file.
  • the simulation file formats the circuit model to accept the various inputs to be applied to the circuit model and to provide the output signals from the model for storage after the simulation is run.
  • a simulation file is generated for a behavior model corresponding to the previously generated logic model, wherein the behavior model is a simple mathematical model representing the actual operation of the circuit in response to an input.
  • a behavior model software program is one fifth to one thirtieth the length of the circuit model program, since a behavior model can be simply described by equations without consideration of any interconnections.
  • a test pattern file is created which consists of the various test input signals, or test vectors, to be applied to both the circuit model and the behavior model to test all the various logic gates, interconnections, and features of the circuit model.
  • the test pattern file is generated by algorithms which are dependent upon the type of circuit to be verified and may be written by a software programmer of ordinary skill in the art using well-known techniques.
  • a pattern file containing over 1,000 test vectors must be created, wherein each test vector represents a single set of parallel or serial inputs into the circuit model and behavior model, and wherein each test vector is sequentially applied to the inputs of the circuit model and behavior model.
  • a file is generated containing the features of the circuit model generated.
  • This file will be used by the behavior model so that, in effect, the behavior model will possess those features of the logic model.
  • a feature may be asynchronous clear, which would be performed by the behavior model.
  • step 7 gate delays for each of the gates comprising the circuit model are analyzed by looking at the loading on each gate to determine if the delay is acceptable. If a gate delay is unacceptable, a flag is set to identify the problem.
  • step 8 simulation is run on the model of the actual circuit implemented in silicon by applying all test vectors previously generated to the inputs of the circuit model.
  • the outputs of the circuit model resulting from the application of each test vector to the inputs of the circuit model are then stored in a logic model output file.
  • step 9 simulation is run on the behavior model and the outputs stored in a behavior model output file.
  • step 10 the outputs of the logic model output file and the behavior model output file are compared line by line to determine any differences between the outputs of the behavior model and the outputs of the circuit model. If the comparison of the output files indicates an output of the circuit model is different than the corresponding output of the behavior model, these lines of the output files are written into a difference table.
  • next line of the output files is compared until a last line of the output files is detected. When this last line is detected, a next NET file is then generated and the verification process is repeated. Once all the possible circuit models generated by the compiler have been tested and the outputs compared, the programmer then reviews the difference table to determine the accuracy of the software program. The programmer then debugs the portion of software which caused the discrepancy.
  • circuit model programs are written in a modular fashion, where a subroutine is dedicated to a certain additional feature, the debugging and testing of the software is easily done by isolating the subroutine that implements that feature associated with the non matching outputs.
  • the compiler may be debugged in less time than in compilers not using the above-described verification process.
  • a logic compiler to develop a behavior model associated with each circuit model available within the compiler enables a number of various highly commercial features of the compiler. For example, the user may be ensured that the user's selected circuit model is error free by directing the logic compiler to display the output of the behavior model and the circuit model in response to various inputs selected by the user. Alternatively, the test inputs may be generated using the test pattern generator. The user, in effect, implements the verification process of Fig. 5 for one selected NET file only. Hence, a valuable feature provided by the incorporation of a behavior model generator in the logic compiler is that it gives the user access to a customized verification process and allows the user to obtain precise performance specifications on a variety of custom input patterns on any circuit created by the logic compiler.
  • the menu driven display leads the user through the process required for the verification process and prompts the user as to the desired selection of the input signals.
  • a user could not perform verification in real time since there would be no verification program in the compiler which generates a behavior model.
  • the user may also request documentation, generated in real time, on the specific circuit model the user has selected simply by responding to a prompt displayed by the menu.
  • the logic compiler estimates the various accumulated delays within the selected circuit and generates performance data, in real time, on that particular circuit.
  • Schematic diagrams of the selected circuit model may also be selected by the user and printed out.
  • Documentation for the most popular types of circuits which can be created by the compiler is fixed in memory in the compiler.
  • the documentation for an adder with a carry look-ahead feature having various popular bit widths may be displayed as shown in Fig. 6.
  • the various parameters displayed in the documentation are inputted by the software programmer based on known delays and known hardware constraints for each of the general types of circuits created by the logic compiler.
  • the user may then incorporate the circuit model into a larger system model containing additional circuit models.
  • a PINS file shown in Fig. 7, is created along with the NET file for a particular circuit.
  • the PINS file contains a listing of the input and output terminals of the circuit represented by the NET file and is basically used to readily indicate the various parts of the circuit.
  • the PINS file also contains the identification name of the NET file given by the user, the bit width of the modeled device, and the technology in which the circuit is to be implemented in silicon.
  • the above-described logic compiler may also find applicability for creating analog circuit models. All software within the logic compiler described above may be written by a software programmer of ordinary skill in the art, given the above description of the logic compiler. Of course, numerous differences in computer programs will result due to the differing techniques and skill levels of software programmers. As mentioned previously, in the preferred embodiment, the compiler software uses an interpreter to interact with a computer so as to enable the compiler to be used on a variety of computer systems to accommodate the widest number of users.

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EP90202055A 1989-09-05 1990-07-27 Logik-Kompilator zum Entwurf von Schaltungsmodellen Expired - Lifetime EP0416669B1 (de)

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US40324789A 1989-09-05 1989-09-05
US403247 1989-09-05

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EP0416669A2 true EP0416669A2 (de) 1991-03-13
EP0416669A3 EP0416669A3 (en) 1993-05-05
EP0416669B1 EP0416669B1 (de) 1998-09-09

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US5377122A (en) * 1989-09-05 1994-12-27 Lsi Logic Corporation Logic compiler for design of circuit models
US6152612A (en) * 1997-06-09 2000-11-28 Synopsys, Inc. System and method for system level and circuit level modeling and design simulation using C++

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Cited By (4)

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Publication number Priority date Publication date Assignee Title
US5377122A (en) * 1989-09-05 1994-12-27 Lsi Logic Corporation Logic compiler for design of circuit models
EP0508075A2 (de) * 1991-04-12 1992-10-14 Lsi Logic Corporation Automatische Logikmodell-Erzeugung aus einer Schaltschema-Datenbank
EP0508075A3 (en) * 1991-04-12 1994-07-13 Lsi Logic Corp Automatic logic model generation from schematic data base
US6152612A (en) * 1997-06-09 2000-11-28 Synopsys, Inc. System and method for system level and circuit level modeling and design simulation using C++

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US5377122A (en) 1994-12-27
DE69032640D1 (de) 1998-10-15
EP0416669A3 (en) 1993-05-05
EP0416669B1 (de) 1998-09-09

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