EP0409830A1 - Mikrorechner mit mitteln zur unterscheidung von rücksetzsignalen - Google Patents
Mikrorechner mit mitteln zur unterscheidung von rücksetzsignalenInfo
- Publication number
- EP0409830A1 EP0409830A1 EP19880903791 EP88903791A EP0409830A1 EP 0409830 A1 EP0409830 A1 EP 0409830A1 EP 19880903791 EP19880903791 EP 19880903791 EP 88903791 A EP88903791 A EP 88903791A EP 0409830 A1 EP0409830 A1 EP 0409830A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- reset signal
- processor
- microcomputer
- reset
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Definitions
- the present invention relates to a microcom ⁇ puter having a processor of a type operating with a reset signal and a RAM whose contents are changed periodically from an initial condition. It is known to control one or more functions in a vehicle using an electronic control unit incorpo ⁇ rating a microcomputer. In many applications, the microcomputer has an associated RAM whose contents are changed periodically. One example of this is an elec- tronically controlled ignition system. Further, the control unit usually is arranged to reset the contents of the RAM to a set of initial data on initial switch on of power to the -unit.
- the microcomputer operates with a reset signal but this does not refresh the RAM with the set of initial data. It is therefore necessary to distinguish between a reset signal which requires refreshing of the RAM with the set of initial data and a further reset signal which does not require this.
- the microcomputer uses a single pin for all reset signals which makes difficult the process of distinguishing reset signals one from another.
- the present invention provides a microcomput ⁇ er having a processor arranged to operate with a first reset signal, a power supply arrangement for supplying the processor with a further reset signal via an input and with power, a store, the contents of which are refreshed by the processor on receipt of a further reset signal by the processor, and means for distin ⁇ guishing between a first reset signal and a further reset signal, characterised in that a signal indicative of a further reset signal is fed to a further input of the processor and the processor is arranged to monitor both the inputs in order to distinguish between a cyclic reset signal and a further reset signal.
- a microcomputer 10 receives power from regu- lator unit 11.
- the regulator 11 is also assumed to provide one or more reset signals to the microcomputer 10 via a reset output 11a.
- the most usual reset from the regulator 11 is a power ON reset which is recognised by the microcomputer and used to control refreshing of a RAM 12 associated with the microcomputer 10. It is also possible for there to be generated other reset signals on the reset output 11a e.g. undervoltage reset, as long as all such reset signals should result in the RAM being refreshed with initial data.
- the microcomputer is arranged to operate normally with a cyclic reset in which case the contents of the RAM 12 should not be refreshed.
- the microcomputer 10 has only one reset pin 14 and so both cyclic and other reset signals are fed to the pin 1 .
- This is represented in the drawing by an OR gate 15 having one input 16 connected to the reset output 11a of the regulator unit and the other input 17 arranged to receive the cyclic reset signal.
- a storage element 20 is connected between the reset signal output 11a and a pin 21 of an input part of the microcomputer.
- the arithmetic program of the microprocessor interrogates the in ⁇ put part to determine whether or not a signal is pres ⁇ ent at the pin 21 indicating the fact that the reset signal is not a cyclic reset signal. If there is a signal present at the pin 21 then the microcomputer causes the RAM 12 to be refreshed with initial data; if no signal is present the microcomputer knows that the reset was a cyclic reset signal and operates accord ⁇ ingly.
- reset signals other than cyclic resets which must be distinguished from restes which require reloading of the memory e.g. watchdog circuit signals which are produced when a regular signal from the microprocessor is not received by the watchdog circuit.
- the above arrangement provides a reliable way for distinguishing between reset signals and so avoid errors.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP1988/000314 WO1989009957A1 (en) | 1988-04-14 | 1988-04-14 | Microcomputer with reset signal distinguishing means |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0409830A1 true EP0409830A1 (de) | 1991-01-30 |
Family
ID=8165261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19880903791 Ceased EP0409830A1 (de) | 1988-04-14 | 1988-04-14 | Mikrorechner mit mitteln zur unterscheidung von rücksetzsignalen |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0409830A1 (de) |
JP (1) | JPH03503689A (de) |
WO (1) | WO1989009957A1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2657181A1 (fr) * | 1990-01-12 | 1991-07-19 | Neiman Sa | Procede et dispositif pour associer a la reception d'impulsions de reinitialisation par un microprocesseur l'acces a des sous-programmes differents. |
DE4112334A1 (de) * | 1991-04-16 | 1992-10-22 | Bosch Gmbh Robert | Mehrrechnersystem in einem kraftfahrzeug |
US5590235A (en) * | 1993-12-03 | 1996-12-31 | Papst-Motoren Gmbh & Co. Kg | DC motor control with periodic reset |
US5463336A (en) * | 1994-01-27 | 1995-10-31 | Rockwell International Corporation | Supply sensing power-on reset circuit |
DE4409286C1 (de) * | 1994-03-18 | 1995-08-10 | Audi Ag | Verfahren zum Erkennen der Ursache eines Reset-Vorgangs eines durch einen Mikroprozessor gesteuerten Systems sowie Schaltung zum Durchführen des Verfahrens |
US5898232A (en) * | 1995-11-08 | 1999-04-27 | Advanced Micro Devices, Inc. | Input/output section of an integrated circuit having separate power down capability |
US5860125A (en) * | 1995-11-08 | 1999-01-12 | Advanced Micro Devices, Inc. | Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an asynchronous partial reset and an asynchronous master reset |
US5960195A (en) * | 1996-06-03 | 1999-09-28 | Samsung Electronics Co., Ltd. | Intelligent volatile memory initialization |
JP3881177B2 (ja) * | 2001-02-06 | 2007-02-14 | 三菱電機株式会社 | 車両用制御装置 |
DE10306553B4 (de) * | 2003-02-17 | 2005-11-24 | Siemens Ag | Steuervorrichtung für Kraftfahrzeuge und Verfahren zum Betreiben einer Steuervorrichtung |
DE10329196A1 (de) * | 2003-06-28 | 2005-01-20 | Audi Ag | Verfahren zum Reset von elektronischen Fahrzeug-Steuergeräten |
IL236627A0 (en) * | 2015-01-11 | 2015-04-30 | Storone Ltd | Method and system for controlling volatile memory |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1112369A (en) * | 1978-07-21 | 1981-11-10 | Tandy Corporation | Video processing logic |
US4410991A (en) * | 1981-06-03 | 1983-10-18 | Gte Laboratories Incorporated | Supervisory control apparatus |
JPS59218525A (ja) * | 1983-05-27 | 1984-12-08 | Maitetsuku:Kk | リセツト機能を持つたパ−ソナルコンピユ−タ |
-
1988
- 1988-04-14 EP EP19880903791 patent/EP0409830A1/de not_active Ceased
- 1988-04-14 JP JP88503603A patent/JPH03503689A/ja active Pending
- 1988-04-14 WO PCT/EP1988/000314 patent/WO1989009957A1/en not_active Application Discontinuation
Non-Patent Citations (1)
Title |
---|
See references of WO8909957A1 * |
Also Published As
Publication number | Publication date |
---|---|
JPH03503689A (ja) | 1991-08-15 |
WO1989009957A1 (en) | 1989-10-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19900906 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB IT SE |
|
17Q | First examination report despatched |
Effective date: 19911223 |
|
RAP3 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ROBERT BOSCH GMBH |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED |
|
18R | Application refused |
Effective date: 19930426 |