WO1989009957A1

WO1989009957A1 - Microcomputer with reset signal distinguishing means

Info

Publication number: WO1989009957A1
Application number: PCT/EP1988/000314
Authority: WO
Inventors: Jörg BONITZ; Siegmar FÖRSTER; Siegfried Rohde
Original assignee: Robert Bosch Gmbh
Priority date: 1988-04-14
Filing date: 1988-04-14
Publication date: 1989-10-19
Also published as: EP0409830A1; JPH03503689A

Abstract

A microcomputer comprises a processor (10) arranged to operate with a cyclic reset signal and is responsive to a further reset signal on an input (14) to refresh the contents of a RAM (12) associated with the processor. In order to distinguish between a cyclic reset signal and a further reset signal, a signal indicative of a further reset signal is fed to a further input (21) of the processor which then monitors both inputs (14, 21).

Description

MICROCOMPUTER WITH RESET SIGNAL DISTINGUISHING MEANS

The present invention relates to a microcom¬ puter having a processor of a type operating with a reset signal and a RAM whose contents are changed periodically from an initial condition. It is known to control one or more functions in a vehicle using an electronic control unit incorpo¬ rating a microcomputer. In many applications, the microcomputer has an associated RAM whose contents are changed periodically. One example of this is an elec- tronically controlled ignition system. Further, the control unit usually is arranged to reset the contents of the RAM to a set of initial data on initial switch on of power to the -unit.

The microcomputer operates with a reset signal but this does not refresh the RAM with the set of initial data. It is therefore necessary to distinguish between a reset signal which requires refreshing of the RAM with the set of initial data and a further reset signal which does not require this. However, the microcomputer uses a single pin for all reset signals which makes difficult the process of distinguishing reset signals one from another.

A previous proposal for distinguishing reset signals has relied on software and requires the micro- computer to analyse the incoming reset signals and the current contents of the RAM and decide which reset signals will cause the RAM to be refreshed. Unless care is taken, this process can occupy a relatively long period of time in the computation cycle of the microcomputer and hence it would be preferable to find another way of overcoming the problem.

The present invention provides a microcomput¬ er having a processor arranged to operate with a first reset signal, a power supply arrangement for supplying the processor with a further reset signal via an input and with power, a store, the contents of which are refreshed by the processor on receipt of a further reset signal by the processor, and means for distin¬ guishing between a first reset signal and a further reset signal, characterised in that a signal indicative of a further reset signal is fed to a further input of the processor and the processor is arranged to monitor both the inputs in order to distinguish between a cyclic reset signal and a further reset signal. In order that the present invention be more readily understood an embodiment thereof will now be described by way of example with reference to the accompanying drawing which shows a block diagram of an arrangement according to the present invention. The figure shows only a part of an electronic control unit but this is considered sufficient in view of the fact that the parts of the unit not shown are know .

A microcomputer 10 receives power from regu- lator unit 11. In this block diagram, the regulator 11 is also assumed to provide one or more reset signals to the microcomputer 10 via a reset output 11a. The most usual reset from the regulator 11 is a power ON reset which is recognised by the microcomputer and used to control refreshing of a RAM 12 associated with the microcomputer 10. It is also possible for there to be generated other reset signals on the reset output 11a e.g. undervoltage reset, as long as all such reset signals should result in the RAM being refreshed with initial data.

The microcomputer is arranged to operate normally with a cyclic reset in which case the contents of the RAM 12 should not be refreshed. However, the microcomputer 10 has only one reset pin 14 and so both cyclic and other reset signals are fed to the pin 1 . This is represented in the drawing by an OR gate 15 having one input 16 connected to the reset output 11a of the regulator unit and the other input 17 arranged to receive the cyclic reset signal. In order to distinguish a cyclic reset signal from the other reset signals, a storage element 20 is connected between the reset signal output 11a and a pin 21 of an input part of the microcomputer. Directly after the microprocessor detects the presence of a reset signal on its reset input pin 14, the arithmetic program of the microprocessor interrogates the in¬ put part to determine whether or not a signal is pres¬ ent at the pin 21 indicating the fact that the reset signal is not a cyclic reset signal. If there is a signal present at the pin 21 then the microcomputer causes the RAM 12 to be refreshed with initial data; if no signal is present the microcomputer knows that the reset was a cyclic reset signal and operates accord¬ ingly. There are reset signals other than cyclic resets which must be distinguished from restes which require reloading of the memory e.g. watchdog circuit signals which are produced when a regular signal from the microprocessor is not received by the watchdog circuit.

The above arrangement provides a reliable way for distinguishing between reset signals and so avoid errors.

Claims

CLAIMS :

1. A microcomputer having a processor (10) arranged to operate with a first reset signal, a power supply arrangement (11) for supplying the processor (10) with a further reset signal via an input (14) and with power, a store (12), the contents of which are refreshed by the processor (10) in receipt of a further reset signal by the processor, and means for distin¬ guishing between a first reset signal and a further reset signal, characterised in that a signal indicative of a further reset signal is fed to a further input (21) of the processor and the processor (10) is ar¬ ranged to monitor both the inputs (14, 21) in order to distinguish between a first reset signal and a further reset signal.

2. A microcomputer according to claim 1 , wherein the further input (21 ) is connected to the power supply arrangement (11) via a storage means (20).