EP0409030A1 - Circuit pour le fonctionnement d'un tableau indicateur à cristal liquide - Google Patents

Circuit pour le fonctionnement d'un tableau indicateur à cristal liquide Download PDF

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Publication number
EP0409030A1
EP0409030A1 EP90113043A EP90113043A EP0409030A1 EP 0409030 A1 EP0409030 A1 EP 0409030A1 EP 90113043 A EP90113043 A EP 90113043A EP 90113043 A EP90113043 A EP 90113043A EP 0409030 A1 EP0409030 A1 EP 0409030A1
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EP
European Patent Office
Prior art keywords
register
pulse
segment
shift register
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90113043A
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German (de)
English (en)
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EP0409030B1 (fr
Inventor
Peter Broderick
Graham Stout
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Germany GmbH
Original Assignee
Eurosil Electronic GmbH
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Filing date
Publication date
Application filed by Eurosil Electronic GmbH filed Critical Eurosil Electronic GmbH
Publication of EP0409030A1 publication Critical patent/EP0409030A1/fr
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Publication of EP0409030B1 publication Critical patent/EP0409030B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/16—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source
    • G09G3/18—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source using liquid crystals

Definitions

  • the invention relates to a circuit arrangement with a microprocessor having a first clock generator for operating a liquid crystal display in the time step multiplex method according to the preamble of claim 1.
  • Such a circuit arrangement is known from DE-PS 29 39 553.
  • a liquid crystal display LCD with rear electrode pulse trains R1, R2, R3 and segment electrode pulse trains SA, ..., SH is driven, for which purpose pulse patterns corresponding to the pulse trains are emitted from a read-only memory ROM.
  • the read-only memory ROM is controlled by a circuit INFO, for example a data processing device, with which the information to be displayed with the liquid crystal display LCD can be output as a function of a takeover signal TO of the read-only memory ROM.
  • the pulse patterns corresponding to the pulse sequences are put together in the read-only memory ROM as a function of the information to be displayed and sent by the INFO circuit and by means of pulse signals of different pulse lengths.
  • the pulse pattern for the back electrode pulses are connected in parallel to a memory STR connected downstream of the read-only memory ROM and the pulse pattern for the segment electrode pulses is connected in series to one of the Read-only memory ROM provided downstream shift register arrangement.
  • the two memories STR and STS have a number of memory locations for the parallel supply of the pulses, which correspond to the number of back electrodes or segment electrodes of all display locations.
  • the pulse signals of different pulse lengths are supplied by a frequency divider FT, which also supplies a take-over pulse TC to the memory STS connected downstream of the shift register arrangement SR and to the memory STR, which in turn drive the liquid crystal display LCD.
  • the read-only memory ROM and the frequency divider FT are controlled with the pulses of a clock generator CL, which also generates the shift clock for the shift register arrangement SR.
  • the shift register arrangement SR has a number of stages which corresponds to the number of total segment electrodes present in the liquid crystal display.
  • the memory STS which drives the liquid crystal display LCD functions not only as a memory circuit but also as a voltage adjustment circuit in that the voltage of the signals to be output from the memory is adapted to the requirements imposed by the liquid crystal display LCD.
  • each display point has three back electrodes and three segment electrodes (see the exemplary embodiment according to FIG. 4 of the above-mentioned document).
  • the microcomputer LCD-III developed by Hitachi (data sheet “Hitachi microcomputer Databook 4-bit single-chip", Sept. 1984, pages 273 to 298) developed for direct control of a liquid crystal display offers the possibility to select the multiplex rate in software, whereby the Electrode pulse trains corresponding pulse patterns in the main memory of the processor are ready to be read into a random access memory RAM when the liquid crystal display is operating in multiplex mode; from there they are pushed into a shift register and then read out in parallel in a memory whose memory locations correspond to the number of segment electrodes. Finally, this data is fed directly to the driver stages that drive the segment electrodes.
  • the disadvantage here is that the control of the liquid crystal display is shut down, that is, the display goes out when the microprocessor is stopped to save power.
  • the microprocessor is also overloaded unnecessarily, since the shift register has to be reloaded with data for each time cycle.
  • the object of the invention is therefore to provide a circuit arrangement for operating a liquid crystal display of the type mentioned, in which an autonomous data storage is possible regardless of the operating state of the microprocessor.
  • the shift register arrangement is designed as a ring register. This makes it possible to have data to be displayed which does not change over a certain period of time circulate in the ring register, the data for controlling the liquid crystal display being fed to the driver stages of the segment electrodes after each circulation.
  • the cut for the first and second place data to be transmitted in chronologically successive clock steps of the clock frequency generated by the first clock generator transmitted over a single data channel.
  • the information to be displayed is updated by only updating the contents of such register locations, the associated segment electrodes of which are required for the information currently to be displayed, and the data signals in the other register locations being pushed through to the old positions by the ring register .
  • the microprocessor contains a second clock generator, the clock frequency of which is lower than the clock frequency of the first clock generator.
  • the first clock generator is switched off and the liquid crystal display is kept in operation by means of the second clock generator by maintaining the data signals in the register positions of the ring register and switching them to the driver stages at the clock frequency of the second clock generator. In this idle state of the microprocessor, its power consumption is significantly reduced.
  • the generation of the back electrode and segment electrode pulse trains is generated Voltage level provided a regulated voltage source, which provides an output voltage compensating the temperature dependence of the liquid crystal display. Since the voltage levels to be applied to the liquid crystal display are hereby temperature-compensated independently of the fluctuations in the supply voltage and with regard to the temperature behavior of the liquid crystal display, the contrast of the liquid crystal display is advantageously kept constant.
  • FIG. 1 of an exemplary embodiment of the subject matter of the invention serves to clarify the principle of autonomous data storage according to the invention, a simple representation being chosen for the sake of clarity.
  • a first interface P1 or a second interface P2 receives the data or control data to be displayed in a liquid crystal display LCD from a microprocessor via a data line 10.
  • the liquid crystal display LCD is made up of 16 segment electrodes and four back electrodes. Accordingly, 16 driver stages TS1 to TS16 are required to control the segment electrodes. Depending on the pulse patterns supplied to them, these driver stages generate the segment electrode pulse trains for driving the electrodes. These pulse patterns corresponding to the segment electrode pulse trains are stored in a 4-bit shift register 2 with 16 stages.
  • the shift register 2 works as a ring register in that the data of the last register point for controlling the 16th segment can be shifted back into the first stage via a data line. Accordingly, if the same information is to be displayed over a certain period of time, the microprocessor 1 sends a corresponding one. Control signal 1 "MASK", which causes the old data to be shifted back into the shift register 2 via the first interface P1.
  • Control signal 1 "MASK” which causes the old data to be shifted back into the shift register 2 via the first interface P1.
  • the second interface P2 generates the back electrode pulse pattern and feeds it to both the shift register 2 and the back electrodes of the liquid crystal display LCD.
  • the table according to FIG. 2 shows two examples of a layout of a display point for control in the multiplex method with a multiplex rate of 2: 1 or 4: 1.
  • the multiplex rate is indicated in the first column, the layouts of the segment and back electrodes are shown in the second and third columns, and in the remaining columns the back electrodes are assigned to the pixels of the corresponding segment electrodes : 1-multiplexing two back electrodes R1 and R2 and four segment electrodes SEG1, ..., SEG4 each with two pixels (a, b), (f, g), (e, c) and (d, DP) are listed, while In the 4: 1 multiplex method, four back electrodes R1, ..., R4 and two segment electrodes SEG1 and SEG2, each with four pixels (a, c, b, DP) and (f, e, g, d), are provided.
  • the segment data are transmitted serially into the shift register 2 as nibbles, ie as four contiguous bit positions, as can be seen from FIG. So every nibble contains the data that everyone has Driver stage to be generated segment electrode pulse trains corresponds, with each bit being assigned to a different back electrode.
  • a maximum of 64 segments can therefore be controlled via 16 driver stages. For example, if the number "3" is to be displayed, the first nibble has the shape "1110" and the second nibble has the shape "0011".
  • FIG. 3 shows the exemplary embodiment of the invention according to FIG. 1 in a detailed illustration of a block diagram.
  • the reference numeral 1 denotes a 4-bit microprocessor which contains a clock generator 11 for clock generation, for example with a clock frequency of 1 MHz.
  • the data output DA of this microprocessor 1 takes place via a bus line 10 to the first interface P1 and to the second interface P2 to the data inputs DE thereof, while via the clock output TA of the microprocessor 1 the clock pulses via a clock line 11 to the clock inputs TE of these two interfaces P1 and P2 be directed. Both the control data and the actual segment data are transmitted via this bus line 10.
  • the first interface P1 receives segment data, while the control data, for example the multiplex rate, receives the second interface P2. After corresponding processing of the segment data by the first interface P1, the processed data are fed to a shift register 2 via the line 12a. Likewise, the clock pulses controlling the shift register 2 are generated by the first interface P1 and fed to the shift register 2 via a clock line 13.
  • the shift register 2 is designed in accordance with that of FIG. 1, so it is a 16-stage 4-bit register and works as a ring register in that the data of the last stage are fed back via a line 12b to the first interface P1, so that this data is transferred to the first Can move the registrar in the presence of corresponding tax data.
  • control data are passed via a line 15 from the second interface P2 to the first interface P1.
  • the second interface P2 contains a decoder P22 for decoding the control data, which are then also passed to a pulse generator 3 in addition to the first interface P1.
  • this pulse generator 3 Depending on the software-selected multiplex rate, this pulse generator 3 generates a pulse sequence which corresponds to the level of the back electrode pulse sequence.
  • the level converter 7 connected downstream of the pulse generator 3 carries out the adaptation to the level corresponding to the back electrodes.
  • the outputs of this level converter 7 delivering the back electrode pulse trains BP1 to BP4 are connected via four lines 17 to the driver stages TB1 to TB4 controlling the back electrodes.
  • the back electrode pulse trains BP1 to BP4 generated by the level converter 7 are simultaneously fed to the shift register 2 via four further lines 17a.
  • the segment electrode pulse trains Corresponding data are stored in the register positions of the shift register 2 and are each supplied to the driver stages TS1 to TS16 of the segment electrodes via 16 lines 14, which are denoted by SS1, ..., SS16.
  • These segment driver stages TS1 to TS16 as well as the driver stages TB1 to TB4 for the back electrodes generate the segment electrode pulse trains as well as the back electrode pulse trains for direct control of the segment electrodes or the back electrodes.
  • these driver stages are supplied with a clock signal via line 19 which is generated by a clock generator 4, which at the same time contains a frequency divider stage.
  • the clock generator 4 is supplied by a crystal oscillator 5, which oscillates at a frequency of 32 kHz, via the two lines 18a and 18b.
  • the driver stages TS1, ..., TS16 or TB1, ..., TB4 are supplied with a voltage U reg which compensates for the temperature dependence of the liquid crystal display. This compensated voltage U reg is generated by a voltage source 6, this voltage reg also being supplied to a voltage doubler circuit 8 and a voltage tripler circuit 9.
  • the Doppler voltage U dop or Trippler voltage U trip generated by these units 8 and 9 is likewise supplied to the driver stages TS1 to TS16 and TB1 to TB4 via line 21 and 22, respectively. Furthermore, the tripler voltage U trip is also supplied to the level converter 7 and the shift register 2 via one of the lines 17a.
  • the autonomous data storage already described in connection with FIG. 1 also takes place during the "SLEEP" operating mode of the microprocessor 1, in which its clock generator 11 is switched off and the clock generator gate 4 with the frequency divider takes over the clock supply of the circuit. Thereafter, the data stored in the register positions of the shift register 2 remain, that is to say neither data are shifted into the shift register 2 during this time, nor are the data stored in the shift register 2 operating as a ring register pushed through.
  • the clock frequency of the second clock generator 4 only serves to switch the data in the register positions of the shift register 2 to its outputs SS1 to SS16. If the microprocessor now switches to "SLEEP" mode after data transmission, the data to be displayed are retained on the liquid crystal display LCD, while the power consumption is reduced by the lower frequency.
  • the voltage levels for the back electrode pulse trains are independent of the supply voltage because of the regulated voltage source 6. Furthermore, together with the temperature compensation, there is a constant contrast of the liquid crystal display LCD.
  • the exemplary embodiment according to FIG. 3 is implemented as an integrated circuit with the circuit elements drawn in the dash-dotted outline.
  • FIG. 4 shows a schematic structure of the first interface P1, which is constructed from a clock generation unit P11 and a multiplexer P12.
  • the clock generation unit P11 generates the clock pulses for the shift register 2, which are supplied to the latter via the line 13. Via the line 11, the clock pulses of the microprocessor and the pulse generation Unit P11 and the multiplexer P12 supplied. Both a reset pulse and the control signal "MASK" are fed to the multiplexer via lines 15.
  • the 4-bit data D1 to D4 present at the input DE are fed to the multiplexer P12 via four lines 10 and multiplexed on two lines 12a.
  • Two data signals DA1 and DA2 are thus available at the output DA and are supplied to the shift register 2 according to FIG. 6, this shift register being physically constructed as a 2-bit shift register.
  • the contents of the last stage of the shift register 2 are supplied to the multiplexer P12 via two lines 12b as data signals S16A1 and S16A2.
  • FIG. 5 shows the second interface P2 according to FIG. 3 in greater detail, reference symbols P22 and P23 denoting an input memory or the decoder.
  • the 4-bit control data C1 to C4 are supplied to the data input DE of the input memory P23 via the line 10.
  • the input memory P23 can be constructed, for example, from four D flip-flops.
  • the input data are fed to the decoder P22 via a line 15a.
  • the input memory P23 and the decoder P22 are supplied with the clock via a clock line 19.
  • the decoded control data are available at the output DA via the lines 15.
  • a reset signal R is sent via a first line, which is also forwarded to the input memory P23, the control signal "MASK” is generated on a second line, while control signals MUX1 to MUX4 are present on the remaining four lines, these control signals being the operating mode for determine the liquid crystal display LCD.
  • This can be a direct control of the liquid crystal display as well as one Control in the 2: 1, 3: 1 or 4: 1 multiplex method.
  • the control signal "MASK” is sent when a content of a register position of the shift register 2 does not have to be generated, but the old content can be shifted back into the shift register 2.
  • FIG. 6 shows an exemplary embodiment of shift register 2 according to FIG. 3.
  • This shift register 2 consists of double D flip-flops D1 to D16, each with data input D1 or D2.
  • the two data inputs of the first flip-flop D1 are supplied with the data signals DA1 and DA2 generated by the multiplexer via line 12a.
  • Two inverse clock signals are fed to the clock input TE of the flip-flops via two lines 13.
  • Each D flip-flop has four outputs Q1 to Q4, the outputs Q1 and Q2 being connected to the two data inputs D1 and D2 of the subsequent D flip-flop.
  • the two outputs Q1 and Q2 of the last D flip-flop D16 lead the data contents S16A1 and S16A2 to the last register position of the shift register 2 of the interface P1 according to FIG. 3 via the two lines 12b, thus realizing the ring structure of the shift register 2.
  • the outputs Q1 to Q4 of the D flip-flops are each connected to the input 1 of a level converter PW via a drain-source path of a field effect transistor.
  • the four field effect transistors belonging to a D flip-flop D1 to D16 are designated TD1 to TD16.
  • the gate electrodes of the field effect transistors of each transistor group TD1 to TD16 belonging to the same output of a D flip-flop are connected and are supplied with the back electrode pulse trains BP1 to BP4 generated by the level converter 7 via four lines 17a.
  • the level converters PW1 to PW16 are additionally supplied with the tripler voltage U trip .
  • the pulse patterns corresponding to the segment electrode pulse trains can be tapped from the outputs 0 of these level converters and are supplied to the driver stages TS1 to TS16 via the lines SS1 to SS16.
  • SLEEP programmable logic field
  • a temperature-compensated control voltage for generating the voltage levels for the back electrode and segment electrode pulse trains ensures independence from the supply voltage, which can therefore fluctuate between 1.2 V and 5 V without suffering a loss of contrast for the liquid crystal display.
  • circuit arrangement according to the invention can be easily expanded with respect to the segment electrodes to be controlled by increasing the number of stages of the shift register and, if necessary, adapting the software.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP90113043A 1989-07-21 1990-07-07 Circuit pour le fonctionnement d'un tableau indicateur à cristal liquide Expired - Lifetime EP0409030B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE3924061 1989-07-21
DE3924061 1989-07-21
DE4006243 1990-02-28
DE4006243A DE4006243A1 (de) 1989-07-21 1990-02-28 Schaltungsanordnung zum betrieb einer fluessigkristallanzeige

Publications (2)

Publication Number Publication Date
EP0409030A1 true EP0409030A1 (fr) 1991-01-23
EP0409030B1 EP0409030B1 (fr) 1994-03-02

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EP90113043A Expired - Lifetime EP0409030B1 (fr) 1989-07-21 1990-07-07 Circuit pour le fonctionnement d'un tableau indicateur à cristal liquide

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US (1) US5258754A (fr)
EP (1) EP0409030B1 (fr)
DE (2) DE4006243A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0529933A2 (fr) * 1991-08-23 1993-03-03 Motorola, Inc. Système de modification d'un flux de données, par exemple dans un contrôleur d'affichage à cristaux liquides
EP0852790A1 (fr) * 1996-06-28 1998-07-15 Microchip Technology Inc. Microcontroleur a horloge interne pour affichage a cristaux liquides
FR2774848A1 (fr) * 1998-02-12 1999-08-13 Jean Philippe Joseph Chevreau Dispositif permettant d'obtenir une nouvelle serie d'effets lumineux dans une console de jeux de lumiere

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5958247A (en) * 1994-03-28 1999-09-28 Siemens Aktiengesellschaft Method for disposing of a solution containing an organic acid
AUPM738894A0 (en) * 1994-08-11 1994-09-01 Dr Sala & Associates Pty Ltd Dotagraph - improved display system
US5874931A (en) * 1996-06-28 1999-02-23 Microchip Technology Incorporated Microcontroller with dual port ram for LCD display and sharing of slave ports
JPH10207438A (ja) * 1996-11-21 1998-08-07 Seiko Instr Inc 液晶装置
JP3982249B2 (ja) 2001-12-11 2007-09-26 株式会社日立製作所 表示装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2939553C2 (fr) * 1979-09-28 1982-11-11 Eurosil Gmbh, 8000 Muenchen, De
DE3234782A1 (de) * 1981-09-19 1983-04-14 Sharp K.K., Osaka Treiberschaltung fuer fluessigkristall- oder aehnliche anzeigevorrichtungen

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1339232A (en) * 1971-02-10 1973-11-28 Suwa Seikosha Kk Timepiece having a liquid crystal display
GB1432382A (en) * 1972-04-06 1976-04-14 Matsushita Electric Ind Co Ltd Method of driving a liquid crystal display device method of producing a drying filter
US4027305A (en) * 1973-08-09 1977-05-31 Canon Kabushiki Kaisha System for driving liquid crystal display device
US4127851A (en) * 1975-09-02 1978-11-28 U.S. Philips Corporation Device for displaying characters
US4257045A (en) * 1978-10-05 1981-03-17 Texas Instruments Incorporated RMS voltage control with variable duty cycle for matching different liquid crystal display materials
US4264963A (en) * 1979-06-08 1981-04-28 Texas Instruments Incorporated Static latches for storing display segment information
US4393379A (en) * 1980-12-31 1983-07-12 Berting John P Non-multiplexed LCD drive circuit
JPS5843494A (ja) * 1981-09-09 1983-03-14 シャープ株式会社 液晶表示装置の駆動装置
DE3508321A1 (de) * 1985-03-06 1986-09-11 CREATEC Gesellschaft für Elektrotechnik mbH, 1000 Berlin Programmierbare schaltung zur steuerung einer fluessigkristallanzeige

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2939553C2 (fr) * 1979-09-28 1982-11-11 Eurosil Gmbh, 8000 Muenchen, De
DE3234782A1 (de) * 1981-09-19 1983-04-14 Sharp K.K., Osaka Treiberschaltung fuer fluessigkristall- oder aehnliche anzeigevorrichtungen

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0529933A2 (fr) * 1991-08-23 1993-03-03 Motorola, Inc. Système de modification d'un flux de données, par exemple dans un contrôleur d'affichage à cristaux liquides
EP0529933A3 (en) * 1991-08-23 1993-11-18 Motorola Inc Data stream altering system, for example in a lcd driver
EP0852790A1 (fr) * 1996-06-28 1998-07-15 Microchip Technology Inc. Microcontroleur a horloge interne pour affichage a cristaux liquides
EP0852790A4 (fr) * 1996-06-28 1999-10-27 Microchip Tech Inc Microcontroleur a horloge interne pour affichage a cristaux liquides
FR2774848A1 (fr) * 1998-02-12 1999-08-13 Jean Philippe Joseph Chevreau Dispositif permettant d'obtenir une nouvelle serie d'effets lumineux dans une console de jeux de lumiere

Also Published As

Publication number Publication date
DE59004738D1 (de) 1994-04-07
US5258754A (en) 1993-11-02
EP0409030B1 (fr) 1994-03-02
DE4006243A1 (de) 1991-01-31
DE4006243C2 (fr) 1993-01-14

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