EP0398291B1 - Method for manufacturing a semiconductor integrated circuit - Google Patents

Method for manufacturing a semiconductor integrated circuit Download PDF

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Publication number
EP0398291B1
EP0398291B1 EP90109241A EP90109241A EP0398291B1 EP 0398291 B1 EP0398291 B1 EP 0398291B1 EP 90109241 A EP90109241 A EP 90109241A EP 90109241 A EP90109241 A EP 90109241A EP 0398291 B1 EP0398291 B1 EP 0398291B1
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EP
European Patent Office
Prior art keywords
region
integrated circuit
conductivity type
film
regions
Prior art date
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EP90109241A
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German (de)
English (en)
French (fr)
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EP0398291A2 (en
EP0398291A3 (en
Inventor
Nobuyuki Sekikawa
Tadayoshi Takada
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Definitions

  • the present invention relates to a method for manufacturing a semiconductor integrated circuit with a high degree of integration
  • Fig. 1 shows the configuration of the bipolar transistor disclosed in above literature.
  • This bipolar transistor comprises: a collector region 94 which is an island formed in an N-type epitaxial layer 91 from a lower isolating region 92 and an upper isolating region 93; a P-type base region 95 formed within the island; and an N + -type emitter region 96 formed within the base region 95.
  • This type of bipolar transistor is manufactured by a process comprising steps of:
  • the area occupied by the upper isolating region 93 of the epitaxial layer 91 is small compared to that obtained by other methods of manufacturing a semiconductor integrated circuit wherein the isolating regions are formed by diffusion from the top surface of the epitaxial layer only, and a comparatively high degree of integration is achieved.
  • the upper isolating region 93 when designing the depth of diffusion of the upper isolating region 93, for example, 10 ⁇ m, the upper isolating region 93 also extends to the same extent in the lateral direction, so that the spacing between the upper isolating region and each region must be over 12 ⁇ m which is a sum of the diffusion distance (10 ⁇ m) of the upper isolating region 93 and a spacing margin (2 ⁇ m). For this reason, even with the above described method of manufacturing a semiconductor integrated circuit, the high degree of integration desired today in a semiconductor integrated circuit is not adequately obtained.
  • the upper isolating region 93, the base region 95, and the collector contact region 97 formed in the fourth, sixth, and seventh steps are selectively doped through different SiO 2 films, there is concern that the positions which these regions occupy will deviate from the design values, as shown by the dotted lines in Fig. 1, because of the mask alignment required to form the doping windows in each SiO 2 film or for the subsequent etching. For this reason, the spacing of these regions must be designed to provide a preset allowance so that contact between these regions resulting from the diffusion treatment is avoided. This is a hindrance to high integration.
  • step 8 in which the respective contact windows in the SiO 2 films for the base region 95, the emitter region 96, and the collector contact region 97 are formed, the contact windows in the base region 95 and the emitter region 96 are completed prior to completely opening the window in the collector contact region 97 because the SiO 2 film for the base region 95 is comparatively thinner than the SiO 2 film for the collector contact region 97.
  • the problem exists that side etching will proceed even further and these contact windows will be expanded beyond the design value. Therefore, it is difficult to design an extremely small base region, and this is a hindrance to high integration in a semiconductor integrated circuit. Also, depending on the etchant used at this time, when the base region 95 and the emitter region 96 are etched the production yield is poor.
  • US-E-30282 discloses a double master mask process for fabricating semiconductor integrated circuits, wherein selectively etchable dielectric layers and ion implanted resistors are used to form dense integrated circuits, wherein the method of manufacturing such an integrated circuit comprises the steps of: forming a first insulating layer on the surface of a semiconductor layer; forming openings in the respective portions of the first insulating layer corresponding to isolation regions and first conductivity type integrated circuit element regions of the same conductivity type of the isolating regions to form doping windows for the respective regions; forming a first mask which shields the doping windows of the first integrated circuit element regions of the first isolating layer, and introducing a first conductivity type dopant into the semiconductor layer to form the isolating regions; introducing a dopant into the semiconductor layer through said windows for at least the first conductivity type integrated circuit element regions in the first insulating film after the first mask is removed, removing at least one part of the first insulating layer to make said layer thickness essentially uniform followed by the
  • the upper isolation region widens in the horizontal direction due to drive in. Further the isolation region is driven in the semiconductor body, which also broadens the width of the isolation region. Further at the time the isolation and base regions are formed, slippage occurs due to the photoetching of each region, and a margin is necessary. Therefore the size of such an IC chip cannot be greatly reduced.
  • US-A-4001869 discloses a method of forming a MOS-capacitor for integrated circuits.
  • the capacitor comprises a first electrode of P-type material, a thin layer of silicon oxide grown simultaneously with the oxide through which the resistor is implanted, and a metal electrode over the oxide dielectric layer.
  • EP-A-031107 discloses a process for fabricating a bipolar integrated circuit, wherein a bilaminate structure is used consisting of a silicon oxide layer and a phospho-silicate layer in which contact holes are formed for the transistor and capacitor forming regions of an integrated circuit.
  • JP-A-61134036 discloses a method of manufacturing a semiconductor IC, wherein an isolation region to the epitaxial layer an the substrate is formed by a diffusion from a high impurity concentration region formed in the substrate surface before epitaxial growth. Side etching occurs in the process according to this document, which causes the doping windows and/or the contact windows to become larger than the design value. This leads to an IC chip wherein a margin of 2 microns must be used to prevent slippage, which limits the size of a transistor element of an integrated circuit.
  • the method of manufacturing the semiconductor integrated circuit of the present invention eliminates the problems of side etching when the contact windows or dopant windows are formed or of etching the element regions. For this reason, it is possible to form element regions of the design size and a large margin of spacing for the isolating regions and the base region is unnecessary. Therefore, a high degree of integration is achieved. Because the position and size of the emitter region can also be formed to meet the design value, the base region can be made very small and therefore an even higher degree of integration can be achieved.
  • the positions at which are formed the upper isolating region and the element regions of the same conductive type as the upper isolating region are readily determined. It is therefore possible to make the spacing margin for the upper isolating region and the other regions extremely small. Also, by means of this embodiment in which the number of masking steps is reduced, problems of contamination of and damage to the semiconductor substrate, and the like in the manufacturing stages are eliminated.
  • the present invention wherein doping with a second-conductive-type of dopant is performed through the second insulating film and the second mask, has the advantage that some slippage between the masking patterns of the second insulating film and the second mask is tolerated. Specifically, the dopant which is inserted through the opening in the second mask finally reaches the surface of the semiconductor layer according to the second insulating layer mask pattern.
  • the second mask therefore is adequate if it has the function of shielding the element regions which do not require doping.
  • the element regions of second-conductive-type can be formed with high positional accuracy without precise mask alignment.
  • the distribution of the dopant in the upper isolating region retrogrades directly after the ion implantation. It is therefore possible to reduce the width of the upper isolating region on the surface of the epitaxial layer, which reaches its maximum width in the subsequent diffusion step, and a semiconductor integrated circuit with a high degree of integration is achieved.
  • the upper and lower isolating regions are linked by means of a diffusion step at a low temperature over a comparatively short time.
  • the width of the upper isolating region on the surface of the epitaxial layer can also be reduced, and, accordingly, a semiconductor integrated circuit with a high degree of integration is achieved.
  • the upper and lower isolating regions are formed by different diffusion processes
  • the lateral diffusion of the upper isolating region can be restrained, and it is possible to curtail the width of the exclusive surface area of the upper isolating region which affects the degree of integration of the semiconductor integrated circuit.
  • the lower isolating region is designed with a large cross section which is formed by a longer period of diffusion than that used for the upper isolating region, a small amount of slippage of the mask can be tolerated during the formation of the upper isolating region, the upper isolating region and the lower isolating region are easily linked, and a complete isolation of junction is obtained.
  • Fig. 12 shows a P-type semiconductor substrate 12; an N-type epitaxial layer 16 formed on the semiconductor substrate 12; a plurality of N + -type buried layers 14 formed by diffusion in the boundary region of the semiconductor substrate 12 and the N-type epitaxial layer 16; and a plurality of isolating regions 18, which reach the surface of the epitaxial layer 16 from the top of the semiconductor substrate 12 as well as the configuration of each type of integrated circuit element (later discussed) within the epitaxial layer 16.
  • the isolating regions 18 are obtained by diffusing upward a P-type lower isolating region 20 to a depth of a little more than half the thickness of the epitaxial layer 16 wherein the P-type lower isolating region 20 has been formed on the surface of the semiconductor substrate 12 prior to growing the epitaxial layer 16, and by diffusing downward a P-type upper isolating region 22 to reach the lower isolating region 20 from the surface of the epitaxial layer 16.
  • the isolating regions 18 are formed to enclose the buried layer 14, and a plurality of electrically isolated islands is formed by the isolating regions 18.
  • common reference numbers have been used in the drawings preceding and subsequent to the diffusion of the lower and upper isolating regions 20, 22.
  • a transistor 54, a MOS capacitive element 68, and a diffusion resistance element 74 are also shown in these drawings as examples of the integrated circuit elements.
  • the transistor 54 is seen to comprise a collector region 56, which is the epitaxial region itself, a base region 60, and an emitter region 64 within a first island formed by the isolating region 18.
  • a MOS capacitive element 68 comprising a lower layer electrode region 69, a dielectric layer 70 formed on the upper layer of the lower layer electrode region 69, and an upper layer electrode 71 formed on the upper layer of the lower layer electrode region 69 is shown.
  • a diffused resistance region 74 is shown comprising a diffused resistance region 75 formed on the surface of the epitaxial layer 16 and two contact regions 76 at each end of the diffused resistance region 75.
  • the diffused regions of the transistor 54, the MOS capacitive element 68, and the diffused resistance region 74 have essentially the same thickness, and, accordingly, they are covered with an SiO 2 film 34 with essentially the same thickness, which is a special feature of the present invention.
  • a semiconductor substrate 12 which functions providing necessary strength in the manufacturing process
  • a P-type silicon semiconductor with impurity concentration of about 10 15 atom/cm 3 , and with a thickness of about 200 ⁇ m is used as a semiconductor substrate 12 which functions providing necessary strength in the manufacturing process.
  • An SiO 2 film is formed on the surface of the semiconductor substrate 12 by a commonly known thermal oxidation process, and a specified area of this SiO 2 film is opened by means of a commonly known photolithography (omitted from the drawings). Then the semiconductor substrate 12 is doped through the openings with antimony or arsenic, which are N-type dopants, to form the N + -type buried layers 14.
  • antimony or arsenic which are N-type dopants
  • FIG. 2 shows the cross sectional configuration of the semiconductor substrate 12 from which the SiO 2 film on the surface have been removed after the above process and on which again an SiO 2 film is newly formed.
  • the layer which is subsequently subjected to a diffusion process is expressed as a buried layer.
  • the same representation and reference numbers are hereinafter used for the layer immediately after doping, and for the layer which is subsequently subjected to diffusion.
  • an specified area of SiO 2 film which is newly formed is opened by photolithography in a different position from that of the previous SiO 2 film (omitted from the drawings).
  • boron which is a P-type impurity, is introduced to dope the semiconductor substrate 12 to form a P + -type lower isolating region 20 (see Fig. 3).
  • the lower isolating region 20 can also be doped with boron by the ion implantation method.
  • an N-type epitaxial layer 16 with a specific resistance of 0.1 to 5 ⁇ .cm is grown to a thickness of about 7 ⁇ m on the semiconductor substrate 12 by a commonly known vapor phase deposition method.
  • the semiconductor substrate 12 combined with a region or layer formed by the subsequent step, for example, the epitaxial layer 16 are referred to as the semiconductor substrate 12.
  • the semiconductor substrate 12 is exposed to high temperatures, and the dopant which has previously been introduced to dope the semiconductor substrate 12 is diffused to a certain extent at that time.
  • the semiconductor substrate 12 is subjected to thermal oxidation for several hours at a temperature of about 1,000°C to form an SiO 2 film 26 on the surface of the epitaxial layer 16, and maintained at about 1,000°C for an additional 2 hours approximately.
  • the lower isolating region 20 is diffused upward to a depth of a little more than half the thickness of the epitaxial layer 16 (about 5 ⁇ m from the substrate surface).
  • the present invention is characterized by this step in which the lower isolating region 20 is diffused in the upward direction to a depth of a little more than half the thickness of the epitaxial layer 16.
  • the lower isolating region 20 is also diffused to the same extent in the lateral direction (on the drawing), if the width of the doping window for the lower isolating region 20 is, for example, 4 ⁇ m, the lower isolating region 20 reaches a maximum width of about 14 ⁇ m in subsequent steps. Accordingly, it is effective for improving the circuit integration that the maximum thickness of the lower isolating region 20 is restrained by forming the epitaxial layer 16 as a thin layer.
  • the SiO 2 film 26 on the surface of the epitaxial layer 16 is further grown to a thickness of several thousand angstroms, and is used as a mask for subsequent selective diffusion.
  • This mask may also be the SiO 2 film which may newly be formed by the CVD process.
  • an opening is created in a portion of the SiO 2 film 26 for the lower layer electrode region 69 of the MOS capacitive element 68 and, for example, phosphorous glass (omitted from the drawing) is formed over the entire surface of the semiconductor substrate 12.
  • phosphorous glass is diffused from the above-mentioned opening into the epitaxial layer 16 to form an N + -type lower layer electrode region 69.
  • the phosphorous glass is then removed with a specified etchant, and the heat treatment is again performed to diffuse the phosphorus to a specified depth (See Fig. 5).
  • each potion of the SiO 2 film 26 for the upper isolating region 22, the base region 60, and the diffused resistance region 75 are opened by means of photolithography using a positive-type resist film and dry etching, to form the respective doping windows 27, 28, and 29.
  • the SiO 2 film 26 is a special feature of the present invention, and, compared to other SiO 2 films of the present invention, in particular, to those used in the conventional manufacturing method, it is commonly used in subsequent steps for a longer time.
  • the exposed epitaxial layer 16 is oxidized and dummy oxidation film 32 is formed to reduce damage to the epitaxial layer 16 from the subsequent ion implantation steps and to implant the impurity ions uniformly. (See Fig. 6).
  • a resist film 40 which is capable of blocking ion implantation is formed on the SiO 2 film 26 of the previous step, an opening is made in the upper section only of the upper isolating region 22, and boron is introduced through a doping window 41 to form a P + -type upper isolating region 22.
  • the present invention in which ion implantation is carried out through the SiO 2 film 26 and the resist film 40 has the advantage that slippage of the mask patterns for the SiO 2 film 26 and the resist film 40 can be tolerated.
  • the ions implanted from the doping window 41 of the resist film 40 are finally implanted in the surface of the epitaxial layer 16 according to the mask pattern of the SiO 2 film 26.
  • the resist layer 40 is adequate if it has the function of shielding the doping windows 28, 29 of the base region 60 and the diffused resistance region 75 respectively. A precise mask alignment is unnecessary. Accordingly, it is desirable that the doping window 41 of the resist film 40 be formed slightly larger than the doping window 27 in the lower section of SiO 2 film 26, as in the resist film 40 shown in Fig. 7.
  • the upper isolating region 22 reaches the lower isolating region 20, and the both regions are linked to form the isolating region 18 as shown in Fig. 8.
  • the isolating region 18, the base region 60, and the diffused resistance region 75 are formed in this way, retrogradation occurs in the dopant distribution in the upper isolating region 22 directly after ion implantation.
  • the width of the upper isolating region 22 on the epitaxial layer 16 which is at its greatest width through the subsequent diffusion step can be narrowed. A high degree of integration is achieved in the semiconductor integrated circuit 10.
  • the upper isolating region 22 and the lower isolating region 20 can be linked through a comparatively short-time, low-temperature diffusion step, whereby it is also possible to narrow the width of the upper isolating region 22 on the epitaxial layer 16, and, accordingly, to achieve a high degree of integration in the semiconductor integrated circuit 10.
  • the diffusion conditions can optionally be designed so as to diffuse the lower isolating region 20 deeply and the upper isolating region 22 shallowly.
  • the lateral diffusion of the upper isolating region 22 can be suppressed, and the width of the exclusive surface area of the upper isolating region 22 which directly affects the degree of integration of the semiconductor integrated circuit 10 can greatly be curtailed.
  • the lower isolating region 20 which is formed by a longer period of diffusion than that used for the upper isolating region 22 is designed with a large cross section, a small amount of slippage of the mask can be tolerated during the period of formation of the upper isolating region 22.
  • the upper isolating region 22 and the lower isolating region 20 are easily linked, and a complete isolation of junction is obtained.
  • the positioning of the doping windows 27, 28, 29 is determined by a single mask, that is, the SiO 2 film 26. Because the positions where the upper isolating region 22 and either the base region 60 or the diffused resistance region 75 are formed is primarily determined, the spacing margin for the upper isolating region 22 and either the base region 60 or the diffused resistance region 75 can be drastically reduced.
  • the distance for lateral diffusion of the upper isolating region 22 is usually 0.8 times that for vertical diffusion, so that the respective intervals between the upper isolating region 22 and the regions for the various integrated circuit elements must be rationally designed at 0.8 times or greater the vertical diffusion distance of the upper isolating region 22.
  • a new resist film 42 is formed on the SiO 2 film 26 and openings are formed by photolithography in respective areas corresponding to a base contact region 61, a diffused resistance element 74, and a pair of contact regions 76, to form the respective doping windows 43, 44, 45.
  • boron (B) ions are implanted in the epitaxial layer 16 through the resist film 42 and the SiO 2 film 26 to form a P-type base contact region 61 and two P-type contact regions 76. (See Fig. 9).
  • the SiO 2 film 26 on the surface of the epitaxial layer 16 is completely removed and a new SiO 2 film 34 is formed.
  • the SiO 2 film 34 is formed as two layers - an non-doped SiO 2 film and a phosphorous (P) doped SiO 2 film (omitted from the drawing) so as to be capable of gettering Na ions.
  • the SiO 2 film 34 may be formed by first etching the SiO 2 film 26 to substantially a uniform thickness of about 1,000 angstroms and by laminating a non-doped SiO 2 film and a phosphorous-doped SiO 2 film to a depth of about several thousand angstroms respectively on the SiO 2 film 26 etched.
  • This SiO 2 film 34 with a uniform thickness of the present invention has a distinctive feature because of the reason that will be clarified by an explanation of the step related to Fig. 11.
  • an opening is made in a portion of the SiO 2 film 34 for a dielectric layer 70 of a MOS capacitive element 68 by means of photolithography using a negative-type photoresist and wet etching.
  • a silicon nitride film of several hundred angstroms is formed on the surface of the semiconductor substrate 12 and etched by a chemical dry-etching method to form the dielectric layer 70 of the shape shown in Fig. 10.
  • the semiconductor substrate 12 is heat-treated under specified conditions, and the base region 60, the diffused resistance region 75, and their respective contact regions 61, 76 are subjected to diffusion.
  • the resulting shapes of the base region 60, the diffused resistance diffusion 75, and their respective contact regions 61, 76, following the foregoing diffusion treatment, are shown in Fig. 11.
  • openings are formed by photolithography in the respective portions of the SiO 2 film 34 for a collector contact region 57, the base contact region 61, the emitter contact region 64, the contact region 72 of the lower layer electrode region 69, and the two contact regions 76 of the diffused resistance region 75, to form the doping windows and/or contact windows 35, 36, 37, 38, 39 simultaneously.
  • a photoresist film 50 is formed so as to expose the collector contact region 57, the emitter region 64, and the contact region 72 of the lower layer electrode region 69.
  • arsenic (As) ions are then implanted in the epitaxial layer 16 to selectively form an N + -type collector contact region 57, emitter region 64, and contact region 72 of the lower layer electrode region 69.
  • the most distinctive characteristic of the present invention is the SiO 2 film 34 of this step.
  • the film thicknesses of the doping windows and/or contact windows formed in the SiO 2 film differ according to the location, as shown by the reference number 26 in Fig. 9.
  • side etching proceeds in the comparatively thin portions of the SiO 2 film for the base contact region, the emitter region, and two contact regions 76 respectively.
  • the emitter region itself will be etched, depending on the etching process used.
  • the thickness of the entire SiO 2 film 34 is essentially uniform, the etching of a portion of the SiO 2 film 34 for the collector contact region 57, and the etching of the respective portions of the SiO 2 film 34 for the base contact region 61, the emitter region 64, and the two contact regions 76 of the diffused resistance region 75 are completed simultaneously. Therefore, the problem of side etching which causes the doping windows and/or the contact windows 36, 37, 39 to become larger than the design value is avoided.
  • the base region 60 can be made very small because the size of the emitter region 64 meets the design specifications. This gives the advantage of a high degree of integration.
  • the semiconductor substrate 12 is heat-treated after the removal of the photoresist film 50 on the SiO 2 film 34, and downward diffusion of the emitter region 64 takes place.
  • a slight SiO 2 film is newly formed at the doping windows, which is removed by light etching, and a plurality of aluminum electrodes 58, 62, 65 is formed at the collector contact region 57, the base contact region 61, and the emitter region 64, of the transistor 54 respectively; an aluminum electrode 73 at a contact region 72 of the lower layer electrode region 69 of the MOS capacitive element 68 and an aluminum electrode 71 as an upper layer electrode of the MOS capacitive element 68 are formed; and an aluminum electrode 77 is formed at the two contact regions 76 of the diffused resistance element 74.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP90109241A 1989-05-19 1990-05-16 Method for manufacturing a semiconductor integrated circuit Expired - Lifetime EP0398291B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP12731989 1989-05-19
JP1127319A JPH06101540B2 (ja) 1989-05-19 1989-05-19 半導体集積回路の製造方法
JP127319/89 1989-05-19

Publications (3)

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EP0398291A2 EP0398291A2 (en) 1990-11-22
EP0398291A3 EP0398291A3 (en) 1992-12-23
EP0398291B1 true EP0398291B1 (en) 2000-04-26

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EP90109241A Expired - Lifetime EP0398291B1 (en) 1989-05-19 1990-05-16 Method for manufacturing a semiconductor integrated circuit

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US (1) US5023195A (ja)
EP (1) EP0398291B1 (ja)
JP (1) JPH06101540B2 (ja)
DE (1) DE69033515T2 (ja)

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US5254486A (en) * 1992-02-21 1993-10-19 Micrel, Incorporated Method for forming PNP and NPN bipolar transistors in the same substrate
JP2586395B2 (ja) * 1993-12-13 1997-02-26 日本電気株式会社 半導体装置の製造方法
EP0778621B1 (en) * 1995-12-06 2008-08-13 Sony Corporation Semiconductor device comprising a photodiode and a bipolar element, and method of fabrication
US5679593A (en) 1996-02-01 1997-10-21 Micron Technology, Inc. Method of fabricating a high resistance integrated circuit resistor
US20060148188A1 (en) * 2005-01-05 2006-07-06 Bcd Semiconductor Manufacturing Limited Fabrication method for bipolar integrated circuits

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DE69033515T2 (de) 2000-08-31
EP0398291A2 (en) 1990-11-22
DE69033515D1 (de) 2000-05-31
US5023195A (en) 1991-06-11
JPH02305464A (ja) 1990-12-19
EP0398291A3 (en) 1992-12-23

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