EP0394216B1 - Method for the control and regulation of a combustion engine - Google Patents

Abstract

A method for the open-loop and closed-loop control of an internal combustion engine (1) in which a digital binary output signal (b) is calculated in a computing device as a function of operating variable signals, such as for example the engine speed (n), the accelerator position, the engine temperature etc., said calculated binary signal is converted into an actuation signal (s) which consists of pulses of a constant amplitude, the overall duration of the actuation signal within a clock period being proportional to the value of the binary signal and this actuation signal being used to control an electromechanical actuator. In this process, the actuation signal is divided up within each clock period depending on the value of the binary signal (b) into individual pulses whose overall duration is proportional to the value of the binary signal (b) and the individual pulses are distributed essentially evenly within each clock period. In addition, a device for carrying out the method is disclosed. <IMAGE>

Description

The invention relates to a method for controlling and regulating an internal combustion engine according to the preamble of claim 1 and to an electronic regulating and control device for internal combustion engines according to the preamble of claim 3.

In the electronic control of a diesel engine, a controller delivers a digital output signal. Depending on this signal, an electromechanical drive for the actuator e.g. the injection pump or pump nozzles. A pulse width modulator with a downstream low-pass filter is then advantageously used as the digital-to-analog converter. It must be taken into account here that, due to its electrical (inductance) and mechanical (mass) properties, the drive exhibits a more or less pronounced low-pass behavior that plays a role in the dimensioning of the low-pass filter. If the control signal is insufficiently filtered, the actuator may in any case be mechanically unsteady, namely an oscillating movement with the clock frequency of the control signal. The effort required for the low-pass filter, particularly at lower clock frequencies, is to be regarded as a disadvantage.

The use of pulse-width modulated signals for controlling actuators for the injection quantity is evident, for example, from DE-A-33 11 351, in which case the actuator is controlled directly by the pulse-width-modulated signals. The applicant's DE-A-37 30 443 also shows the use of a pulse-width-modulated signal, but this signal is used here as a command variable for a servo circuit for the actuator. The term "control signal for controlling an electromechanical actuator" is thus to be understood in the sense that it includes direct control as well as control of a servo circuit for the actuator.

Document JP-A-59 120 776 (abstract) discloses a speed-dependent control of a fuel pump, which is carried out in such a way that a speed-dependent pulse train is fed to a monostable multivibrator, which forms a speed-dependent pulse from the pulse train, the individual pulses of which have a constant duration. This pulse is fed to a fuel pump. Accordingly, the pulse duty factor increases with increasing speed and, on average, more electrical energy is supplied to the fuel pump. For an actual regulation e.g. Such a control is unsuitable in the sense of the documents mentioned above.

A pulse width modulator for converting a dual digital value into a pulse width modulated signal, which is implemented using a microcomputer, can, for example from the company publication "Embedded Controller Handbook", Intel, Order Number 21 09 18-005, 1987. Here, the digital value is fed to a register, at whose output the value is, for example, 8 digits (in the dual system). A clock frequency is fed to a counter input, the 8-digit output of which is also compared in a comparator with the previously mentioned value. The output of the comparator, which checks for equality, is fed to the reset input of a flip-flop, the set input of which receives the overflow signal from the counter. A pulse width modulated signal is then present at the Q output of the flip-flop. This signal has a pulse within each cycle, the width or length of which increases with increasing size of the value mentioned. With a register value 0 the width of the pulse disappears, with a register value 255 the width almost corresponds to the period T _o .

In this known solution, the relative amplitude of the voltage fluctuations is almost 25% regardless of the number of bits with a filter time constant τ = T _o and with a pulse duty factor for the pulses within each clock of 1: 1. As the duty cycle increases or decreases, the relative amplitude of the voltage fluctuations decreases, but it is still around 10% at a duty cycle of 1: 5 or 5: 1. In order to reduce the relative voltage fluctuations, one must therefore choose larger filter time constants, which results in a corresponding deterioration in the dynamics, which has an extremely unfavorable effect on the driving behavior of the vehicle.

It should be noted here that the terms "dual code" and "binary code" are used in accordance with German-language literature (e.g. U. Tietze, Ch. Schenk: "semiconductor circuit technology", Springer-Verlag, Berlin 1983).

The invention has set itself the goal of converting the pulse instead of the usual pulse width modulation To create output signals of the computing device in a control signal for an electromechanical actuator, which has the same effort, in particular with respect to the filtering, significantly lower relative voltage fluctuations of the analog signal. This goal can be achieved with a method according to the characterizing part of claim 1 or with a device according to the characterizing part of claim 3.

The invention offers the advantage that, with the same circuit complexity as according to the prior art, a significant reduction in the ripple of the output signal is obtained. With the same demands on the residual ripple, the outlay for a downstream low-pass filter can be kept considerably lower than according to the prior art. The term "downstream low-pass filter" here also includes a consumer with a low-pass character, which has already been explained above.

Further features are characterized in the dependent subclaims.

The invention together with other advantages is explained in more detail below using exemplary embodiments which are illustrated in the drawing. 1 shows an exemplary embodiment of a device according to the invention in a block diagram, FIG. 2 shows another exemplary embodiment of a device according to the invention and FIGS. 3a and b show the form of the output signal as a function of the preset signal in a device in time diagrams within one cycle according to the prior art (Fig. 3a) or in a device according to the invention (Fig. 3b).

Fig. 1 shows schematically a diesel engine 1 with an injection pump 2, the control rod 3 determining the amount of fuel supplied is adjustable by means of an electromechanical drive 4. A computing device 5 calculates from operating variable signals of the engine 1 and also the Vehicle output signal b, which is the basis for the adjustment of the control rod 3.

Essential operating variables as input variables of the computing device 5 are the accelerator pedal position, which generates a corresponding signal f via a transmitter 7 and the speed of the engine 1, a speed signal n being supplied by a speed transmitter 8 to the computing device 5. In Fig. 1 further sensors 9 are indicated schematically, the additional operating quantity signals, e.g. in terms of engine temperature, air pressure, fuel temperature etc.

The output signal b of the computing device 5 and any further output signals b ', b˝ is in digital, dual-coded form and is fed to a register 10, from where it has 8 digits as word B to the inputs B₀ to B₇ of an 8-bit comparator 11 arrives. Such a comparator can be implemented, for example, with logic modules MM54C85, 4-bit magnitude comparator from National Semiconducter. The company publication "Logic Databook, Volume 1, National Semiconductor Corporation", 1984 shows the logical structure of such modules and describes their interconnection to word lengths that are greater than 4 bits.

Returning to Fig. 1, it can be said that the output signal b or the word B is supplied to the comparator 11 with the correct position, i.e. the output with the lowest position value (LSB = least significant bit) of the register is connected to the input B₀ of the comparator 11.

There is also a dual counter 12 which is supplied with a counting cycle f 1 of the period T 1. This counting clock expediently comes from a clock generator, which is required by the computing device 5 and is not shown in detail. An 8-digit output of the counter 12 is connected to the second input of the comparator 11, but here the counter output is connected to the comparator input in such a way that the output MSB (most significant bit) of the counter 12 corresponds to the Input A₀ of the comparator 11 with the lowest position value (LSB) corresponds, ie the order of the positions is reversed when wiring, or, in other words, the counter signal a is fed to the comparator 11 in inverted form.

At the output of the comparator 11, which checks whether the word A at the inputs A₀ to A₇ is smaller than the word B at the inputs B₀ to B₇, a drive signal of the period T₀ occurs, which consists of individual pulses within each period, the Total length within each period T₀ is proportional to the value of the output signal b of the computing device 5. For a 4-bit comparator, this is illustrated in FIG. 3b, with the previously customary pulse width modulation being compared in FIG. 3a. The default value B is numbered 0 to 15 on the left.

Period T₀ with counter clock T₁ are related to each other over the word length n of the comparator via T₀ = T₁.2 ⁿ . In Fig. 1 the word length is shown with 8 bits, in Fig. 3 with 4 bits. In practice, however, word lengths of 8 to 16 bits or more will be used.

The output of the comparator 11 can be followed by a D flip-flop 13 which is clock-edge-controlled by the counter clock f 1 and frees the control signal from switching spikes which arise in the comparator 11. An inverter is upstream of the clock input of the flip-flop 13. The elimination of switching spikes is particularly advisable at higher clock frequencies, when run times in the comparator lead to spikes of a clearly noticeable length, which could cause the predefined signal to be falsified.

The control signal s is fed to the electromechanical drive 4 via a simple low-pass filter 14 and an output stage 15.

Fig. 2 shows an implementation example of a 4-bit comparator using conventional gate modules and Fig. 3b, as already mentioned, the associated control signal for the sixteen possible default values. From Fig. 3b the person skilled in the art already sees the significant improvement in the ripple of a voltage obtained after filtering. Of course, this improvement is also shown mathematically and experimentally and is given below with the aid of a comparison for the worst case of the pulse duty factor (eg number 8 in FIG. 3a).

In a pulse width modulator according to the prior art, the relative voltage fluctuations with a filter time constant τ = T _{o are} approximately 25%, regardless of the number of bits used.

In the invention, these voltage fluctuations are at the same filter time constant
4 bits below 12%
10 bits under 0.2%
16 bits under 40.10⁻⁶

It can be seen from this that the filtering effort is drastically reduced when the invention is used. In view of the low-pass property inherent in electromechanical actuators, a low-pass filter can in many cases be dispensed with entirely.

Actuators that are to be controlled based on the output signal b of the computing device 5 are, in particular, the control rod of an injection pump, as shown in FIG. 1. But it can also be actuators for adjusting the injection timing, the amount of air, an exhaust gas recirculation valve, a throttle valve and the like. What is indicated by signals b ', b˝ in Fig. 1.

A particular advantage associated with the invention can be seen in the rapid and error-free response to a change in the default value, which is not only given by the more favorable filter dimensioning. you alleviate within the period T _o the default value B to a particularly smaller value, then a reaction in the desired direction is shown in almost all cases with the structure according to the invention even before the end of the same period. In the case of the prior art, in the worst case, if the default value changes during the period, either so-called outliers (one-time output of 100%) occur, or the desired change does not occur until the next period T _o . Such misconduct can have fatal consequences for driving the motor vehicle.

If it is mentioned in the present application that the total duration of the control signal s is essentially proportional to the value of the dual or binary output signal b, this should not mean that a direct component (offset) is excluded.

Claims (5)

1. Method for controlling and regulating an internal combustion engine, where a digital, binary output signal is calculated in a computer in dependence upon the signals of the operating values, such as for example the rotational speed, the accelator pedal position, the engine temperature etc. and this.calculated binary signal is converted into a control signal, which comprises pulses of constant level, and the total duration of the control signal within a predetermined fixed timing period is proportional to the value of the binary signal and this control signal is used to control an electro-magnetic adjusting member, characterised in that the control signal within each timing period is, depending on the value of the binary signal (b), divided into individual pulses, and the summation of the duration of the individual pulses within the timing period is proportional to the value of the binary signal (b) and the individual pulses are divided substantially evenly within each timing period.
2. Method according to claim 1, characterised in that the calculated binary signal (b) is represented as an n-bit preceding binary signal, the timing pulses for producing the durations of the individual pulses are counted binary, in order to provide an n-bit binary counter signal (a), which is compared using a comparator with the preceding binary signal and n > 1 [apparent omission in Germann text] for the purpose of comparison, the binary counter signal (a) is fed to the comparator in a reverse sequence according to its binary bits and a comparison is carried out as to whether the numerical value, according to the reverse sequence of the binary bits, of the binary counter signal is smaller than the numerical value of the preceding binary signal.
3. Electronic regulating and controlling device for internal combustion engines for carrying out the method in accordance with one of claims 1 to 2, having a computer 5, to which is fed the rotational speed signal (n) of a rotational speed sensor (8) and further signals of operating values determined by means of sensors and, for the purpose of outputting an n-bit preceding binary signal (b) calculated from the operating values, the computer (5) is fitted with an n-bit binary counter which is fed a timing signal (f1) for the purpose of forming an n-bit binary counter signal (a) and is also fitted with an n-bit comparator (11) which, for the purpose of comparing the binary counter signal (a) is fed with the n-bit preceding binary signal (b) and whose output signal (s) is used for controlling an electro-mechanical adjusting member (4), and n > [apparent omission in German text] characterised in that the binary counter signal (a) and the preceding binary signal (b) are fed to the comparator (11) in such a way that the binary counter signal (a) with respect to the comparator input (b) is used in the reverse sequence according to its binary bits.
4. Device according to claim 3, characterised in that the comparator (11) is fitted, for the purpose of outputting an output signal, should the respective value of the pre-set binary signal (b) be larger than the corresponding value of the binary counter signal (a), which is used in the reverse sequence according to its binary places.
5. Device according to claim 3 or 4, characterised in that, a pulse edge controlled D-flip-flop (13) is connected downstream of the comparator (11).

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