Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
  • H01L27/14625—Optical elements or arrangements associated with the device
  • H01L27/14627—Microlenses
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
  • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/02—Details
  • H01L31/0232—Optical elements or arrangements associated with the device
  • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors

Definitions

• the present invention relates to making lens arrays in Si0 2 for light sensitive devices.
• Image sensing devices made up of an array of laterally spaced sensors are well known and can take a variety of forms.
• the array can be viewed as being made up of a number of laterally offset regions, commonly referred to as pixels or sensing elements.
• the art has recognized that sensing advantages can be realized by forming a lens array having convex lens surface for each pixel.
• This object is achieved in a method of forming on a light sensitive device defining a plurality of sensing elements, a lens array having a separate lens for each sensing element, comprising the steps of: a) providing a spacer and planarization layer on the device over each sensing element; b) depositing a layer of hard dielectric material on the spacer and planarization layer; c) applying a layer of photoresist material and patterning and flowing the photoresist material in the shape of the desired lens array on the hard dielectric material layer; and d) plasma etching the photoresist material which etches the hard dielectric material at a similar rate as it etches the photoresist material until the lens array is etched into the layer of hard dielectric material.
• FIG. 1 is a plan view of a multipixel semiconductor array
• FIG. 2 is a sectional of a single sensing element just after a photoresist layer has been patterned in the process of forming the lens array of FIG. 3;
• FIG. 3 is a sectional view of the sensing element of FIG. 2 after the lens array has been formed.
• FIG. 1 a multipixel semiconductor array 10 is shown formed by a plurality of laterally spaced photodiodes 14 on a substrate.
• the semiconductor array can be viewed as being made up of a plurality of sensing elements or pixels 12, each having a photodiode sensor 14 centrally positioned adjacent its upper surface and each peripherally defined by linear polygonal boundaries indicated by dashed lines 18.
• FIG. 2 where we see in cross—section a sensing element or pixel 12 of the array of FIG. 1 while in the process of forming the lens array of this invention.
• a conductive layer 27 covers the lower major surface.
• the semiconductive substrate has an N conductivity type region 29 and a P conductivity type well 31 formed by diffusion from the upper major surface 23.
• a photodiode is formed centrally in the pixel by an N diffusion 33 from the upper major surface. The function of the photodiode is to produce electrons in proportion to the amount of light received on exposure.
• the electrons are supplied to an adjacent charge coupled device.
• a shallow N conductivity type region 35 is located adjacent the upper major surface.
• the buried channel thus formed extends from the photodiode to an adjacent CCD.
• P conductivity type zones 37 referred to as channel stops, isolate the photodiode and the adjacent CCD from other adjacent surface structures.
• a gate electrode 39 typically formed of polycrystalline silicon, is shown overlying a gate insulator 36 which overlies the upper surface of the semiconductive substrate. Since polycrystalline silicon is transparent, a light shield 41, typically formed of aluminum, overlies the gate electrode. A transparent insulator 43 is shown overlying the entire upper major surface of the semiconductive substrate and also separating the gate electrodes from the light shields. Typically the insulator is silicon dioxide, with a surface laydown of passivant, such as borosilicate glass, being common. Although shown as unit, the insulator is typically formed in several successive fabrication steps.
• a transparent insulative material 45 commonly referred to as a planarizing material, is positioned to provide a smooth surface 47.
• a filter 49 having an element 51, such as an additive primary filter element, coextensive with the pixel or sensor element boundaries.
• a spacer and planarization layer 53 is formed on filter 49. The purpose of layer 53 is to offset the lens from the photodiode to maximize collection of light in photodiode or to permit the use of a smaller photodiode with the same collection efficiency.
• the layer 53 of course, has to be transparent and must permit the hard, transparent layer 54 to be formed on it.
• a layer 54 is deposited.
• Layer 54 is formed of Si0 2 or some other hard transparent dielectric.
• a layer of photoresist is then deposited.
• a lens array is formed in photoresist layer 54 in the manner described in detail in U.S. Patent No. 4,694,185.
• a photoresist layer is deposited by spin coating.
• the resist is patterned by photolitho ⁇ graphy.
• the resist is flowed to form a convex lens-like upper surface 59.
• U.S. Patent No. 4,694,185 described in detail a patterning and flowing of photoresist to form a lens array.
• the lens profile of the photoresist is transferred to the Si0 2 layer 54 as shown in FIG. 3. More specifically, the lens shape array in photoresist is transferred to the Si0 2 using a plasma etch which etches Si0 2 at the same rate as the resist. This etch is continued until all resist is removed.
• FIG. 3 shows the Si0 2 in the shape of the photoresist after this etch.
• a plasma etch with the same etch rates (1:1) for a dielectric (phosphorus-doped Si0 2 ) and a Novalak based photoresist is formed from gases C 2 F, , 0 2 and He. They are in a 4:1:1 volume ratio.
• Such gas has been flowed through a single wafer etch system (100 mm diameter wafers) with electrode spacing of 6 mm.
• the power supplied to the plasma was 350 watts at a RF frequency of 13.56 MHz.
• the chamber pressure was 650-700 m Torr and converted into SI units "86-93 Pa".
• Another effective etch is described in the paper "Planarization of Phosphorus-Doped Silicon Dioxide" by A. C. Adams and C. D. Capio in the Journal of the Electrochemical Society, Vol. 128, pages 423-429.
• Si0 2 silicon dioxide
• etch rates are similar to photoresist and if deposition of the material with sufficient thickness can be performed on the spacer and existing device.
• FIG. 3 where a lens 57 formed of Si0 2 is shown, light striking the lens surface 59, indicated by vertical arrows, is bent inwardly, as indicated by the converging arrows in layer 53. The light is shown directed to the focal spot F on the surface of the photodiode.
• the inward directing of light from the lens to the photodiode causes light to be received by only the central portion of the filter.
• the lens array constructions allows edge alignments of the pixel boundaries and the filter elements to be relaxed without incurring an optical penalty.

Landscapes

• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Electromagnetism (AREA)
• Chemical & Material Sciences (AREA)
• Manufacturing & Machinery (AREA)
• Chemical Kinetics & Catalysis (AREA)
• General Chemical & Material Sciences (AREA)
• Inorganic Chemistry (AREA)
• Solid State Image Pick-Up Elements (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=22856806

Family Applications (1)

Country Status (3)

Families Citing this family (6)

Family Cites Families (4)

• 1989
  • 1989-07-27 WO PCT/US1989/003181 patent/WO1990001805A1/en not_active Application Discontinuation
  • 1989-07-27 EP EP89909468A patent/EP0380654A1/de not_active Withdrawn
  • 1989-07-27 JP JP89508871A patent/JPH03500834A/ja active Pending

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events