WO1990001805A1 - Lens arrays for light sensitive devices - Google Patents

Lens arrays for light sensitive devices Download PDF

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Publication number
WO1990001805A1
WO1990001805A1 PCT/US1989/003181 US8903181W WO9001805A1 WO 1990001805 A1 WO1990001805 A1 WO 1990001805A1 US 8903181 W US8903181 W US 8903181W WO 9001805 A1 WO9001805 A1 WO 9001805A1
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WO
WIPO (PCT)
Prior art keywords
layer
photoresist
lens array
lens
dielectric material
Prior art date
Application number
PCT/US1989/003181
Other languages
French (fr)
Inventor
David Newell Nichols
Original Assignee
Eastman Kodak Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Company filed Critical Eastman Kodak Company
Priority to JP89508871A priority Critical patent/JPH03500834A/en
Publication of WO1990001805A1 publication Critical patent/WO1990001805A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors

Definitions

  • the present invention relates to making lens arrays in Si0 2 for light sensitive devices.
  • Image sensing devices made up of an array of laterally spaced sensors are well known and can take a variety of forms.
  • the array can be viewed as being made up of a number of laterally offset regions, commonly referred to as pixels or sensing elements.
  • the art has recognized that sensing advantages can be realized by forming a lens array having convex lens surface for each pixel.
  • This object is achieved in a method of forming on a light sensitive device defining a plurality of sensing elements, a lens array having a separate lens for each sensing element, comprising the steps of: a) providing a spacer and planarization layer on the device over each sensing element; b) depositing a layer of hard dielectric material on the spacer and planarization layer; c) applying a layer of photoresist material and patterning and flowing the photoresist material in the shape of the desired lens array on the hard dielectric material layer; and d) plasma etching the photoresist material which etches the hard dielectric material at a similar rate as it etches the photoresist material until the lens array is etched into the layer of hard dielectric material.
  • FIG. 1 is a plan view of a multipixel semiconductor array
  • FIG. 2 is a sectional of a single sensing element just after a photoresist layer has been patterned in the process of forming the lens array of FIG. 3;
  • FIG. 3 is a sectional view of the sensing element of FIG. 2 after the lens array has been formed.
  • FIG. 1 a multipixel semiconductor array 10 is shown formed by a plurality of laterally spaced photodiodes 14 on a substrate.
  • the semiconductor array can be viewed as being made up of a plurality of sensing elements or pixels 12, each having a photodiode sensor 14 centrally positioned adjacent its upper surface and each peripherally defined by linear polygonal boundaries indicated by dashed lines 18.
  • FIG. 2 where we see in cross—section a sensing element or pixel 12 of the array of FIG. 1 while in the process of forming the lens array of this invention.
  • a conductive layer 27 covers the lower major surface.
  • the semiconductive substrate has an N conductivity type region 29 and a P conductivity type well 31 formed by diffusion from the upper major surface 23.
  • a photodiode is formed centrally in the pixel by an N diffusion 33 from the upper major surface. The function of the photodiode is to produce electrons in proportion to the amount of light received on exposure.
  • the electrons are supplied to an adjacent charge coupled device.
  • a shallow N conductivity type region 35 is located adjacent the upper major surface.
  • the buried channel thus formed extends from the photodiode to an adjacent CCD.
  • P conductivity type zones 37 referred to as channel stops, isolate the photodiode and the adjacent CCD from other adjacent surface structures.
  • a gate electrode 39 typically formed of polycrystalline silicon, is shown overlying a gate insulator 36 which overlies the upper surface of the semiconductive substrate. Since polycrystalline silicon is transparent, a light shield 41, typically formed of aluminum, overlies the gate electrode. A transparent insulator 43 is shown overlying the entire upper major surface of the semiconductive substrate and also separating the gate electrodes from the light shields. Typically the insulator is silicon dioxide, with a surface laydown of passivant, such as borosilicate glass, being common. Although shown as unit, the insulator is typically formed in several successive fabrication steps.
  • a transparent insulative material 45 commonly referred to as a planarizing material, is positioned to provide a smooth surface 47.
  • a filter 49 having an element 51, such as an additive primary filter element, coextensive with the pixel or sensor element boundaries.
  • a spacer and planarization layer 53 is formed on filter 49. The purpose of layer 53 is to offset the lens from the photodiode to maximize collection of light in photodiode or to permit the use of a smaller photodiode with the same collection efficiency.
  • the layer 53 of course, has to be transparent and must permit the hard, transparent layer 54 to be formed on it.
  • a layer 54 is deposited.
  • Layer 54 is formed of Si0 2 or some other hard transparent dielectric.
  • a layer of photoresist is then deposited.
  • a lens array is formed in photoresist layer 54 in the manner described in detail in U.S. Patent No. 4,694,185.
  • a photoresist layer is deposited by spin coating.
  • the resist is patterned by photolitho ⁇ graphy.
  • the resist is flowed to form a convex lens-like upper surface 59.
  • U.S. Patent No. 4,694,185 described in detail a patterning and flowing of photoresist to form a lens array.
  • the lens profile of the photoresist is transferred to the Si0 2 layer 54 as shown in FIG. 3. More specifically, the lens shape array in photoresist is transferred to the Si0 2 using a plasma etch which etches Si0 2 at the same rate as the resist. This etch is continued until all resist is removed.
  • FIG. 3 shows the Si0 2 in the shape of the photoresist after this etch.
  • a plasma etch with the same etch rates (1:1) for a dielectric (phosphorus-doped Si0 2 ) and a Novalak based photoresist is formed from gases C 2 F, , 0 2 and He. They are in a 4:1:1 volume ratio.
  • Such gas has been flowed through a single wafer etch system (100 mm diameter wafers) with electrode spacing of 6 mm.
  • the power supplied to the plasma was 350 watts at a RF frequency of 13.56 MHz.
  • the chamber pressure was 650-700 m Torr and converted into SI units "86-93 Pa".
  • Another effective etch is described in the paper "Planarization of Phosphorus-Doped Silicon Dioxide" by A. C. Adams and C. D. Capio in the Journal of the Electrochemical Society, Vol. 128, pages 423-429.
  • Si0 2 silicon dioxide
  • etch rates are similar to photoresist and if deposition of the material with sufficient thickness can be performed on the spacer and existing device.
  • FIG. 3 where a lens 57 formed of Si0 2 is shown, light striking the lens surface 59, indicated by vertical arrows, is bent inwardly, as indicated by the converging arrows in layer 53. The light is shown directed to the focal spot F on the surface of the photodiode.
  • the inward directing of light from the lens to the photodiode causes light to be received by only the central portion of the filter.
  • the lens array constructions allows edge alignments of the pixel boundaries and the filter elements to be relaxed without incurring an optical penalty.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

In the method of this invention, lens arrays for light sensitive devices are formed in SiO2 or other hard dielectric material consisting of forming lens arrays in photoresist on a layer of SiO2, then, using an etch with etch rates similar for oxide and resist, transferring the resist profile to the SiO2.

Description

LENS ARRAYS FOR LIGHT SENSITIVE DEVICES Field of the Invention
The present invention relates to making lens arrays in Si02 for light sensitive devices. Background of the Invention
Image sensing devices made up of an array of laterally spaced sensors are well known and can take a variety of forms. The array can be viewed as being made up of a number of laterally offset regions, commonly referred to as pixels or sensing elements. The art has recognized that sensing advantages can be realized by forming a lens array having convex lens surface for each pixel.
Commonly assigned U.S. Patent No. 4,694,185 to Weiss discloses a multipixel light sensing semiconductor device having a lens array with a separate lens for each image pixel. The device has a lens supporting layer for directing light inwardly to a se iconductive light sensor. As discussed in this patent, the lens array is made by processing polymeric photoresist material. While effective, the lenses of such arrays have problems . They are susceptible to defects caused by handling and high temperature environments. Also, they may "yellow*' in response to XN radiation. Summary of the Invention
It is an object of this invention to produce lens arrays for light sensitive devices which eliminate the problems noted above. This object is achieved in a method of forming on a light sensitive device defining a plurality of sensing elements, a lens array having a separate lens for each sensing element, comprising the steps of: a) providing a spacer and planarization layer on the device over each sensing element; b) depositing a layer of hard dielectric material on the spacer and planarization layer; c) applying a layer of photoresist material and patterning and flowing the photoresist material in the shape of the desired lens array on the hard dielectric material layer; and d) plasma etching the photoresist material which etches the hard dielectric material at a similar rate as it etches the photoresist material until the lens array is etched into the layer of hard dielectric material. Brief Description of the Drawings
The invention can be better appreciated by reference to the following description of preferred embodiments considered in conjunction with the drawings, in which
FIG. 1 is a plan view of a multipixel semiconductor array; FIG. 2 is a sectional of a single sensing element just after a photoresist layer has been patterned in the process of forming the lens array of FIG. 3; and
FIG. 3 is a sectional view of the sensing element of FIG. 2 after the lens array has been formed. Mode of Carrying: Out the Invention
In FIG. 1 a multipixel semiconductor array 10 is shown formed by a plurality of laterally spaced photodiodes 14 on a substrate.
The semiconductor array can be viewed as being made up of a plurality of sensing elements or pixels 12, each having a photodiode sensor 14 centrally positioned adjacent its upper surface and each peripherally defined by linear polygonal boundaries indicated by dashed lines 18. Turning now to FIG. 2 where we see in cross—section a sensing element or pixel 12 of the array of FIG. 1 while in the process of forming the lens array of this invention. A semiconductive substrate 21, typically a onocrystalline silicon substrate, is shown having an upper major surface 23 and a lower major surface 25. A conductive layer 27 covers the lower major surface. The semiconductive substrate has an N conductivity type region 29 and a P conductivity type well 31 formed by diffusion from the upper major surface 23. A photodiode is formed centrally in the pixel by an N diffusion 33 from the upper major surface. The function of the photodiode is to produce electrons in proportion to the amount of light received on exposure.
The electrons are supplied to an adjacent charge coupled device. To create a buried channel for electron transfer, a shallow N conductivity type region 35 is located adjacent the upper major surface. The buried channel thus formed extends from the photodiode to an adjacent CCD. To prevent unwanted lateral charge conductions, P conductivity type zones 37, referred to as channel stops, isolate the photodiode and the adjacent CCD from other adjacent surface structures.
A gate electrode 39, typically formed of polycrystalline silicon, is shown overlying a gate insulator 36 which overlies the upper surface of the semiconductive substrate. Since polycrystalline silicon is transparent, a light shield 41, typically formed of aluminum, overlies the gate electrode. A transparent insulator 43 is shown overlying the entire upper major surface of the semiconductive substrate and also separating the gate electrodes from the light shields. Typically the insulator is silicon dioxide, with a surface laydown of passivant, such as borosilicate glass, being common. Although shown as unit, the insulator is typically formed in several successive fabrication steps. A transparent insulative material 45, commonly referred to as a planarizing material, is positioned to provide a smooth surface 47. On this surface is positioned a filter 49 having an element 51, such as an additive primary filter element, coextensive with the pixel or sensor element boundaries. A spacer and planarization layer 53 is formed on filter 49. The purpose of layer 53 is to offset the lens from the photodiode to maximize collection of light in photodiode or to permit the use of a smaller photodiode with the same collection efficiency. The layer 53, of course, has to be transparent and must permit the hard, transparent layer 54 to be formed on it.
Next a layer 54 is deposited. Layer 54 is formed of Si02 or some other hard transparent dielectric. A layer of photoresist is then deposited. In accordance with this method of making lens array in Si02 layer 53, a lens array is formed in photoresist layer 54 in the manner described in detail in U.S. Patent No. 4,694,185. As described in such patent, a photoresist layer is deposited by spin coating. The resist is patterned by photolitho¬ graphy. Then, by appropriate heat treatment, the resist is flowed to form a convex lens-like upper surface 59. U.S. Patent No. 4,694,185 described in detail a patterning and flowing of photoresist to form a lens array.
Thereafter, using an etch with etch rates similar for oxide and photoresist, the lens profile of the photoresist is transferred to the Si02 layer 54 as shown in FIG. 3. More specifically, the lens shape array in photoresist is transferred to the Si02 using a plasma etch which etches Si02 at the same rate as the resist. This etch is continued until all resist is removed. FIG. 3 shows the Si02 in the shape of the photoresist after this etch. A plasma etch with the same etch rates (1:1) for a dielectric (phosphorus-doped Si02) and a Novalak based photoresist is formed from gases C2F, , 02 and He. They are in a 4:1:1 volume ratio. Such gas has been flowed through a single wafer etch system (100 mm diameter wafers) with electrode spacing of 6 mm. The power supplied to the plasma was 350 watts at a RF frequency of 13.56 MHz. The chamber pressure was 650-700 m Torr and converted into SI units "86-93 Pa". Another effective etch is described in the paper "Planarization of Phosphorus-Doped Silicon Dioxide" by A. C. Adams and C. D. Capio in the Journal of the Electrochemical Society, Vol. 128, pages 423-429.
It is noted that other "hard" dielectric materials may be used in place of Si02 if etch rates are similar to photoresist and if deposition of the material with sufficient thickness can be performed on the spacer and existing device.
Turning to FIG. 3 where a lens 57 formed of Si02 is shown, light striking the lens surface 59, indicated by vertical arrows, is bent inwardly, as indicated by the converging arrows in layer 53. The light is shown directed to the focal spot F on the surface of the photodiode.
It should be noted that the inward directing of light from the lens to the photodiode causes light to be received by only the central portion of the filter. Thus, the lens array constructions allows edge alignments of the pixel boundaries and the filter elements to be relaxed without incurring an optical penalty.
While only one sensing element of the exemplary semiconductor device is shown in FIG. 3, it is appreciated that actual devices typically contain very large numbers of essentially similar sensing
3 elements, actual numbers ranging in the 10 to
10 orders of magnitude, depending on the application being served. While the invention has been described in terms of directing light to a photodiode, it is appreciated that many CCD's are constructed for directly sensing light and can be made in accordance with the invention. The application of the invention to still other light sensing multipixel semiconductor arrays will be readily appreciated.
The invention has been described in detail with particular reference to a preferred embodiment thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.

Claims

What is claimed is
1. In a method of forming a lens array on a light sensitive device defining a plurality of sensing elements, a lens array having a separate lens for each image sensor and is obtained by wiring a layer of photoresist material 55 and patterning and flowing the photoresist material in the shape of the desired lens array on the hard dielectric material layer; and wherein a spacer and planarization layer 53 on the device over each sensing element is provided; said method being characterized by the steps of:
(a) providing a layer 54 of hard, transparent dielectric material between the spacer and planarization layer and the photoresist material; and
(b) plasma etching the photoresist material which etches the hard dielectric material at a similar rate as it etches the photoresist material until the lens array is etched into the layer of hard dielectric material.
2. The method of claim 2 wherein such hard dielectric material is Si02-
3. The method of claim 2 wherein the plasma etch is formed from a gas having C2F,,
02 and He.
PCT/US1989/003181 1988-08-01 1989-07-27 Lens arrays for light sensitive devices WO1990001805A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP89508871A JPH03500834A (en) 1988-08-01 1989-07-27 Lens array for photosensitive devices

Applications Claiming Priority (2)

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US22834588A 1988-08-01 1988-08-01
US228,345 1988-08-01

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992006506A1 (en) * 1990-10-01 1992-04-16 Eastman Kodak Company Static control overlayers on opto-electronic devices
EP0502340A2 (en) * 1991-02-12 1992-09-09 Sony Corporation CCD solid state imager
EP0706070A3 (en) * 1994-10-04 1997-04-02 Siemens Ag Process for dry-etching a semiconductor substrate
US5811320A (en) * 1992-09-30 1998-09-22 Rostoker; Michael D. Method of forming image with binary lens element array
EP0875940A2 (en) * 1997-04-30 1998-11-04 Hewlett-Packard Company Optoelectronic array and method of making the same
US8253142B1 (en) * 1999-08-27 2012-08-28 Sony Corporation Solid-state imaging device and method of fabricating the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667092A (en) * 1982-12-28 1987-05-19 Nec Corporation Solid-state image device with resin lens and resin contact layer
US4694185A (en) * 1986-04-18 1987-09-15 Eastman Kodak Company Light sensing devices with lenticular pixels
JPH0653073A (en) * 1992-07-29 1994-02-25 Mitsubishi Materials Corp Chip type silicon capacitor
JPH0660755A (en) * 1992-08-06 1994-03-04 Fujitsu Ltd Small sized detection switch

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667092A (en) * 1982-12-28 1987-05-19 Nec Corporation Solid-state image device with resin lens and resin contact layer
US4694185A (en) * 1986-04-18 1987-09-15 Eastman Kodak Company Light sensing devices with lenticular pixels
JPH0653073A (en) * 1992-07-29 1994-02-25 Mitsubishi Materials Corp Chip type silicon capacitor
JPH0660755A (en) * 1992-08-06 1994-03-04 Fujitsu Ltd Small sized detection switch

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Journal of the Electrochemial Society, Volume 132, No. 8, August 1985, (Manchester, New Hampshire, US), R.J. SAIA et al.: "Dry Etching of Tapered Contact Holes using Multilayer Resist", pages 1954-1957 *
Journal of the Electrochemical Society, Volume 128, No. 2, February 1981, (Manchester, New Hampshire, US), A.C. ADAMS et al.: "Planarization of Phosphorus-Doped Silicon Dioxide", pages 423-429 *
PATENT ABSTRACTS OF JAPAN, Volume 8, No. 206 (E-267) (1643), 20 September 1984; & JP-A-5992567 (Mitsubishi Denki K.K.) 28 May 1984 *
PATENT ABSTRACTS OF JAPAN, Volume 9, No. 181 (E-331) (1904), 26 July 1985; & JP-A-6053073 (Hitachi Seisakusho K.K.) 26 March 1985 *
PATENT ABSTRACTS OF JAPAN, Volume 9, No. 193 (E-334) (1916), 9 August 1985; & JP-A-6060755 (Hitachi Seisakusho K.K.) 8 April 1985 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992006506A1 (en) * 1990-10-01 1992-04-16 Eastman Kodak Company Static control overlayers on opto-electronic devices
EP0502340A2 (en) * 1991-02-12 1992-09-09 Sony Corporation CCD solid state imager
EP0502340A3 (en) * 1991-02-12 1992-10-21 Sony Corporation Ccd solid state imager
US5811320A (en) * 1992-09-30 1998-09-22 Rostoker; Michael D. Method of forming image with binary lens element array
EP0706070A3 (en) * 1994-10-04 1997-04-02 Siemens Ag Process for dry-etching a semiconductor substrate
US5705025A (en) * 1994-10-04 1998-01-06 Siemens Aktiengesellschaft Method for dry etching of a semiconductor substrate
EP0875940A2 (en) * 1997-04-30 1998-11-04 Hewlett-Packard Company Optoelectronic array and method of making the same
EP0875940A3 (en) * 1997-04-30 2000-01-05 Hewlett-Packard Company Optoelectronic array and method of making the same
US8253142B1 (en) * 1999-08-27 2012-08-28 Sony Corporation Solid-state imaging device and method of fabricating the same
US8729650B2 (en) 1999-08-27 2014-05-20 Sony Corporation Solid-state imaging device and method of fabricating the same

Also Published As

Publication number Publication date
EP0380654A1 (en) 1990-08-08
JPH03500834A (en) 1991-02-21

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