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EP0353779A2 - Preamble detection circuit for digital communications system - Google Patents

Preamble detection circuit for digital communications system

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Publication number
EP0353779A2
EP0353779A2 EP19890114484 EP89114484A EP0353779A2 EP 0353779 A2 EP0353779 A2 EP 0353779A2 EP 19890114484 EP19890114484 EP 19890114484 EP 89114484 A EP89114484 A EP 89114484A EP 0353779 A2 EP0353779 A2 EP 0353779A2
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EP
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Patent type
Prior art keywords
phase
clock
error
detector
means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19890114484
Other languages
German (de)
French (fr)
Other versions
EP0353779A3 (en )
EP0353779B1 (en )
Inventor
Motoya C/O Nec Corporation Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying includes continuous phase systems
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/227Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2275Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying includes continuous phase systems
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/233Demodulator circuits; Receiver circuits using non-coherent demodulation
    • H04L27/2332Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0024Carrier regulation at the receiver end
    • H04L2027/0026Correction of carrier offset
    • H04L2027/003Correction of carrier offset at baseband only
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0044Control loops for carrier regulation
    • H04L2027/0053Closed loops
    • H04L2027/0057Closed loops quadrature phase
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0083Signalling arrangements
    • H04L2027/0089In-band signals
    • H04L2027/0093Intermittant signals
    • H04L2027/0095Intermittant signals in a preamble or similar structure
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

In a burst mode digital communication system, a preamble containing a predetermined bit pattern and a digital signal are modulated upon orthogonal carriers and transmitted in a series of burst signals. At a distant end of the system, the preamble and the digital signal are noncoherently detected with locally generated orthogonal carriers having the same frequency as the transmitted orthogonal carriers to produce in-­phase and quadrature signals. First and second correlators are provided to perform a correlation calculation between a locally generated bit pattern and the in-phase signal and to perform a correlation calculation between the local bit pattern and the quadrature signal. A phase error of the local carriers with respect to the transmitted carriers is detected from the outputs of the first and second correlators. A clock phase error of a locally generated clock pulse with respect to symbols contained in the transmitted burst signals is detected from one of the outputs of the correlators. Power level detector is connected to the outputs of the correlators for detecting a power level of the received burst signals. The carrier and clock phase error detection as well as the power level detection are performed in a parallel fashion, allowing a reduction of the amount of information contained in the preamble.

Description

  • [0001]
    The present invention relates generally to burst mode digital communications systems, and more specifically it relates to a technique for reducing the amount of information contained in the preamble of each burst transmission that is necessary for recovering carrier and clock timing at a receiving end of the system.
  • [0002]
    In a burst mode of digital transmission, a preamble is transmitted at the beginning of each burst transmission to convey information as to the carrier and symbol clock timing of a modulator to allow receiving stations to establish correct timing relationships with the carrier and symbol clock of the modulator. The preamble is made up of a carrier recovery field and a clock recovery field that follows. On receiving a preamble, the receiver's function is to first analyze the carrier recovery field to establish correct timing with the carrier of the modulator and then proceed to the clock recovery field to establish proper symbol clock timing. In addition, an automatic gain control signal is derived from the received signal after the clock recovery procedure is complete.
  • [0003]
    Because of the sequential operations, the time taken to process the preamble is substantial and hence the transmission efficiency of the current burst mode of digital communications system is low.
  • [0004]
    It is therefore an object of the present invention to provide a preamble detection circuit that requires a small amount of preamble information for establishing carrier and clock timing and controlling preamplifier gain by deriving error control signals simultaneously during the reception of a preamble.
  • [0005]
    According to one aspect of the present invention, a preamble detection circuit is provided. At a transmitter, a preamble containing a predetermined bit pattern and a digital signal are modulated upon orthogonal carriers and transmitted in a series of burst signals. The preamble detection circuit noncoherently ("pseudo-synchronously") detects the preamble and digital signal with locally generated orthogonal carriers having the same frequency as the transmitted orthogonal carriers to produce in-phase and quadrature signals. The locally generated carriers tend to deviate in phase from the transmitted orthogonal carriers over a predetermined range. First and second correlators are provided to perform a correlation calculation between a locally generated bit pattern which corresponds to the bit pattern of the preamble and the in-phase signal and to perform a correlation calculation between the locally generated bit pattern and the quadrature signal. A phase error of the locally generated orthogonal carriers with respect to the transmitted carriers is detected from the outputs of the first and second correlators. A clock phase error of a locally generated clock pulse with respect to transmitted symbols is detected from one of the outputs of the correlators. Power level detector is preferably connected to the outputs of the correlators for detecting a power level of the received burst signals.
  • [0006]
    Since the carrier and clock phase error detection and the power level detection can be performed in a parallel fashion, the amount of information contained in the preamble can be reduced.
  • [0007]
    According to a second aspect, a digital communication system incorporating the preamble detection circuit is provided. The system includes a gain-controlled amplifier for amplifying burst signals received from a transmitter station with a gain controlled with the power level detected by the power level detector. A symbol clock generator generates a local clock pulse at a symbol rate of the transmitted burst signals. First and second decision circuits, or A/D converters, are responsive to the local clock pulse for sampling the in-phase and quadrature output signals from the correlators. A clock phase error detector is connected to one of the outputs of the correlators and to the output of the symbol clock generator for detecting a phase error of the local clock pulse with respect to symbols of the transmitted burst signals and controlling the symbol clock generator with the detected phase error. A carrier generator generates second local orthogonal carriers. Using the second local carriers, a synchronous detector provides synchronous detection on output signals from the first and second decision circuits. A carrier phase error detector is connected to the outputs of the first and second correlators for detecting a phase error of the local orthogonal carriers with respect to the transmitted carriers and controlling the carrier generator with the detected phase error.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0008]
    The present invention will be described in further detail with reference to the accompanying drawings, in which:
    • Fig. 1 is a block diagram of a receiving station of a digital communication system according to an embodiment of the present invention;
    • Fig. 2 shows a data structure of a burst transmission employed in the present invention;
    • Fig. 3 shows details of the error detection circuit of Fig. 1, including the power level detector, clock phase error detector and carrier phase error detector;
    • Fig. 4 shows a waveform of a portion of the preamble of a modulated QPSK incoming signal;
    • Fig. 5 shows a portion of the locally generated predetermined bit pattern supplied to the correlators of Fig. 1;
    • Fig. 6 shows a portion of the waveform of the output signal of one of correlators of Fig. 1; and
    • Figs. 7-9 are illustrations of the outputs of the clock phase error detector, carrier phase error detector and power level detector of Fig. 3, respectively.
    DETAILED DESCRIPTION
  • [0009]
    Referring now to Fig. 1, there is shown a receiving station of a burst mode digital radio communication system according to an embodiment of the present invention. Through an input terminal 10 the station receives a transmitted burst of a QPSK (quadrature phase-shift keying) signal which comprises a preamble and a data field as shown in Fig. 2. The preamble contains a sequence of +1 and -1 binary logic values of a predetermined number which alternate at symbol clock intervals T. No discrimination is made between a carrier recovery field and a clock recovery field as in the format of the prior art preamble.
  • [0010]
    The preamble of each burst transmission at terminal 10 has a waveform M(t) which is represented by m(t)(cos ωct + sin ωct) as illustrated in Fig. 4, where m(t) is +1 for t=2nT, -1 for t=(2n+1)T and 0 for t=(n+½)T, and ωc is the angle frequency of the carrier of the burst signal and n is an integer including zero. The signal contained in the preamble is passed through a gain-controlled preamplifier stage 11 to a QPSK (quadriphase shift keying) demodulator 12. This demodulator is provided with a local oscillator which independently generates orthogonal carriers having the same frequency as the transmitted carriers without receiving frequency and phase control signals from external sources. The local carriers may deviate in phase from the transmitted carriers in a range between -π and +π. Therefore, the incoming signal is demodulated in a "pseudo-synchronous mode", or noncoherent detection mode to recover the following in-phase and quadrature components I(t) and Q(t):
    I(t) = ½m(t)(cosΔϑ-sinΔϑ)      (1)
    Q(t)= ½m(t)(cosΔϑ+sinΔϑ)      (2)
    These components appear at the inputs of correlators 13 and 14, respectively.
  • [0011]
    A pattern generator 15 is provided to supply to the correlators 13 and 14 a sequence V(T) of symbol bits which is given by the following relation: where N is the number of symbol bits contained in the preamble, δ(t) is the delta function, and Vn assumes +1 for n=4k or 4k+1 or -1 for n=4k+2 or 4k+3 (where k is an integer including zero). Therefore, Vn is a series of 2N symbols of +1, +1, -1, -1, +1, +1, .....-1, -1 as shown Fig. 5.
  • [0012]
    Each of the correlators 13 and 14 performs correlation calculation to produce output signals I′(t) and Q′(t), respectively, which are given by:
  • [0013]
    Since m(t) is given by the following equations:
    m(t -2kT) = m(t)      (6)
    m{t - (2k+1)T} = -m(t)      (7)
    m(t - T 2 - 2kT) = m(t - T 2 )      (8)
    m{t - T 2 -(2k+1)T} = -m(t - T 2 )      (9)
    the in-phase and quadrature signals I′(t) and Q′(t) during the reception of a preamble can be represented by:
    I′(t) = N[m(t) + m(t - T 2 )] (cosΔϑ - sinΔϑ)      (10)
    Q′(t) = N[m(t) + m(t - T 2 )] (cosΔϑ + sinΔϑ)      (11)
    Fig. 6 depicts the waveform of the in-phase signal I′(t) as a result of the correlation calculation between the symbols from the pattern generator 15 and those of the preamble contained in the in-phase signal I(t). A similar waveform is derived from the correlation calculation between the symbols from the pattern generator 15 and those of the preamble contained in the quadrature signal Q(t). The outputs of the correlators 13 and 14 are coupled to an error detection circuit including a power level detector 16, a clock phase error detector 17 and a carrier phase error detector 18. Details of the detector circuits 16, 17 and 18 will be described with reference to Fig. 3.
  • [0014]
    On the other hand, the outputs of demodulator 12 are further coupled to analog-to-digital converters 20 and 21, respectively, to produce digital versions of the in-phase and quadrature signals I(t) and Q(t) for coupling to a synchronous detector 22. Sampling pulses are supplied to the A/D converters 20 and 21 at symbol clock timing from a closed loop including a clock frequency error detector 23 coupled to one output terminal of the synchronous detector 22 and a voltage-controlled oscillator 24 which is responsive to a frequency error from the detector 23 as well as to a phase error supplied from the clock phase error detector 17. Clock frequency error detector 23 includes a zero-crossing detector and a loop filter to generate a signal representative of a frequency deviation of the VCO 24 from the transmitted symbol clock frequency.
  • [0015]
    Orthogonal reference carriers for the synchronous detector 22 are obtained by a closed loop formed by a carrier frequency error detector 25 coupled to the outputs of synchronous detector 22 which respectively lead to output terminals 28I and 28Q, a voltage-controlled oscillator 26 responsive to the outputs of the frequency error detector 25 as well as to a carrier phase error supplied from the phase error detector 18, and a π/2 phase shifter 27 coupled to the VCO 23. Carrier frequency error detector 25 includes a phase discriminator coupled to the outputs of synchronous detector 22 and a loop filter to generate a signal representative of a frequency deviation of the VCO 23 from an intended value.
  • [0016]
    A gain control circuit 19 is provided to respond to the outputs of power level detector 16 and VCO 24 by maintaining the output power level of preamplifier stage 11 at a constant level.
  • [0017]
    As shown in Fig. 3, clock phase error detector 17 comprises D flip-flops 33 and 34 whose data inputs are coupled to one of the outputs of correlators 13 and 14. The output of VCO 24 is supplied to the clock input of flip-flop 33 through a delay circuit 35 that introduces a half-symbol interval (=T/2) on the one hand, and directly to the clock input of flip-flop 34 on the other. The output of flip-flop 33 is coupled to one input of a multiplier 37 and the output of flip-flop 34 is coupled to a sign-code detector 36 whose output is connected to the other input of multiplier 37. The output of multiplier 37 is representative of a phase error of the symbol clock timing and fed to the phase control input of the VCO 24. Assume that there is a phase delay of ΔT in the local symbol clock from VCO 24 with respect to that of the incoming signal, the sampling of the input signal I′(t) by flip-flop 34 in response to the local symbol clock results in the generation of a sample value I′n which is given by:
    I′n = I′(nT + ΔT)      (12)
    where, 0 ≦ ΔT < T. On the other hand, the sampling of the signal I′(t) by flip-flop 33 in response to the output of delay 35 results in the generation of a sample value I˝n which is given by:
    n = I′(nT + T 2 + ΔT)      (13)
    Typical examples of the sample values I′n and I˝n are respectively indicated by blank and solid dots in Fig. 6. Sign-code detector 36 produces signal SGN (I′n) which is multiplied by I˝n by multiplier 37 to produce a clock phase error signal which is given by:
    R = SGN (I′n) I˝n      (14)
    where SGN (·) denotes the signum function. This signal varies exclusively as a function of symbol clock phase error ΔT as shown in Fig. 7.
  • [0018]
    Carrier phase error detector 18 is formed by a dividing circuit 38 that performs division calculation Q′/I′ on the signals from the correlators 13 and 14 and supplies the result of the calculation to an arctangent calculator 39, which calculates the following equation:
  • [0019]
    As illustrated in Fig. 8, the output of the arctangent calculator 39 is a signal that varies as a linear function of phase error Δϑ. The output of arctangent calculator 39 is fed to a subtractor 40 where π/4 is subtracted. The output of subtractor 40 is applied to VCO 26 as a carrier phase error.
  • [0020]
    Power level detector 16 includes squaring circuits 30 and 31 respectively coupled to the outputs of correlators 13 and 14 to generate squared values I′(t) and Q′(t). An adder 32 adds up the squared signals [I′(t)]² and [Q′(t)]² to produce a signal P(t) which is given by:
    P(t) = [I′(t)]² + [Q′(t)]²
    = 2N² [m(t) + m(t - T 2 )]²      (16)
    and supplies the sum as a gain control signal to the gain control circuit 19. As shown in Fig. 9, the gain control signal varies exclusively with the amplitude m(t) of the incoming signal and represents its signal power.
  • [0021]
    The operation of gain control circuit 19 is based on the sampling of the output of power level detector 16 in response to the output of VCO 24 so that the sampled value is a faithful representation of power level at the time the phase error control signal ΔT is generated. The gain and phase error control signals can therefore be derived in a short period of time and hence the amount of information contained in the preamble of each burst transmission can be reduced to achieve high transmission efficiency.
  • [0022]
    The system operates satisfactorily with the local oscillator included in the orthogonal demodulator 12 of the type mentioned above if the amount of time necessary for error detection is much less than a period 1/Δf, (where Δf represents the frequency deviation of the local oscillator of demodulator 12 from the carrier frequency of the incoming signal).
  • [0023]
    According to another feature of the invention, the use of correlators 13 and 14 ensures high signal-to-noise ratio at their outputs by as much as {(10/2)log₁₀N} dB. This is advantageous for the error detection circuit to derive control signals.
  • [0024]
    The foregoing description shows only one preferred embodiment of the present invention Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiment shown and described is only illustrative, not restrictive.

Claims (10)

1. A preamble detection circuit for a transmission system in which a preamble and a digital signal are modulated upon orthogonal carriers and transmitted in a series of burst signals said preamble containing a predetermined bit pattern, comprising:
orthogonal demodulator means for receiving the transmitted burst signals and noncoherently detecting the preamble and the digital signal with local orthogonal carriers having the same frequency as the frequency of the transmitted orthogonal carriers, said local orthogonal carriers tending to deviate in phase over a predetermined range from the transmitted orthogonal carriers, said orthogonal demodulator means generating in-phase and quadrature output signals;
means for generating a local bit pattern corresponding to the bit pattern contained in said preamble;
first and second correlators, the first correlator providing a correlation calculation between the local bit pattern and the in-phase output signal and the second correlator providing a correlation calculation between the local bit pattern and the quadrature output signal;
carrier phase error detector means connected to the outputs of the first and second correlators for detecting a phase error of the local orthogonal carriers with respect to the transmitted carriers;
symbol clock generator means for generating a local clock pulse at a symbol rate of the transmitted burst signals; and
clock phase error detector means connected to one of the outputs of the first and second correlators and to the output of the symbol clock generator means for detecting a phase error of the local clock pulse with respect to symbols contained in the transmitted burst signals and controlling the symbol clock generator means with the detected phase error.
2. A preamble detection circuit as claimed in claim 1, further comprising power level detector means connected to the outputs of the first and second correlators for detecting a power level of the received burst signals.
3. A preamble detection circuit in claim 1 or 2, wherein the bit pattern contained in the preamble is a series of alternating binary logic values.
4. A preamble detection circuit as claimed in any one of claims 1 to 3, wherein the carrier phase error detector means comprises:
a division circuit for providing a division calculation between the in-­phase and quadrature output signals to produce a quotient; and
arctangent calculator means for determining the arctangent of the quotient.
5. A preamble detection circuit as claimed in any one of claims 1 to 4, wherein the clock phase error detector means comprises:
delay means for delaying the local clock pulse by an amount corresponding to one-half the interval between successive symbols contained in the transmitted burst signals;
first sampling means for sampling one of the in-phase and quadrature output signals in response to the delayed local clock pulse;
second sampling means for sampling the one of said in-phase and quadrature output signals in response to the local clock pulse;
symbol detector means for detecting a predetermined symbol from the output of the second sampling means; and
multiplier means for generating a signal representative of a product of the output of the first sampling means and the predetermined symbol.
6. A digital communication system in which a preamble and a digital signal are modulated upon orthogonal carriers and transmitted to a distant end of the system in a series of burst signals, the preamble containing a predetermined bit pattern for carrier and clock recovery at the distant end of the system, comprising at the distant end:
gain-controlled amplifier means for receiving the transmitted burst signals and amplifying the received signals;
orthogonal demodulator means connected to the amplifier means for noncoherently detecting the preamble and the digital signal with local orthogonal carriers having the same frequency as the frequency of the transmitted orthogonal carriers, said local orthogonal carriers tending to deviate in phase over a predetermined range from the transmitted orthogonal carriers, said orthogonal demodulator means generating in-­phase and quadrature output signals;
means for generating a local bit pattern corresponding to the bit pattern contained in said preamble;
first and second correlators, the first correlator providing a correlation calculation between the local bit pattern and the in-phase output signal and the second correlator providing a correlation calculation between the local bit pattern and the quadrature output signal; symbol clock generator means for generating a local clock pulse at a symbol rate of the transmitted burst signals;
first and second decision circuits responsive to the local clock pulse for respectively sampling the in-phase and quadrature output signals;
clock phase error detector means connected to one of the outputs of the first and second correlators and to the output of the symbol clock generator means for detecting a phase error of the local clock pulse with respect to symbols contained in the transmitted burst signals and controlling the symbol clock generator means with the detected phase error;
carrier generator means for generating second local orthogonal carriers;
synchronous detector means for providing synchronous detection on output signals from the first and second decision circuits with the second local orthogonal carriers;
carrier phase error detector means connected to the outputs of the first and second correlators for detecting a phase error of the local orthogonal carriers with respect to the transmitted carriers and controlling the carrier generator means with the detected phase error; and
power level detector means connected to the outputs of the first and second correlators for detecting a power level of the received burst signals and controlling the gain-controlled amplifier means with the detected power level.
7. A digital communication system as claimed in claim 6, wherein the bit pattern contained in the preamble is a series of alternating binary logic values.
8. A digital communication system as claimed in claim 6 or 7, wherein the carrier phase error detector means comprises:
a division circuit for providing a division calculation between the in-­phase and quadrature output signals to produce a quotient; and
arctangent calculator means for determining the arctangent of the quotient.
9. A digital communication system as claimed in any one of claims 6 to 8, wherein the clock phase error detector means comprises:
delay means for delaying the local clock pulse by an amount corresponding to one-half the interval between successive symbols contained in the transmitted burst signals;
first sampling means for sampling one of the in-phase and quadrature output signals in response to the delayed local clock pulse;
second sampling means for sampling the one of said in-phase and quadrature output signals in response to the local clock pulse;
symbol detector means for detecting a predetermined symbol from the output of the second sampling means; and
multiplier means for generating a signal representative of a product of the output of the first sampling means and the predetermined symbol.
10. A digital communication system as claimed in any one of claims 6 to 9, further comprising means for sampling the detected power level in response to the local clock pulse and supplying the sampled power level to the gain-­controlled amplifier means as said detected power level.
EP19890114484 1988-08-05 1989-08-04 Preamble detection circuit for digital communications system Expired - Lifetime EP0353779B1 (en)

Priority Applications (2)

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JP19591188A JPH0716206B2 (en) 1988-08-05 1988-08-05 Signal detector
JP195911/88 1988-08-05

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EP0353779A2 true true EP0353779A2 (en) 1990-02-07
EP0353779A3 true EP0353779A3 (en) 1991-12-11
EP0353779B1 EP0353779B1 (en) 1995-11-02

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EP (1) EP0353779B1 (en)
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DE (2) DE68924677D1 (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991002421A1 (en) * 1989-08-11 1991-02-21 SIEMENS AKTIENGESELLSCHAFT öSTERREICH Process and device for converting digitally modulated high-frequency reception signals
EP0487701A1 (en) * 1990-06-15 1992-06-03 AlliedSignal Inc. Signal acquisition
EP0497424A2 (en) * 1991-01-31 1992-08-05 Deutsche Thomson-Brandt GmbH Broadcast receiver including a NICAM or DAB decoder
FR2672454A1 (en) * 1991-01-31 1992-08-07 Alcatel Telspace A demodulating method for coherent modulation and a phase displacement óoeuvre formatting device of the method.
EP0503632A2 (en) * 1991-03-14 1992-09-16 Fujitsu Limited Delay detector for QPSK signals
EP0527249A1 (en) * 1991-08-09 1993-02-17 Nec Corporation Carrier recovery apparatus for digital satellite communication system
EP0614582A1 (en) * 1991-11-27 1994-09-14 Communications Satellite Corporation Digital demodulator for preamble-less burst communications
FR2706711A1 (en) * 1993-06-17 1994-12-23 Matra Communication Method and digital signal demodulation apparatus.
EP0632610A1 (en) * 1993-06-29 1995-01-04 Alcatel Telspace Apparatus for detecting unique words in a BPSK-TDMA system
ES2071554A1 (en) * 1992-12-30 1995-06-16 Alcatel Standard Electrica Method and device data recovery in communication systems bursty.
EP0757461A2 (en) * 1995-07-31 1997-02-05 Harris Corporation Method of estimating signal quality for a direct sequence spread spectrum receiver
EP0805573A2 (en) * 1996-04-30 1997-11-05 Advantest Corporation Method for measuring modulation parameters of digital quadrature-modulated signal
FR2773029A1 (en) * 1997-12-23 1999-06-25 Telecommunications Sa Method of synchronizing a receiver on digital data transmitted in packets
WO2000028712A2 (en) * 1998-10-30 2000-05-18 Broadcom Corporation Cable modem system
WO2002005474A1 (en) * 2000-07-07 2002-01-17 Cleansun Pty Ltd Data communications method
EP1213872A2 (en) * 2000-12-05 2002-06-12 Philips Electronics N.V. Recovery of a packet in a packet transmission system with return link
US6961314B1 (en) 1998-10-30 2005-11-01 Broadcom Corporation Burst receiver for cable modem system
US7103065B1 (en) 1998-10-30 2006-09-05 Broadcom Corporation Data packet fragmentation in a cable modem system
US7899034B2 (en) 1998-10-30 2011-03-01 Broadcom Corporation Methods for the synchronization of multiple base stations in a wireless communication system

Families Citing this family (42)

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US5301364A (en) * 1988-11-30 1994-04-05 Motorola, Inc. Method and apparatus for digital automatic gain control in a receiver
US5276685A (en) * 1988-11-30 1994-01-04 Motorola, Inc. Digital automatic gain control
JP2638273B2 (en) * 1989-09-26 1997-08-06 日本電気株式会社 Unique word detection method
US5228057A (en) * 1989-11-15 1993-07-13 Telefonaktiebolaget L M Ericsson Method of determining sampling time points
US5206886A (en) * 1990-04-16 1993-04-27 Telebit Corporation Method and apparatus for correcting for clock and carrier frequency offset, and phase jitter in mulicarrier modems
DE4014766A1 (en) * 1990-04-19 1992-01-09 Siemens Ag Digital transmission path quality parameter evaluation system
EP0505657A1 (en) * 1991-03-27 1992-09-30 International Business Machines Corporation Preamble recognition and synchronization detection in partial-response systems
US5233632A (en) * 1991-05-10 1993-08-03 Motorola, Inc. Communication system receiver apparatus and method for fast carrier acquisition
JPH0529879A (en) * 1991-07-22 1993-02-05 Toshiba Corp Afc circuit in radio communication equipment
DE69233096D1 (en) * 1991-07-30 2003-07-17 Nec Corp Unique word detector circuit for use in a coherent demodulator
US5404362A (en) * 1991-12-04 1995-04-04 Meitner; Edmund Very low jitter clock recovery from serial audio data
JP2812347B2 (en) * 1992-02-17 1998-10-22 日本電気株式会社 Resynchronization demodulator
US5400366A (en) * 1992-07-09 1995-03-21 Fujitsu Limited Quasi-synchronous detection and demodulation circuit and frequency discriminator used for the same
JP3003826B2 (en) * 1992-12-11 2000-01-31 三菱電機株式会社 Clock recovery circuit
US5388126A (en) * 1992-12-21 1995-02-07 Rypinski; Chandos A. Baseband signal processor for a microwave radio receiver
JPH0828754B2 (en) * 1993-06-30 1996-03-21 日本電気株式会社 Frame synchronization method
US5444697A (en) * 1993-08-11 1995-08-22 The University Of British Columbia Method and apparatus for frame synchronization in mobile OFDM data communication
US5436942A (en) * 1993-08-17 1995-07-25 Teknekron Communications Systems, Inc. Method of equalizing digitally encoded signals transmitted in a plurality of non-contiguous time slots
US5491726A (en) * 1993-08-17 1996-02-13 Tcsi Corp. Method and apparatus to determine the frequency and time slot position in a digital wireless communication session
US5581579A (en) * 1993-08-17 1996-12-03 Tcsi Corporation Method and apparatus to adaptively control the frequency of reception in a digital wireless communication system
US5438595A (en) * 1993-08-17 1995-08-01 Teknekron Communication Systems, Inc. Method of estimating the speed of a mobile unit in a digital wireless communication system
US5400368A (en) * 1993-08-17 1995-03-21 Teknekron Communications Systems, Inc. Method and apparatus for adjusting the sampling phase of a digitally encoded signal in a wireless communication system
WO1995005705A1 (en) * 1993-08-17 1995-02-23 Teknekron Communications Systems, Inc. Digital wireless communication system and method of operation therefor
US5444639A (en) * 1993-09-07 1995-08-22 Rockwell International Corporation Angular rate sensing system and method, with digital synthesizer and variable-frequency oscillator
US5432819A (en) * 1994-03-09 1995-07-11 Martin Marietta Corporation DPSK communications with Doppler compensation
US5553076A (en) * 1994-05-02 1996-09-03 Tcsi Corporation Method and apparatus for a wireless local area network
US5528632A (en) * 1994-07-28 1996-06-18 Motorola, Inc. Non-complex dual-correlation phase reversal detector and method
JP2748872B2 (en) * 1994-12-28 1998-05-13 日本電気株式会社 Demodulator control system
WO1997014241A1 (en) * 1995-10-12 1997-04-17 Next Level Communications Burst mode preamble
US5729577A (en) * 1996-05-21 1998-03-17 Motorola, Inc. Signal processor with improved efficiency
US5864585A (en) 1996-10-07 1999-01-26 Erisman; David Cosine segment communications system
US6047033A (en) * 1997-05-19 2000-04-04 Motorola, Inc. Apparatus and method for signal timing error detection
CA2306842A1 (en) * 1997-11-03 1999-05-14 Harris Corporation Receiver for a reconfigurable radio system and method therefor
US6690740B1 (en) 1998-08-19 2004-02-10 Telefonaktiebolaget L M Ericsson Methods and apparatus for providing robust synchronization of radio transceivers
US6785350B1 (en) * 1999-10-14 2004-08-31 Nokia Corporation Apparatus, and associated method, for detecting a symbol sequence
US6861900B2 (en) * 2001-12-27 2005-03-01 Proxim Corporation Fast timing acquisition for multiple radio terminals
DE10213838B4 (en) * 2002-03-27 2008-10-02 Advanced Micro Devices, Inc., Sunnyvale Frequency error correction unit and method in a wireless LAN system
FR2843503B1 (en) 2002-08-08 2004-10-15 Thomson Licensing Sa A method of adjusting receiver for signals transmitted by bursts and corresponding receptors
WO2008144005A1 (en) * 2007-05-16 2008-11-27 Thomson Licensing Apparatus and method for encoding and decoding signals
CN101828396A (en) * 2007-10-15 2010-09-08 汤姆森特许公司 Apparatus and method for communicating burst mode activity
CA2701688A1 (en) 2007-10-15 2009-04-23 Thomson Licensing Apparatus and method for encoding and decoding signals
KR101057365B1 (en) 2009-07-23 2011-08-17 (주)파인텔레콤 Preamble detection method for a burst-mode packet transmission system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985004999A1 (en) * 1984-04-17 1985-11-07 Harris Corporation Technique for acquiring timing and frequency synchronization for modem utilizing known (non-data) symbols as part of their normal transmitted data format
WO1986003356A1 (en) * 1984-11-22 1986-06-05 Devon County Council Data modem system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993956A (en) * 1975-11-03 1976-11-23 Motorola, Inc. Digital detection system for differential phase shift keyed signals
US4149121A (en) * 1977-06-23 1979-04-10 Ncr Corporation Four phase to two phase correlator
US4146841A (en) * 1977-09-28 1979-03-27 Harris Corporation Technique for combatting jitter in multiple phase transmission system
US4164036A (en) * 1977-12-07 1979-08-07 Honeywell Inc. Quadrature correlation phase reversal pulse detector
US4397039A (en) * 1980-12-29 1983-08-02 International Business Machines Corporation Instantaneous phase tracking in single sideband systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985004999A1 (en) * 1984-04-17 1985-11-07 Harris Corporation Technique for acquiring timing and frequency synchronization for modem utilizing known (non-data) symbols as part of their normal transmitted data format
WO1986003356A1 (en) * 1984-11-22 1986-06-05 Devon County Council Data modem system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE NTC'72, CONFERENCE RECORD, Houston, Texas, December 1972, pages 20D-1/20D-6, IEEE, New York, US; J.N. BIRCH: "Comparison of coherent and noncoherent detection of phase continuous binary FM signals" *

Cited By (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5402449A (en) * 1989-08-11 1995-03-28 Siemens Aktiengesellschaft Process and device for converting digitally modulate high-frequency reception signals
WO1991002421A1 (en) * 1989-08-11 1991-02-21 SIEMENS AKTIENGESELLSCHAFT öSTERREICH Process and device for converting digitally modulated high-frequency reception signals
EP0487701A1 (en) * 1990-06-15 1992-06-03 AlliedSignal Inc. Signal acquisition
EP0487701A4 (en) * 1990-06-15 1993-08-11 Sundstrand Data Control, Inc. Signal acquisition
US5337331A (en) * 1991-01-31 1994-08-09 Alcatel Telspace Method of coherent demodulation for phase shift keying and a device for implementing the method
FR2672454A1 (en) * 1991-01-31 1992-08-07 Alcatel Telspace A demodulating method for coherent modulation and a phase displacement óoeuvre formatting device of the method.
EP0498704A1 (en) * 1991-01-31 1992-08-12 Alcatel Telspace Method for the coherent demodulation of PSK and apparatus for the implementation of the method
EP0497424A3 (en) * 1991-01-31 1992-10-28 Deutsche Thomson-Brandt Gmbh Broadcast receiver including a nicam or dab decoder
EP0497424A2 (en) * 1991-01-31 1992-08-05 Deutsche Thomson-Brandt GmbH Broadcast receiver including a NICAM or DAB decoder
WO1992014326A1 (en) * 1991-01-31 1992-08-20 Alcatel Telspace Coherent demodulation process for phase shift modulation and device for carrying out same
EP0503632A2 (en) * 1991-03-14 1992-09-16 Fujitsu Limited Delay detector for QPSK signals
EP0503632A3 (en) * 1991-03-14 1993-03-17 Fujitsu Limited Delay detector for qpsk signals
US5317602A (en) * 1991-03-14 1994-05-31 Fujitsu Limited Base-band delayed detector with synchronizing circuit
EP0527249A1 (en) * 1991-08-09 1993-02-17 Nec Corporation Carrier recovery apparatus for digital satellite communication system
EP0614582A4 (en) * 1991-11-27 1994-11-09 Communications Satellite Corp Digital demodulator for preamble-less burst communications.
EP0614582A1 (en) * 1991-11-27 1994-09-14 Communications Satellite Corporation Digital demodulator for preamble-less burst communications
ES2071554A1 (en) * 1992-12-30 1995-06-16 Alcatel Standard Electrica Method and device data recovery in communication systems bursty.
FR2706711A1 (en) * 1993-06-17 1994-12-23 Matra Communication Method and digital signal demodulation apparatus.
WO1995001034A1 (en) * 1993-06-17 1995-01-05 Matra Communication Digital signal demodulation method and device
US5640125A (en) * 1993-06-17 1997-06-17 Matra Communication Digital PSK-type demodulator having clock recovery before carrier recovery
EP0632610A1 (en) * 1993-06-29 1995-01-04 Alcatel Telspace Apparatus for detecting unique words in a BPSK-TDMA system
US5548618A (en) * 1993-06-29 1996-08-20 Alcatel Telspace Device for detecting BPSK modulated singular words suitable for a TDMA analog modem and detection method used therein
FR2707128A1 (en) * 1993-06-29 1995-01-06 Alcatel Telspace Device unique word detecting modulated BPSK adapted to an analog modem operating in TDMA mode and method of detection set Óoeuvre in such a device.
EP0757461A2 (en) * 1995-07-31 1997-02-05 Harris Corporation Method of estimating signal quality for a direct sequence spread spectrum receiver
EP0757461A3 (en) * 1995-07-31 1997-09-03 Harris Corp Method of estimating signal quality for a direct sequence spread spectrum receiver
EP0805573A2 (en) * 1996-04-30 1997-11-05 Advantest Corporation Method for measuring modulation parameters of digital quadrature-modulated signal
EP0805573A3 (en) * 1996-04-30 1999-12-01 Advantest Corporation Method for measuring modulation parameters of digital quadrature-modulated signal
FR2773029A1 (en) * 1997-12-23 1999-06-25 Telecommunications Sa Method of synchronizing a receiver on digital data transmitted in packets
EP0926858A1 (en) * 1997-12-23 1999-06-30 Sagem Sa Method for synchronizing a receiver on digital packet data
US6961314B1 (en) 1998-10-30 2005-11-01 Broadcom Corporation Burst receiver for cable modem system
WO2000028712A3 (en) * 1998-10-30 2000-11-23 Broadcom Corp Cable modem system
US8005072B2 (en) 1998-10-30 2011-08-23 Broadcom Corporation Synchronization of multiple base stations in a wireless communication system
US7899034B2 (en) 1998-10-30 2011-03-01 Broadcom Corporation Methods for the synchronization of multiple base stations in a wireless communication system
US7843847B2 (en) 1998-10-30 2010-11-30 Broadcom Corporation Compensating for noise in a wireless communication system
US6650624B1 (en) 1998-10-30 2003-11-18 Broadcom Corporation Cable modem apparatus and method
WO2000028712A2 (en) * 1998-10-30 2000-05-18 Broadcom Corporation Cable modem system
US6965616B1 (en) 1998-10-30 2005-11-15 Broadcom Corporation Network data transmission synchronization system and method
US7103065B1 (en) 1998-10-30 2006-09-05 Broadcom Corporation Data packet fragmentation in a cable modem system
US7120123B1 (en) 1998-10-30 2006-10-10 Broadcom Corporation Pre-equalization technique for upstream communication between cable modem and headend
US7139283B2 (en) 1998-10-30 2006-11-21 Broadcom Corporation Robust techniques for optimal upstream communication between cable modem subscribers and a headend
US7512154B2 (en) 1998-10-30 2009-03-31 Broadcom Corporation Data packet fragmentation in a wireless communication system
US7519082B2 (en) 1998-10-30 2009-04-14 Broadcom Corporation Data packet fragmentation in a wireless communication system
US7821954B2 (en) 1998-10-30 2010-10-26 Broadcom Corporation Methods to compensate for noise in a wireless communication system
US9301310B2 (en) 1998-10-30 2016-03-29 Broadcom Corporation Robust techniques for upstream communication between subscriber stations and a base station
WO2002005474A1 (en) * 2000-07-07 2002-01-17 Cleansun Pty Ltd Data communications method
EP1213872A3 (en) * 2000-12-05 2002-07-03 Philips Electronics N.V. Recovery of a packet in a packet transmission system with return link
EP1213872A2 (en) * 2000-12-05 2002-06-12 Philips Electronics N.V. Recovery of a packet in a packet transmission system with return link

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US5012491A (en) 1991-04-30 grant
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