EP0353779B1

EP0353779B1 - Preamble detection circuit for digital communications system

Info

Publication number: EP0353779B1
Application number: EP89114484A
Authority: EP
Inventors: Motoya C/O Nec Corporation Iwasaki
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1988-08-05
Filing date: 1989-08-04
Publication date: 1995-11-02
Anticipated expiration: 2009-08-04
Also published as: DE68924677T2; EP0353779A2; US5012491A; DE68924677D1; AU3939389A; JPH0716206B2; AU624404B2; JPH0244947A; EP0353779A3

Description

The present invention relates generally to burst mode digital communications systems, and more specifically it relates to a technique for reducing the amount of information contained in the preamble of each burst transmission that is necessary for recovering carrier and clock timing at a receiving end of the system.
In a burst mode of digital transmission, a preamble is transmitted at the beginning of each burst transmission to convey information as to the carrier and symbol clock timing of a modulator to allow receiving stations to establish correct timing relationships with the carrier and symbol clock of the modulator. The preamble is made up of a carrier recovery field and a clock recovery field that follows. On receiving a preamble, the receiver's function is to first analyze the carrier recovery field to establish correct timing with the carrier of the modulator and then proceed to the clock recovery field to establish proper symbol clock timing. In addition, an automatic gain control signal is derived from the received signal after the clock recovery procedure is complete.
Because of the sequential operations, the time taken to process the preamble is substantial and hence the transmission efficiency of the current burst mode of digital communications system is low. WO-A-85/04999 discloses a signal processing scheme for synchronizing the receiver to the transmitted data signals. A replica of the known signal bursts is (complex) correlated with the incoming signal to locate and lock onto a known (PN) reference symbol burst.
It is therefore an object of the present invention to provide a preamble detection circuit that requires a small amount of preamble information for establishing carrier and clock timing and controlling preamplifier gain by deriving error control signals simultaneously during the reception of a preamble. This object is solved with the features of the claims.
According to one aspect of the present invention, a preamble detection circuit is provided. At a transmitter, a preamble containing a predetermined bit pattern and a digital signal are modulated upon orthogonal carriers and transmitted in a series of burst signals. The preamble detection circuit noncoherently ("pseudo-synchronously") detects the preamble and digital signal with locally generated orthogonal carriers having the same frequency as the transmitted orthogonal carriers to produce in-phase and quadrature signals. The locally generated carriers tend to deviate in phase from the transmitted orthogonal carriers over a predetermined range. First and second correlators are provided to perform a correlation calculation between a locally generated bit pattern which corresponds to the bit pattern of the preamble and the in-phase signal and to perform a correlation calculation between the locally generated bit pattern and the quadrature signal. A phase error of the locally generated orthogonal carriers with respect to the transmitted carriers is detected from the outputs of the first and second correlators. A clock phase error of a locally generated clock pulse with respect to transmitted symbols is detected from one of the outputs of the correlators. Power level detector is preferably connected to the outputs of the correlators for detecting a power level of the received burst signals.
Since the carrier and clock phase error detection and the power level detection can be performed in a parallel fashion, the amount of information contained in the preamble can be reduced.
According to a second aspect, a digital communication system incorporating the preamble detection circuit is provided. The system includes a gain-controlled amplifier for amplifying burst signals received from a transmitter station with a gain controlled with the power level detected by the power level detector. A symbol clock generator generates a local clock pulse at a symbol rate of the transmitted burst signals. First and second decision circuits, or A/D converters, are responsive to the local clock pulse for sampling the in-phase and quadrature output signals from the correlators. A clock phase error detector is connected to one of the outputs of the correlators and to the output of the symbol clock generator for detecting a phase error of the local clock pulse with respect to symbols of the transmitted burst signals and controlling the symbol clock generator with the detected phase error. A carrier generator generates second local orthogonal carriers. Using the second local carriers, a synchronous detector provides synchronous detection on output signals from the first and second decision circuits. A carrier phase error detector is connected to the outputs of the first and second correlators for detecting a phase error of the local orthogonal carriers with respect to the transmitted carriers and controlling the carrier generator with the detected phase error.
The present invention will be described in further detail with reference to the accompanying drawings, in which:

Fig. 1 is a block diagram of a receiving station of a digital communication system according to an embodiment of the present invention;
Fig. 2 shows a data structure of a burst transmission employed in the present invention;
Fig. 3 shows details of the error detection circuit of Fig. 1, including the power level detector, clock phase error detector and carrier phase error detector;
Fig. 4 shows a waveform of a portion of the preamble of a modulated QPSK incoming signal;
Fig. 5 shows a portion of the locally generated predetermined bit pattern supplied to the correlators of Fig. 1;
Fig. 6 shows a portion of the waveform of the output signal of one of correlators of Fig. 1; and
Figs. 7-9 are illustrations of the outputs of the clock phase error detector, carrier phase error detector and power level detector of Fig. 3, respectively.

Referring now to Fig. 1, there is shown a receiving station of a burst mode digital radio communication system according to an embodiment of the present invention. Through an input terminal 10 the station receives a transmitted burst of a QPSK (quadrature phase-shift keying) signal which comprises a preamble and a data field as shown in Fig. 2. The preamble contains a sequence of +1 and -1 binary logic values of a predetermined number which alternate at symbol clock intervals T. No discrimination is made between a carrier recovery field and a clock recovery field as in the format of the prior art preamble.
The preamble of each burst transmission at terminal 10 has a waveform M(t) which is represented by m(t)(cos ω_ct + sin ω_ct) as illustrated in Fig. 4, where m(t) is +1 for t=2nT, -1 for t=(2n+1)T and 0 for $t=(n+ \frac{1}{2})T,$
and ω_c is the angle frequency of the carrier of the burst signal and n is an integer including zero. The signal contained in the preamble is passed through a gain-controlled preamplifier stage 11 to a QPSK (quadriphase shift keying) demodulator 12. This demodulator is provided with a local oscillator which independently generates orthogonal carriers having the same frequency as the transmitted carriers without receiving frequency and phase control signals from external sources. The local carriers may deviate in phase from the transmitted carriers in a range between -π and +π. Therefore, the incoming signal is demodulated in a "pseudo-synchronous mode", or noncoherent detection mode to recover the following in-phase and quadrature components I(t) and Q(t): $I(t) = \frac{1}{2} m(t)(cos Δϑ - sin Δϑ)$
$Q(t)= \frac{1}{2} m(t)(cos Δϑ + sin Δϑ)$

These components appear at the inputs of correlators 13 and 14, respectively.
A pattern generator 15 is provided to supply to the correlators 13 and 14 a sequence V(T) of symbol bits which is given by the following relation:

where N is the number of symbol bits contained in the preamble, δ(t) is the delta function, and V_n assumes +1 for n=4k or 4k+1 or -1 for n=4k+2 or 4k+3 (where k is an integer including zero). Therefore, V_n is a series of 2N symbols of +1, +1, -1, -1, +1, +1, .....-1, -1 as shown Fig. 5.
Each of the correlators 13 and 14 performs correlation calculation to produce output signals I′(t) and Q′(t), respectively, which are given by:
Since m(t) is given by the following equations: $m(t-2kT) = m(t)$
$m{t - (2k+1)T} = -m(t)$
$m(t - \frac{T}{2} - 2kT)= m(t - \frac{T}{2})$
$m{t - \frac{T}{2} -(2k+1)T} = -m(t - \frac{T}{2})$

the in-phase and quadrature signals I′(t) and Q′(t) during the reception of a preamble can be represented by: $I′(t) = N[m(t) + m(t - \frac{T}{2})] (cos Δϑ - sin Δϑ)$
$Q′(t) = N[m(t) + m(t - \frac{T}{2})] (cos Δϑ + sin Δϑ)$

Fig. 6 depicts the waveform of the in-phase signal I′(t) as a result of the correlation calculation between the symbols from the pattern generator 15 and those of the preamble contained in the in-phase signal I(t). A similar waveform is derived from the correlation calculation between the symbols from the pattern generator 15 and those of the preamble contained in the quadrature signal Q(t). The outputs of the correlators 13 and 14 are coupled to an error detection circuit including a power level detector 16, a clock phase error detector 17 and a carrier phase error detector 18. Details of the detector circuits 16, 17 and 18 will be described with reference to Fig. 3.
On the other hand, the outputs of demodulator 12 are further coupled to analog-to- digital converters 20 and 21, respectively, to produce digital versions of the in-phase and quadrature signals I(t) and Q(t) for coupling to a synchronous detector 22. Sampling pulses are supplied to the A/ D converters 20 and 21 at symbol clock timing from a dosed loop including a clock frequency error detector 23 coupled to one output terminal of the synchronous detector 22 and a voltage-controlled oscillator 24 which is responsive to a frequency error from the detector 23 as well as to a phase error supplied from the clock phase error detector 17. Clock frequency error detector 23 includes a zero-crossing detector and a loop filter to generate a signal representative of a frequency deviation of the VCO 24 from the transmitted symbol clock frequency.
Orthogonal reference carriers for the synchronous detector 22 are obtained by a closed loop formed by a carrier frequency error detector 25 coupled to the outputs of synchronous detector 22 which respectively lead to output terminals 28I and 28Q, a voltage-controlled oscillator 26 responsive to the outputs of the frequency error detector 25 as well as to a carrier phase error supplied from the phase error detector 18, and a π/2 phase shifter 27 coupled to the VCO 26. Carrier frequency error detector 25 includes a phase discriminator coupled to the outputs of synchronous detector 22 and a loop filter to generate a signal representative of a frequency deviation of the VCO 26 from an intended value.
A gain control circuit 19 is provided to respond to the outputs of power level detector 16 and VCO 24 by maintaining the output power level of preamplifier stage 11 at a constant level.
As shown in Fig. 3, clock phase error detector 17 comprises D flip- flops 33 and 34 whose data inputs are coupled to one of the outputs of correlators 13 and 14. The output of VCO 24 is supplied to the clock input of flip-flop 33 through a delay circuit 35 that introduces a half-symbol interval (=T/2) on the one hand, and directly to the clock input of flip-flop 34 on the other. The output of flip-flop 33 is coupled to one input of a multiplier 37 and the output of flip-flop 34 is coupled to a sign-code detector 36 whose output is connected to the other input of multiplier 37. The output of multiplier 37 is representative of a phase error of the symbol clock timing and fed to the phase control input of the VCO 24. Assume that there is a phase delay of ΔT in the local symbol clock from VCO 24 with respect to that of the incoming signal, the sampling of the input signal I′(t) by flip-flop 34 in response to the local symbol clock results in the generation of a sample value I′_n which is given by: ${I′}_{n} = I′(nT + ΔT)$

where, 0 ≦ ΔT < T. On the other hand, the sampling of the signal I′(t) by flip-flop 33 in response to the output of delay circuit 35 results in the generation of a sample value I˝_n which is given by: ${I˝}_{n} = I′(nT + \frac{T}{2} + ΔT)$

Typical examples of the sample values I′_n and I˝_n are respectively indicated by blank and solid dots in Fig. 6. Sign-code detector 36 produces a signal SGN (I′_n) which is multiplied by I˝_n by multiplier 37 to produce a clock phase error signal which is given by: ${R = SGN (I′}_{n} {) I˝}_{n}$

where SGN (·) denotes the signum function. This signal varies exclusively as a function of symbol clock phase error ΔT as shown in Fig. 7.
Carrier phase error detector 18 is formed by a dividing circuit 38 that performs division calculation Q′/I′ on the signals from the correlators 13 and 14 and supplies the result of the calculation to an arctangent calculator 39, which calculates the following equation: $S = tan⁻¹ [\frac{Q′}{I′}] = tan⁻¹ [\frac{cos Δϑ + sin Δϑ}{cos Δϑ - sin Δϑ}] = tan⁻¹ [\frac{sin (Δϑ + π/4)}{cos (Δϑ + π/4)}] = Δϑ + π/4$

As illustrated in Fig. 8, the output of the arctangent calculator 39 is a signal that varies as a linear function of phase error Δϑ. The output of arctangent calculator 39 is fed to a subtractor 40 where π/4 is subtracted. The output of subtractor 40 is applied to VCO 26 as a carrier phase error.
Power level detector 16 includes squaring circuits 30 and 31 respectively coupled to the outputs of correlators 13 and 14 to generate squared values I′(t) and Q′(t). An adder 32 adds up the squared signals [I′(t)]² and [Q′(t)]² to produce a signal P(t) which is given by: $P(t) = [I′(t)]² + [Q′(t)]² = 2N² [m(t) + m(t - \frac{T}{2})]²$

and supplies the sum as a gain control signal to the gain control circuit 19. As shown in Fig. 9, the gain control signal varies exclusively with the amplitude m(t) of the incoming signal and represents its signal power.
The operation of gain control circuit 19 is based on the sampling of the output of power level detector 16 in response to the output of VCO 24 so that the sampled value is a faithful representation of power level at the time the phase error control signal ΔT is generated. The gain and phase error control signals can therefore be derived in a short period of time and hence the amount of information contained in the preamble of each burst transmission can be reduced to achieve high transmission efficiency.
The system operates satisfactorily with the local oscillator included in the orthogonal demodulator 12 of the type mentioned above if the amount of time necessary for error detection is much less than a period 1/Δf, (where Δf represents the frequency deviation of the local oscillator of demodulator 12 from the carrier frequency of the incoming signal).
According to another feature of the invention, the use of correlators 13 and 14 ensures high signal-to-noise ratio at their outputs by as much as {(10/2)log₁₀N} dB. This is advantageous for the error detection circuit to derive control signals.
The foregoing description shows only one preferred embodiment of the present invention Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiment shown and described is only illustrative, not restrictive.

Claims

A preamble detection circuit for a transmission system in which a preamble and a digital signal are modulated upon orthogonal carriers and transmitted in a series of burst signals, said preamble containing a predetermined bit pattern, comprising:
orthogonal demodulator means (12) for receiving the transmitted burst signals and noncoherently detecting the preamble and the digital signal with local orthogonal carriers having the same frequency as the frequency of the transmitted orthogonal carriers, said local orthogonal carriers tending to deviate in phase over a predetermined range from the transmitted orthogonal carriers, said orthogonal demodulator means generating in-phase and quadrature output signals;
means (15) for generating a local bit pattern corresponding to the bit pattern contained in said preamble;
first and second correlators (13, 14), the first correlator (13) providing a correlation calculation between the local bit pattern and the in-phase output signal and the second correlator (14) providing a correlation calculation between the local bit pattern and the quadrature output signal;
carrier phase error detector means (18) connected to the outputs of the first and second correlators (13, 14) for detecting a phase error of the local orthogonal carriers with respect to the transmitted carriers;
symbol clock generator means (24) for generating a local clock pulse at a symbol rate of the transmitted burst signals; and
clock phase error detector means (17) connected to one (13) of the outputs of the first and second correlators and to the output of the symbol clock generator means (24) for detecting a phase error (ΔT) of the local clock pulse with respect to symbols contained in the transmitted burst signals and controlling the symbol clock generator means (24) with the detected phase error (ΔT).
A preamble detection circuit as claimed in claim 1, further comprising power level detector means (16) connected to the outputs of the first and second correlators (13, 14) for detecting a power level of the received burst signals.
A preamble detection circuit as claimed in claim 1 or 2, wherein the bit pattern contained in the preamble is a series of alternating binary logic values.
A preamble detection circuit as claimed in any one of claims 1 to 3, wherein the carrier phase error detector means (18) comprises:
a division circuit (38) for providing a division calculation between the in-phase and quadrature output signals to produce a quotient; and
arctangent calculator means (39) for determining the arctangent of the quotient.
A preamble detection circuit as claimed in any one of claims 1 to 4, wherein the clock phase error detector means (17) comprises:
delay means (35) for delaying the local clock pulse by an amount corresponding to one-half the interval between successive symbols contained in the transmitted burst signals;
first sampling means (33) for sampling one of the in-phase and quadrature output signals in response to the delayed local clock pulse;
second sampling means (34) for sampling the one of said in-phase and quadrature output signals in response to the local clock pulse;
symbol detector means (36) for detecting a predetermined symbol from the output of the second sampling means (34); and
multiplier means (37) for generating a signal representative of a product of the output of the first sampling means and the predetermined symbol.
A digital communication system in which a preamble and a digital signal are modulated upon orthogonal carriers and transmitted to a distant end of the system in a series of burst signals, the preamble containing a predetermined bit pattern for carrier and clock recovery at the distant end of the system, comprising at the distant end a preamble detection circuit according to claim 2, 3, 4 or 5 and having gain-controlled amplifier means (11) for receiving the transmitted burst signals, amplifying the received signals, and supplying the amplified signals to the orthogonal demodulator means (12);
first and second decision circuits responsive to the local clock pulse for respectively sampling the in-phase and quadrature output signals;
carrier generator means (26) for generating second local orthogonal carriers; and
synchronous detector means (22) for providing synchronous detection on output signals from the first and second decision circuits with the second local orthogonal carriers; wherein the carrier phase error detector means (25) controls the carrier generator means (26) with the detected phase error; and
the power level detector means (16) controls the gain-controlled amplifier means (11) with the detected power level.
A digital communication system as claimed in claim 6, further comprising means (19) for sampling the detected power level in response to the local clock pulse and supplying the sampled power level to the gain-controlled amplifier means (11) as said detected power level.