EP0353249A1 - Architecture de gestion de reseau parallele - Google Patents

Architecture de gestion de reseau parallele

Info

Publication number
EP0353249A1
EP0353249A1 EP88904083A EP88904083A EP0353249A1 EP 0353249 A1 EP0353249 A1 EP 0353249A1 EP 88904083 A EP88904083 A EP 88904083A EP 88904083 A EP88904083 A EP 88904083A EP 0353249 A1 EP0353249 A1 EP 0353249A1
Authority
EP
European Patent Office
Prior art keywords
data
switch
receiving
transmitted
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88904083A
Other languages
German (de)
English (en)
Other versions
EP0353249A4 (en
Inventor
Douglas M. Pihl
Gary D. Connell
John M. Hedin
Blair A. Wilson
John D. Hardy, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LEE DATA CORP
Original Assignee
LEE DATA CORP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LEE DATA CORP filed Critical LEE DATA CORP
Publication of EP0353249A1 publication Critical patent/EP0353249A1/fr
Publication of EP0353249A4 publication Critical patent/EP0353249A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

Abstract

Nouvelle architecture de transmission de données numériques mettant en oeuvre un concept de gestion de réseau pouvant être utilisé pour interconnecter en parallèle, simultanément, les nombreuses ressources et installations normalement interconnectées à un ou plusieurs systèmes d'ordinateurs centraux (24, 25). Comme le circuit logique adaptateur (20) et le commutateur de distribution de matrice (30) servent uniquement à interconnecter un dispositif demandeur (29, 35) au dispositif récepteur de destination (29, 35), l'invention peut être utilisée dans n'importe quel environnement de transmission de données, dans lequel n'importe lequel des trois dispositifs de transmission de données ou plus (29, 35) sont agencés pour transmettre vers n'importe lequel des dispositifs interconnectés (29, 35). Comme le commutateur NxN (30) est agencé pour établir un itinéraire d'accès séparé pour chaque dispositif demandant une transmission, un traitement parallèle indépendant est possible.
EP19880904083 1987-04-06 1988-04-01 Parallel networking architecture Withdrawn EP0353249A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3488187A 1987-04-06 1987-04-06
US34881 1987-04-06

Publications (2)

Publication Number Publication Date
EP0353249A1 true EP0353249A1 (fr) 1990-02-07
EP0353249A4 EP0353249A4 (en) 1992-01-08

Family

ID=21879186

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880904083 Withdrawn EP0353249A4 (en) 1987-04-06 1988-04-01 Parallel networking architecture

Country Status (3)

Country Link
EP (1) EP0353249A4 (fr)
JP (1) JPH02503366A (fr)
WO (1) WO1988008167A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2011935A1 (fr) * 1989-04-07 1990-10-07 Desiree A. Awiszio Systeme d'interconnexion d'ordinateurs a deux trajets a controleur de memoire a paquets a quatre ports
US5410649A (en) * 1989-11-17 1995-04-25 Texas Instruments Incorporated Imaging computer system and network
US5522083A (en) * 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
EP0429733B1 (fr) * 1989-11-17 1999-04-28 Texas Instruments Incorporated Multiprocesseur avec commutateur à coordonnées entre processeurs et mémoires
US6038584A (en) * 1989-11-17 2000-03-14 Texas Instruments Incorporated Synchronized MIMD multi-processing system and method of operation
US5339447A (en) * 1989-11-17 1994-08-16 Texas Instruments Incorporated Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data
US6070003A (en) * 1989-11-17 2000-05-30 Texas Instruments Incorporated System and method of memory access in apparatus having plural processors and plural memories
JPH052570A (ja) * 1991-06-25 1993-01-08 Gurafuiko:Kk クロスバースイツチおよびそれを使用した並列処理装置
EP0597205B1 (fr) * 1992-09-07 2003-04-09 Hitachi, Ltd. Système multiprocesseur et procédé de communication entre des processeurs
US5613067A (en) * 1993-12-30 1997-03-18 International Business Machines Corporation Method and apparatus for assuring that multiple messages in a multi-node network are assured fair access to an outgoing data stream
JPH08191951A (ja) * 1995-01-17 1996-07-30 Sony Corp ゲーム機およびその中継器
US6651104B1 (en) * 1996-11-12 2003-11-18 Ericsson Inc. Multi-layered interface for interconnecting application programs to system bus lines for electronic devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005272A (en) * 1974-08-14 1977-01-25 Arthur A. Collins, Inc. Time folded TST (time space time) switch
US4389642A (en) * 1981-07-01 1983-06-21 Kahn William M Digital matrix switching
NL8104358A (nl) * 1981-09-22 1983-04-18 Nederlanden Staat Werkwijze en inrichting voor het besturen van een schakelnetwerk.
JPS58220541A (ja) * 1982-06-17 1983-12-22 Toshiba Corp 端末回線切替え装置
US4539564A (en) * 1982-08-04 1985-09-03 Smithson G Ronald Electronically controlled interconnection system
US4553203A (en) * 1982-09-28 1985-11-12 Trw Inc. Easily schedulable horizontal computer
GB8329728D0 (en) * 1983-11-08 1983-12-14 Cripps M D Interconnection networks
US4633245A (en) * 1983-12-30 1986-12-30 International Business Machines Corporation Local area network interconnect switching system
GB2175176A (en) * 1985-05-10 1986-11-19 Philips Electronic And Assaoci Signal transmission arrangement, a transmitter and a receiver for such an arrangement and a communication system including such an arrangement

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
No further relevant documents have been disclosed. *
See also references of WO8808167A1 *

Also Published As

Publication number Publication date
WO1988008167A1 (fr) 1988-10-20
JPH02503366A (ja) 1990-10-11
EP0353249A4 (en) 1992-01-08

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