Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
  • H10D84/65—Integrated injection logic

Definitions

• This inventor relates to Integrated Injection Logic (P 2 L) gates.
• I 2 L gates are used extensively in integrated circuit logic and memory designs. It's popularity is due to its compatibility with bipolar transistor processes, relatively simple layout and reasonably high packing density.
• FIG. 1 of the accompanying drawings shows a circuit diagram and a schematic cross-section of a typical I 2 L gate.
• a buried N+ layer 10 acts as a base for a lateral pnp transistor Q 1 and as a common emitter for a vertical npn transistor Q 2 having a plurality of collectors.
• the collector of transistor Q 1 is an isolated P+ region 11 and the collectors of transistor Q2 are isolated N+ regions 12 in a P region 13 (which also acts as the collector of transistor Q 1 ).
• the injector, base and collector contacts are located in wells etched in an SIO 2 layer.
• Figures 2 (1 ), 2 (1 1 ) and 3 are schematic plan views of I 2 L devices of single collector, non-walled (figure 2 (1 )). single collector, walled contact areas (Figure 2 (11)) and multiple collector, non walled ( Figure 3) I 2 L devices known in the prior art. The contacts and doped areas of these devices are as indicated by the legend of Figure 2.
• a disadvantage of such devices is that collector fan out is limited due to the resistance of the P area forming the base of the transistor Q 2 .
• a fan out of three is possibly provided that the bases of the driven devices are substantially equidistant and the metal routes thereto are kept short.
• the device of figure 3 will thus support three devices for each collector. As the number of collectors is increased, however, the resistance R BB is high due to the P substrate. Thus a large P area also reduces gain and is a detrimental factor in the speed/power product.
• an integrated injection logic device comprising a substrate having a buried N+ layer, an isolated P+ layer and a common P region providing base and collector areas, and wherein the common P region is comb shaped and has its back bone and first tooth forming a base region doped to a P+ level and at least a further tooth doped to a P level with an overlying N+ layer forming a collector region.
• Figure 4 is a schematic plan view of an improved integrated injection logic gate in accordance with the present invention.
• Figure 5 is a diagrammatic plan view of an advantageous gate arrangement.
• an Integrated Injection Logic ( I 2 L) device in accordance with the present invention, comprises a substrate of a semiconductor material having a common buried N+ layer and an isolated P+ region 33 for the injector as in the prior art.
• the P layer of the prior art (See Figure 1) is replaced by a comb-shaped layer of P material produced by appropriate masking and doping.
• the back bone 37 and a first tooth 39 of the comb are masked and doped to a P+ level.
• a contact is made to the P+ layer constituting the first tooth 39 to provide a base 35 for the device.
• third and further teeth 41 of the comb are masked and doped to a P level, and, thereafter, are doped to provide superjacent N+ layers. Contacts are made to the N+ layers to form the collectors of the device .
• the contacts to the injector 33, the base 35 and the collectors 45 may be effected in respective wells etched in a top layer of S i O 2 on the substrate.
• the doping may be effected in such manner that the whole comb shaped structure is doped to P level and thereafter masked and further doped to the P+ level in the region of the back bone 37 and first tooth 39.
• the whole comb shaped structure may be doped to the P+ level, and thereafter, doping with the N+ material in the regions of the second and subsequent teeth 41 be effected to leave a subjacent P layer.
• gates have an injector for each base and collector or collectors.
• the layout is rearranged ( Figure 5 (1 )) so that the or each injector is common to a pair of bases and collectors.
• each injector 50 has a base 52 and a collector 54 at each side thereof.
• a chip area saving approaching 20% can thus be acheived.
• the invention is not confined to the precise details of the foregoing examples and variations may be made thereto. For instance, as conduction within the P+ layer is higher than that in a P layer, each collector may have a greater fan out with less restriction on the driven devices. Further, more collectors, per device, can be provided as the base resistance is reduced.

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• Bipolar Integrated Circuits (AREA)

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• 1987
  • 1987-12-17 GB GB878729417A patent/GB8729417D0/en active Pending
• 1988
  • 1988-12-01 WO PCT/GB1988/001051 patent/WO1989006049A1/en not_active Ceased
  • 1988-12-01 JP JP1500940A patent/JPH04501341A/ja active Pending
  • 1988-12-01 EP EP89900278A patent/EP0349622A1/de not_active Withdrawn

Non-Patent Citations (1)

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