WO1989006049A1

WO1989006049A1 - Logic gate

Info

Publication number: WO1989006049A1
Application number: PCT/GB1988/001051
Authority: WO
Inventors: Nicholas Paul Cowley
Original assignee: Plessey Overseas Limited
Priority date: 1987-12-17
Filing date: 1988-12-01
Publication date: 1989-06-29
Also published as: JPH04501341A; EP0349622A1; GB8729417D0

Abstract

The invention provides an I2L device in which a P+ region forms a collector of the injector and further provides an extended connection to one or more P- regions forming the base of the virtual transistor or transistors of the device.

Description

LOGIC GATE

This inventor relates to Integrated Injection Logic (P²L) gates.

I²L gates are used extensively in integrated circuit logic and memory designs. It's popularity is due to its compatibility with bipolar transistor processes, relatively simple layout and reasonably high packing density.

Figure 1 of the accompanying drawings, shows a circuit diagram and a schematic cross-section of a typical I²L gate. A buried N+ layer 10 acts as a base for a lateral pnp transistor Q ₁ and as a common emitter for a vertical npn transistor Q₂ having a plurality of collectors. The collector of transistor Q₁ is an isolated P+ region 11 and the collectors of transistor Q2 are isolated N+ regions 12 in a P region 13 (which also acts as the collector of transistor Q ₁ ). The injector, base and collector contacts are located in wells etched in an SIO₂ layer.

Figures 2 (1 ), 2 (1 1 ) and 3 are schematic plan views of I²L devices of single collector, non-walled (figure 2 (1 )). single collector, walled contact areas (Figure 2 (11)) and multiple collector, non walled (Figure 3) I²L devices known in the prior art. The contacts and doped areas of these devices are as indicated by the legend of Figure 2.

A disadvantage of such devices is that collector fan out is limited due to the resistance of the P area forming the base of the transistor Q₂. A fan out of three is possibly provided that the bases of the driven devices are substantially equidistant and the metal routes thereto are kept short. The device of figure 3 will thus support three devices for each collector. As the number of collectors is increased, however, the resistance R_BB is high due to the P substrate. Thus a large P area also reduces gain and is a detrimental factor in the speed/power product.

It is an object of the present invention to provide an I²L gate wherein the aforesaid disadvantages are minimised.

According to the present invention, there is provided an integrated injection logic device comprising a substrate having a buried N+ layer, an isolated P+ layer and a common P region providing base and collector areas, and wherein the common P region is comb shaped and has its back bone and first tooth forming a base region doped to a P+ level and at least a further tooth doped to a P level with an overlying N+ layer forming a collector region.

The invention will be described further, by way of example, with reference to figures 4 and 5 of the accompanying drawings, in which:-

Figure 4 is a schematic plan view of an improved integrated injection logic gate in accordance with the present invention: and,

Figure 5 is a diagrammatic plan view of an advantageous gate arrangement.

Referring firstly to Figure 4, an Integrated Injection Logic ( I²L) device, in accordance with the present invention, comprises a substrate of a semiconductor material having a common buried N+ layer and an isolated P+ region 33 for the injector as in the prior art. In accordance with the present invention, the P layer of the prior art (See Figure 1) is replaced by a comb-shaped layer of P material produced by appropriate masking and doping. The back bone 37 and a first tooth 39 of the comb are masked and doped to a P+ level. A contact is made to the P+ layer constituting the first tooth 39 to provide a base 35 for the device. Second, third and further teeth 41 of the comb are masked and doped to a P level, and, thereafter, are doped to provide superjacent N+ layers. Contacts are made to the N+ layers to form the collectors of the device . The contacts to the injector 33, the base 35 and the collectors 45 may be effected in respective wells etched in a top layer of S_iO₂ on the substrate.

It will be appreciated that the doping may be effected in such manner that the whole comb shaped structure is doped to P level and thereafter masked and further doped to the P+ level in the region of the back bone 37 and first tooth 39. Alternatively, the whole comb shaped structure may be doped to the P+ level, and thereafter, doping with the N+ material in the regions of the second and subsequent teeth 41 be effected to leave a subjacent P layer.

The arrangement shown in Figure 5 may, with advantage be applied to I²L gates in accordance with the present invention. It is however applicable to other semiconductive devices wherein it similarly provides a saving in overall chip area.

Conventionally, gates (Figures 5(1 )) have an injector for each base and collector or collectors. In accordance with this feature, the layout is rearranged (Figure 5 (1 )) so that the or each injector is common to a pair of bases and collectors.

As shown in Figure 5 (11 ), each injector 50 has a base 52 and a collector 54 at each side thereof. A chip area saving approaching 20% can thus be acheived. The invention is not confined to the precise details of the foregoing examples and variations may be made thereto. For instance, as conduction within the P+ layer is higher than that in a P layer, each collector may have a greater fan out with less restriction on the driven devices. Further, more collectors, per device, can be provided as the base resistance is reduced.

As the area of P material is reduced, gain and speed/power product are increased.

Utilising the arrangement of Figure 5 (11), a greater packing density can be achieved for an integrated circuit employing so arranged devices.

Claims

1 . An integrated injection logic device comprising a substrate having a buried N+ layer, an isolated P+ layer and a common P region providing base and collector areas, and wherein the common P region is comb shaped and has its back bone and first tooth forming a base region doped to a P+ level and at least a further tooth doped to a P level with an overlying N+ layer forming a collector region.

2. A device as claimed in claim 1 comprising a plurality of further teeth each doped to a P level and each having a respective overlying N+ region to define respective collectors.

3. A device as claimed in claim 1 or 2 having a top layer of silicon oxide having wells etched therein in register with the P+ injector region, the P+ base region, and the N+ collector region or regions, and contacts to said regions in the wells.

4. An integrated circuit comprising a plurality of devices each as claimed in claim 1 and wherein an injector of a first of the devices constitutes also the injector of a second of the devices.

5. An integrated circuit comprising two devices as claimed in claim 1 wherein the doped area constituting the isolated P+ layer of one of said two devices acts as the isolated P+ layer of the other device.