EP0332548A1 - Stabilisierter Generator für die Lieferung einer Schwellenspannung für einen MOS-Transistor - Google Patents

Stabilisierter Generator für die Lieferung einer Schwellenspannung für einen MOS-Transistor Download PDF

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Publication number
EP0332548A1
EP0332548A1 EP89420084A EP89420084A EP0332548A1 EP 0332548 A1 EP0332548 A1 EP 0332548A1 EP 89420084 A EP89420084 A EP 89420084A EP 89420084 A EP89420084 A EP 89420084A EP 0332548 A1 EP0332548 A1 EP 0332548A1
Authority
EP
European Patent Office
Prior art keywords
transistor
inverter
voltage
comparator
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89420084A
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English (en)
French (fr)
Other versions
EP0332548B1 (de
Inventor
Antoine Pavlin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
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Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of EP0332548A1 publication Critical patent/EP0332548A1/de
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature

Definitions

  • the present invention relates to the field of integrated circuits of the MOS (metal-oxide-semiconductor) type.
  • FIG. 1 schematically shows such a comparator used in the prior art.
  • This comparator receives on its inputs the two voltages to be compared, the output stage consisting of an inverter 2.
  • a conventional bias voltage supply circuit for comparator 1 comprises two MOS transistors M1 and M2 in series between a power source V DD and ground.
  • the transistor M1 is a depletion MOS transistor and the transistor M2 is an enrichment MOS transistor.
  • the transistor M1 serves as a load and its gate and its source are interconnected while the drain and the gate of the MOS transistor M2 are also interconnected.
  • the bias voltage of comparator 1 is taken from the interconnection point of the transistors M1 and M2.
  • inverter a circuit providing a high output voltage when its input is at low level and vice versa and not a circuit reversing the polarity of the voltages d 'Entrance.
  • FIG. 2 represents in more detail an embodiment of the circuit of FIG. 1 and more particularly of the comparator 1.
  • This comparator comprises two MOS transistors with enhancement M3 and M4 whose gates are connected respectively to V in and to a reference voltage V REF .
  • the drain of transistor M3 is connected to the supply voltage V DD
  • the drain of transistor M4 is connected to this same voltage by means of a depletion MOS transistor serving as load M5, the gate of which is connected to the source .
  • the sources of the transistors M3 and M4 are interconnected and are connected to ground by an MOS polarization transistor M6 of the enrichment type.
  • the output stage, or level shift stage, of the comparator comprises MOS enhancement transistors M7 and M8 connected in series, the gate of transistor M7 connected to the gate of transistor M5 and the gate of transistor M8 being connected to the gates M2 and M6 transistors.
  • the bias voltage set by the transistors M1 and M2 is used to establish the level of the current in the transistors M6 and M8.
  • V x the voltage at the common sources of the transistors M3 and M4, and V y the voltage on the gate of the transistor M7
  • V y the voltage on the gate of the transistor M7
  • An object of the present invention is to provide a circuit making it possible to obtain a voltage always corresponding to the threshold voltage of a MOS transistor even when the operating parameters, temperature or manufacturing conditions vary.
  • the present invention proposes to play on the bias voltage of the comparator.
  • the present invention provides a stabilized generator included in an MOS integrated circuit for supplying a bias voltage to a first comparator connected to a first inverter intended to supply a voltage equal to a threshold voltage of MOS transistor when these two inputs are at same potential.
  • This generator comprises a second comparator and a second inverter identical to the first, and a third inverter receiving the output of the second and whose output is connected to the polarization inputs of the comparators, this third inverter being dimensioned so that its threshold voltage is slightly higher to that of a MOS transistor.
  • the second comparator comprises two comparison MOS transistors whose gates are interconnected and receive the reference voltage V REF and whose sources are connected to ground via a transistor polarization which receives on its grid the output of the third inverter.
  • the third inverter comprises a transistor with depletion in series with an enrichment transistor, the enrichment transistor being identical to the transistor to which a threshold bias voltage is to be supplied, the depletion transistor having a high resistance in the on state compared to that of the enrichment transistor near its threshold conduction.
  • a circuit according to the present invention is used to bias the comparator 1 of the conventional circuit illustrated in FIG. 1.
  • the bias circuit comprises a comparator 11 and an inverter 12 connected in the same way as the comparator 1 and the inverter 2 of FIG. 1 except that the two inputs of the comparator 11 are connected together at the reference voltage V REF .
  • the output of the inverter 12 is connected to the input of an inverter 13 whose output 14 provides the bias voltage of the comparators 11 and 1.
  • the circuit is dimensioned so that the inverter 12 normally provides a voltage almost equal to the threshold of the inverter 13 which is itself dimensioned so that its threshold voltage is practically equal to the threshold of an MOS transistor. Since the input voltage of the inverter 13 is practically equal and slightly greater than the conduction threshold of this inverter, a small current flows in this inverter and establishes at output an equilibrium bias voltage for the comparator of voltage.
  • the operation of this circuit will be better understood in relation to the description of an exemplary implementation illustrated in FIG. 4 where there is the comparator 11, the inverter 12 and the inverter 13.
  • the comparator 11 is identical to the comparator 1 illustrated in detail in FIG. 2.
  • the MOS transistors constituting this comparator are designated in FIG. 4 by the same references as those in FIG. 2 assigned a premium.
  • the output inverter 13 comprises a MOS enhancement transistor M10, the gate of which receives the output of the inverter 12 and which is connected to the voltage V DD by means of a load made up of a depletion MOS transistor M11 .
  • transistor M11 is connected to connection 14 of transistors M11 and M10 which also serves as a terminal and output connected to the common connection of transistors M6 ′ and M8 ′ which corresponds to the polarization input of comparator 11. Similarly, terminal 14 is connected to the polarization terminal of comparator 1.
  • Transistor M10 is a transistor identical to transistor M which we want to polarize exactly at its threshold voltage. The circuits 11 and 12 are such that the voltage V p at the input of the transistor M10 is very slightly greater than its threshold voltage. Thus, the output of the inverter 2 to the transistor M will be at the same value and we will have reached the desired result.
  • V T the gate threshold voltage of transistor M10 or of transistor M
  • g m the transconductance of transistor M10
  • I ds the current in transistor M10.
  • the threshold voltage V T of the transistor M10 increases momentarily with respect to an equilibrium value as a result of variations in parameters such as the temperature, this will result in a decrease in the current in the transistor M10.
  • This will cause the bias voltage on terminal 14 to increase, that is to say that the voltage V x at the connection point of the transistors M3 ′ and M4 ′ drops.
  • This will cause a decrease in the output voltage of the comparator Il and therefore an increase in V p .
  • An increase in V p will tend to decrease the bias voltage on terminal 14.
  • This action of the bias voltage is in the opposite direction from the influence of a growth of V T. The same reasoning applies in the opposite case where V T would tend to decrease.
  • the bias voltage is maintained at equilibrium so that the output of the inverter 13 is always immediately above the threshold voltage of an MOS transistor.
  • the resistance of transistor M11 is high compared to the resistance of transistor M10 in the vicinity of the conduction threshold.
  • This resistance in the vicinity of the conduction threshold being of the order of a hundred ohms, the resistance M11 will be chosen of the order of a hundred kilhons.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Automation & Control Theory (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Control Of Electrical Variables (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
EP89420084A 1988-03-09 1989-03-08 Stabilisierter Generator für die Lieferung einer Schwellenspannung für einen MOS-Transistor Expired - Lifetime EP0332548B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8803751A FR2628547B1 (fr) 1988-03-09 1988-03-09 Generateur stabilise de fourniture de tension de seuil de transistor mos
FR8803751 1988-03-09

Publications (2)

Publication Number Publication Date
EP0332548A1 true EP0332548A1 (de) 1989-09-13
EP0332548B1 EP0332548B1 (de) 1993-07-14

Family

ID=9364534

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89420084A Expired - Lifetime EP0332548B1 (de) 1988-03-09 1989-03-08 Stabilisierter Generator für die Lieferung einer Schwellenspannung für einen MOS-Transistor

Country Status (6)

Country Link
US (1) US4954728A (de)
EP (1) EP0332548B1 (de)
JP (1) JPH0210917A (de)
KR (1) KR890015102A (de)
DE (1) DE68907504T2 (de)
FR (1) FR2628547B1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110364992A (zh) * 2018-04-10 2019-10-22 杰力科技股份有限公司 电压转换电路及其控制电路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2656174B1 (fr) * 1989-12-15 1995-03-17 Bull Sa Procede et dispositif de compensation de la derive en courant dans un circuit integre mos, et circuit integre en resultant.
JPH05315852A (ja) * 1992-05-12 1993-11-26 Fuji Electric Co Ltd 電流制限回路および電流制限回路用定電圧源

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2016801A (en) * 1978-03-08 1979-09-26 Hitachi Ltd Reference voltage generating device
EP0019279A1 (de) * 1979-05-15 1980-11-26 Kabushiki Kaisha Toshiba Spannungsvergleichsschaltung
EP0045841A1 (de) * 1980-06-24 1982-02-17 Nec Corporation Spannung-Strom-Umsetzer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3546481A (en) * 1967-10-18 1970-12-08 Texas Instruments Inc Threshold circuit for comparing variable amplitude voltages
US4553098A (en) * 1978-04-05 1985-11-12 Hitachi, Ltd. Battery checker
JPS58221521A (ja) * 1982-06-18 1983-12-23 Toshiba Corp 基準電位発生回路およびこれを用いた入力回路
US4563595A (en) * 1983-10-27 1986-01-07 National Semiconductor Corporation CMOS Schmitt trigger circuit for TTL logic levels
US4584492A (en) * 1984-08-06 1986-04-22 Intel Corporation Temperature and process stable MOS input buffer
JPS61224192A (ja) * 1985-03-29 1986-10-04 Sony Corp 読出し増幅器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2016801A (en) * 1978-03-08 1979-09-26 Hitachi Ltd Reference voltage generating device
EP0019279A1 (de) * 1979-05-15 1980-11-26 Kabushiki Kaisha Toshiba Spannungsvergleichsschaltung
EP0045841A1 (de) * 1980-06-24 1982-02-17 Nec Corporation Spannung-Strom-Umsetzer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 8, no. 74 (E-236) 1511 06 avril 1984, & JP-A-58 221521 (TOKYO SHIBAURA DENKI) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110364992A (zh) * 2018-04-10 2019-10-22 杰力科技股份有限公司 电压转换电路及其控制电路
CN110364992B (zh) * 2018-04-10 2021-07-06 杰力科技股份有限公司 电压转换电路及其控制电路

Also Published As

Publication number Publication date
KR890015102A (ko) 1989-10-28
JPH0210917A (ja) 1990-01-16
EP0332548B1 (de) 1993-07-14
US4954728A (en) 1990-09-04
DE68907504T2 (de) 1994-01-05
FR2628547A1 (fr) 1989-09-15
FR2628547B1 (fr) 1990-12-28
DE68907504D1 (de) 1993-08-19

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