EP0332548A1 - Stabilized generator for the delivery of a threshold voltage for a MOS transistor - Google Patents

Stabilized generator for the delivery of a threshold voltage for a MOS transistor Download PDF

Info

Publication number
EP0332548A1
EP0332548A1 EP89420084A EP89420084A EP0332548A1 EP 0332548 A1 EP0332548 A1 EP 0332548A1 EP 89420084 A EP89420084 A EP 89420084A EP 89420084 A EP89420084 A EP 89420084A EP 0332548 A1 EP0332548 A1 EP 0332548A1
Authority
EP
European Patent Office
Prior art keywords
transistor
inverter
voltage
comparator
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89420084A
Other languages
German (de)
French (fr)
Other versions
EP0332548B1 (en
Inventor
Antoine Pavlin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of EP0332548A1 publication Critical patent/EP0332548A1/en
Application granted granted Critical
Publication of EP0332548B1 publication Critical patent/EP0332548B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature

Definitions

  • the present invention relates to the field of integrated circuits of the MOS (metal-oxide-semiconductor) type.
  • FIG. 1 schematically shows such a comparator used in the prior art.
  • This comparator receives on its inputs the two voltages to be compared, the output stage consisting of an inverter 2.
  • a conventional bias voltage supply circuit for comparator 1 comprises two MOS transistors M1 and M2 in series between a power source V DD and ground.
  • the transistor M1 is a depletion MOS transistor and the transistor M2 is an enrichment MOS transistor.
  • the transistor M1 serves as a load and its gate and its source are interconnected while the drain and the gate of the MOS transistor M2 are also interconnected.
  • the bias voltage of comparator 1 is taken from the interconnection point of the transistors M1 and M2.
  • inverter a circuit providing a high output voltage when its input is at low level and vice versa and not a circuit reversing the polarity of the voltages d 'Entrance.
  • FIG. 2 represents in more detail an embodiment of the circuit of FIG. 1 and more particularly of the comparator 1.
  • This comparator comprises two MOS transistors with enhancement M3 and M4 whose gates are connected respectively to V in and to a reference voltage V REF .
  • the drain of transistor M3 is connected to the supply voltage V DD
  • the drain of transistor M4 is connected to this same voltage by means of a depletion MOS transistor serving as load M5, the gate of which is connected to the source .
  • the sources of the transistors M3 and M4 are interconnected and are connected to ground by an MOS polarization transistor M6 of the enrichment type.
  • the output stage, or level shift stage, of the comparator comprises MOS enhancement transistors M7 and M8 connected in series, the gate of transistor M7 connected to the gate of transistor M5 and the gate of transistor M8 being connected to the gates M2 and M6 transistors.
  • the bias voltage set by the transistors M1 and M2 is used to establish the level of the current in the transistors M6 and M8.
  • V x the voltage at the common sources of the transistors M3 and M4, and V y the voltage on the gate of the transistor M7
  • V y the voltage on the gate of the transistor M7
  • An object of the present invention is to provide a circuit making it possible to obtain a voltage always corresponding to the threshold voltage of a MOS transistor even when the operating parameters, temperature or manufacturing conditions vary.
  • the present invention proposes to play on the bias voltage of the comparator.
  • the present invention provides a stabilized generator included in an MOS integrated circuit for supplying a bias voltage to a first comparator connected to a first inverter intended to supply a voltage equal to a threshold voltage of MOS transistor when these two inputs are at same potential.
  • This generator comprises a second comparator and a second inverter identical to the first, and a third inverter receiving the output of the second and whose output is connected to the polarization inputs of the comparators, this third inverter being dimensioned so that its threshold voltage is slightly higher to that of a MOS transistor.
  • the second comparator comprises two comparison MOS transistors whose gates are interconnected and receive the reference voltage V REF and whose sources are connected to ground via a transistor polarization which receives on its grid the output of the third inverter.
  • the third inverter comprises a transistor with depletion in series with an enrichment transistor, the enrichment transistor being identical to the transistor to which a threshold bias voltage is to be supplied, the depletion transistor having a high resistance in the on state compared to that of the enrichment transistor near its threshold conduction.
  • a circuit according to the present invention is used to bias the comparator 1 of the conventional circuit illustrated in FIG. 1.
  • the bias circuit comprises a comparator 11 and an inverter 12 connected in the same way as the comparator 1 and the inverter 2 of FIG. 1 except that the two inputs of the comparator 11 are connected together at the reference voltage V REF .
  • the output of the inverter 12 is connected to the input of an inverter 13 whose output 14 provides the bias voltage of the comparators 11 and 1.
  • the circuit is dimensioned so that the inverter 12 normally provides a voltage almost equal to the threshold of the inverter 13 which is itself dimensioned so that its threshold voltage is practically equal to the threshold of an MOS transistor. Since the input voltage of the inverter 13 is practically equal and slightly greater than the conduction threshold of this inverter, a small current flows in this inverter and establishes at output an equilibrium bias voltage for the comparator of voltage.
  • the operation of this circuit will be better understood in relation to the description of an exemplary implementation illustrated in FIG. 4 where there is the comparator 11, the inverter 12 and the inverter 13.
  • the comparator 11 is identical to the comparator 1 illustrated in detail in FIG. 2.
  • the MOS transistors constituting this comparator are designated in FIG. 4 by the same references as those in FIG. 2 assigned a premium.
  • the output inverter 13 comprises a MOS enhancement transistor M10, the gate of which receives the output of the inverter 12 and which is connected to the voltage V DD by means of a load made up of a depletion MOS transistor M11 .
  • transistor M11 is connected to connection 14 of transistors M11 and M10 which also serves as a terminal and output connected to the common connection of transistors M6 ′ and M8 ′ which corresponds to the polarization input of comparator 11. Similarly, terminal 14 is connected to the polarization terminal of comparator 1.
  • Transistor M10 is a transistor identical to transistor M which we want to polarize exactly at its threshold voltage. The circuits 11 and 12 are such that the voltage V p at the input of the transistor M10 is very slightly greater than its threshold voltage. Thus, the output of the inverter 2 to the transistor M will be at the same value and we will have reached the desired result.
  • V T the gate threshold voltage of transistor M10 or of transistor M
  • g m the transconductance of transistor M10
  • I ds the current in transistor M10.
  • the threshold voltage V T of the transistor M10 increases momentarily with respect to an equilibrium value as a result of variations in parameters such as the temperature, this will result in a decrease in the current in the transistor M10.
  • This will cause the bias voltage on terminal 14 to increase, that is to say that the voltage V x at the connection point of the transistors M3 ′ and M4 ′ drops.
  • This will cause a decrease in the output voltage of the comparator Il and therefore an increase in V p .
  • An increase in V p will tend to decrease the bias voltage on terminal 14.
  • This action of the bias voltage is in the opposite direction from the influence of a growth of V T. The same reasoning applies in the opposite case where V T would tend to decrease.
  • the bias voltage is maintained at equilibrium so that the output of the inverter 13 is always immediately above the threshold voltage of an MOS transistor.
  • the resistance of transistor M11 is high compared to the resistance of transistor M10 in the vicinity of the conduction threshold.
  • This resistance in the vicinity of the conduction threshold being of the order of a hundred ohms, the resistance M11 will be chosen of the order of a hundred kilhons.

Abstract

Stabilised generator included within a MOS integrated circuit in order to deliver a bias voltage to a first comparator (1) connected to a first inverter (2) intended to deliver a voltage equal to a MOS transistor (M) threshold voltage when the input voltages thereof are identical, including a second comparator (11) whose inputs are together connected to a reference voltage and a second inverter (12), which are identical to the first ones, and a third inverter (13) receiving the output from the second one and whose output (14) is connected to the bias inputs of the comparators (1, 11), this third inverter being rated so that its threshold voltage is identical with that of an MOS transistor. <IMAGE>

Description

La présente invention concerne le domaine des circuits intégrés de type MOS (métal-oxyde-semiconducteur).The present invention relates to the field of integrated circuits of the MOS (metal-oxide-semiconductor) type.

Dans de tels circuits, on a souvent besoin de comparer un signal de tension variable Vin à une tension de référence VREF.In such circuits, it is often necessary to compare a variable voltage signal V in with a reference voltage V REF .

La figure 1, représente schématiquement un tel compara­teur utilisé dans l'art antérieur. Ce comparateur reçoit sur ses entrées les deux tensions à comparer, l'étage de sortie étant constitué d'un inverseur 2. Cet inverseur fournit à un transistor MOS M, quand la tension de référence et la tension de polarisation du comparateur 1 sont convenablement choisies, une tension égale à sa tension de seuil au moment où Vin = VREF.Figure 1 schematically shows such a comparator used in the prior art. This comparator receives on its inputs the two voltages to be compared, the output stage consisting of an inverter 2. This inverter supplies to a MOS transistor M, when the reference voltage and the bias voltage of comparator 1 are suitably chosen , a voltage equal to its threshold voltage at the time when V in = V REF .

Un circuit classique de fourniture de tension de polari­sation pour le comparateur 1 comprend deux transistors MOS M1 et M2 en série entre une source d'alimentation VDD et la masse. Le transistor M1 est un transistor MOS à appauvrissement et le tran­sistor M2 est un transistor MOS à enrichissement. Le transistor M1 sert de charge et sa grille et sa source sont interconnectées tan­dis que le drain et la grille du transistor MOS M2 sont également interconnectés. La tension de polarisation du comparateur 1 est prélevée sur le point d'interconnexion des transistors M1 et M2.A conventional bias voltage supply circuit for comparator 1 comprises two MOS transistors M1 and M2 in series between a power source V DD and ground. The transistor M1 is a depletion MOS transistor and the transistor M2 is an enrichment MOS transistor. The transistor M1 serves as a load and its gate and its source are interconnected while the drain and the gate of the MOS transistor M2 are also interconnected. The bias voltage of comparator 1 is taken from the interconnection point of the transistors M1 and M2.

On notera dans ce qui précède et dans la suite de la présente description que l'on désigne ici par inverseur un circuit fournissant une tension de sortie haute quand son entrée est à bas niveau et inversement et non pas un circuit inversant la polarité des tensions d'entrée.It will be noted in the foregoing and in the remainder of this description that here is designated by inverter a circuit providing a high output voltage when its input is at low level and vice versa and not a circuit reversing the polarity of the voltages d 'Entrance.

La figure 2 représente plus en détail un mode de réali­sation du circuit de la figure 1 et plus particulièrement du com­parateur 1. Ce comparateur comprend deux transistors MOS à enrichissement M3 et M4 dont les grilles sont connectées respecti­vement à Vin et à une tension de référence VREF. Le drain du tran­sistor M3 est relié à la tension d'alimentation VDD, le drain du transistor M4 est relié à cette même tension par l'intermédiaire d'un transistor MOS à déplétion servant de charge M5 dont la gril­le est reliée à la source. Les sources des transistors M3 et M4 sont interconnectées et sont reliés à la masse par un transistor MOS de polarisation M6 de type à enrichissement. L'étage de sor­tie, ou étage de décalage de niveau, du comparateur comprend des transistors MOS à enrichissement M7 et M8 reliés en série, la grille du transistor M7 reliée à la grille du transistor M5 et la grille du transistor M8 étant reliée aux grilles des tran­sistors M2 et M6.FIG. 2 represents in more detail an embodiment of the circuit of FIG. 1 and more particularly of the comparator 1. This comparator comprises two MOS transistors with enhancement M3 and M4 whose gates are connected respectively to V in and to a reference voltage V REF . The drain of transistor M3 is connected to the supply voltage V DD , the drain of transistor M4 is connected to this same voltage by means of a depletion MOS transistor serving as load M5, the gate of which is connected to the source . The sources of the transistors M3 and M4 are interconnected and are connected to ground by an MOS polarization transistor M6 of the enrichment type. The output stage, or level shift stage, of the comparator comprises MOS enhancement transistors M7 and M8 connected in series, the gate of transistor M7 connected to the gate of transistor M5 and the gate of transistor M8 being connected to the gates M2 and M6 transistors.

La tension de polarisation réglée par les transistors M1 et M2 sert à établir le niveau du courant dans les transistors M6 et M8. Les dimensions de ces transistors par rapport aux autres transistors du comparateur et du circuit de décalage de niveau sont choisies pour établir à la sortie de l'inverseur 2 une ten­sion égale à la tension de seuil d'un transistor à enrichissement à canal N pour un ensemble donné de température de fonctionnement et de paramètres de fabrication lorsque Vin = VREF. Mais, si l'une de ces conditions change, la tension de sortie de l'inverseur ne sera plus égale à la tension de seuil du transistor MOS. Ainsi, si l'on appelle Vx la tension au niveau des sources communes des transistors M3 et M4, et Vy la tension sur la grille du transistor M7, si la tension de polarisation augmente, les transistors M6 et M8 deviendront plus passants et la tension aux noeuds Vx et Vy diminuera. Il en résultera une diminution de la tension à l'entrée de l'inverseur et une augmentation de la tension à sa sortie. Cette tension ne sera alors plus égale à la tension de seuil d'un transistor MOS à canal N au moment où Vin = VREF. Inversement, si la tension de polarisation sur la grille des transistors M6 et M8 diminue, la tension de sortie de l'inverseur 2 diminuera.The bias voltage set by the transistors M1 and M2 is used to establish the level of the current in the transistors M6 and M8. The dimensions of these transistors relative to the other transistors of the comparator and of the level shift circuit are chosen to establish at the output of the inverter 2 a voltage equal to the threshold voltage of an N-channel enhancement transistor for a given set of operating temperature and manufacturing parameters when V in = V REF . However, if one of these conditions changes, the output voltage of the inverter will no longer be equal to the threshold voltage of the MOS transistor. Thus, if we call V x the voltage at the common sources of the transistors M3 and M4, and V y the voltage on the gate of the transistor M7, if the bias voltage increases, the transistors M6 and M8 will become more conducting and the voltage at the nodes V x and V y will decrease. This will result in a decrease in voltage at the input of the inverter and an increase in voltage at its output. This voltage will then no longer be equal to the threshold voltage of an N-channel MOS transistor at the time when V in = V REF . Conversely, if the bias voltage on the gate of the transistors M6 and M8 decreases, the output voltage of the inverter 2 will decrease.

Un objet de la présente invention est de prévoir un cir­cuit permettant d'obtenir une tension correspondant toujours à la tension de seuil d'un transistor MOS même quand les paramètres de fonctionnement, température ou conditions de fabrication, varient.An object of the present invention is to provide a circuit making it possible to obtain a voltage always corresponding to the threshold voltage of a MOS transistor even when the operating parameters, temperature or manufacturing conditions vary.

Pour atteindre cet objet, la présente invention propose de jouer sur la tension de polarisation du comparateur.To achieve this object, the present invention proposes to play on the bias voltage of the comparator.

Ainsi, la présente invention prévoit un générateur stabilisé compris dans une circuit intégré MOS pour fournir une tension de polarisation à un premier comparateur relié à un pre­mier inverseur destiné à fournir une tension égale à une tension de seuil de transistor MOS lorsque ces deux entrées sont au même potentiel. Ce générateur comprend un deuxième comparateur et un deuxième inverseur identiques aux premiers, et un troisième inver­seur recevant la sortie du deuxième et dont la sortie est reliée aux entrées de polarisation des comparateurs, ce troisième inver­seur étant dimensionné pour que sa tension de seuil soit légère­ment supérieure à celle d'un transistor MOS.Thus, the present invention provides a stabilized generator included in an MOS integrated circuit for supplying a bias voltage to a first comparator connected to a first inverter intended to supply a voltage equal to a threshold voltage of MOS transistor when these two inputs are at same potential. This generator comprises a second comparator and a second inverter identical to the first, and a third inverter receiving the output of the second and whose output is connected to the polarization inputs of the comparators, this third inverter being dimensioned so that its threshold voltage is slightly higher to that of a MOS transistor.

Selon un mode de réalisation de la présente invention, le deuxième comparateur comprend deux transistors MOS de com­paraison dont les grilles sont interconnectées et reçoivent la tension de référence VREF et dont les sources sont connectées à la masse par l'intermédiaire d'un transistor de polarisation qui reçoit sur sa grille la sortie du troisième inverseur.According to an embodiment of the present invention, the second comparator comprises two comparison MOS transistors whose gates are interconnected and receive the reference voltage V REF and whose sources are connected to ground via a transistor polarization which receives on its grid the output of the third inverter.

Selon un mode de réalisation de la présente invention, le troisième inverseur comprend un transistor à appauvrissement en série avec un transistor à enrichissement, le transistor à enri­chissement étant identique au transistor auquel on veut fournir une tension de polarisation de seuil, le transistor à appauvrisse­ment ayant une résistance à l'état passant élévée devant celle du transistor à enrichissement au voisinage de son seuil de conduc­tion.According to an embodiment of the present invention, the third inverter comprises a transistor with depletion in series with an enrichment transistor, the enrichment transistor being identical to the transistor to which a threshold bias voltage is to be supplied, the depletion transistor having a high resistance in the on state compared to that of the enrichment transistor near its threshold conduction.

Ces objets, caractéristiques et avantages ainsi que d'autres de la présente invention seront exposés plus en détail dans la description suivante de modes de réalisation particuliers faite en relation avec les figures joints parmi lesquelles :

  • la figure 1 représente sous forme de blocs un comparateur selon l'art antérieur ;
  • la figure 2 représente de façon plus détaillée le cir­cuit selon l'art antérieur ;
  • la figure 3 représente sous forme de blocs un circuit de polarisation selon présente invention ;
  • la figure 4 représente de façon plus détaillée un cir­cuit selon la présente invention.
These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of particular embodiments made in relation to the attached figures, among which:
  • FIG. 1 represents in the form of blocks a comparator according to the prior art;
  • Figure 2 shows in more detail the circuit according to the prior art;
  • FIG. 3 represents in the form of blocks a polarization circuit according to the present invention;
  • Figure 4 shows in more detail a circuit according to the present invention.

Dans ces diverses figures, des éléments identiques ou analogues sont désignés par les mêmes références numériques. D'autre part, on notera que les transistors MOS à enrichissement (normalement bloqués) sont représentés avec un trait de grille séparé par un blanc d'un trait symbolisant le substrat alors que les transistors MOS du type à appauvrissement (normalement passants) sont désignés avec un trait de grille séparé par une zone hachurées d'un trait symbolisant le substrat.In these various figures, identical or analogous elements are designated by the same reference numerals. On the other hand, it will be noted that the enriched MOS transistors (normally blocked) are represented with a grid line separated by a white line of a line symbolizing the substrate while the MOS transistors of the depletion type (normally on) with a grid line separated by a hatched area with a line symbolizing the substrate.

Comme le représente la figure 3, un circuit selon la présente invention, est utilisé pour polariser le comparateur 1 du circuit classique illustré en figure 1. Le circuit de polarisation comprend un comparateur 11 et un inverseur 12 connectés de la même façon qui le comparateur 1 et l'inverseur 2 de la figure 1 si ce n'est que les deux entrées du comparateur 11 sont reliées ensemble à la tension de référence VREF. La sortie de l'inverseur 12 est reliée à l'entrée d'un inverseur 13 dont la sortie 14 fournit la tension de polarisation des comparateurs 11 et 1. Les circuit est dimensionné pour que l'inverseur 12 fournisse normalement une ten­sion presque égale au seuil de l'inverseur 13 qui est lui-même di­mensionné pour que sa tension de seuil soit pratiquement égale au seuil d'un transistor MOS. Etant donné que la tension d'entrée de l'inverseur 13 est pratiquement égale et légèrement supérieure au seuil de conduction de cet inverseur, un petit courant circule dans cet inverseur et établit en sortie une tension de polarisa­tion à l'équilibre pour le comparateur de tension.As shown in FIG. 3, a circuit according to the present invention is used to bias the comparator 1 of the conventional circuit illustrated in FIG. 1. The bias circuit comprises a comparator 11 and an inverter 12 connected in the same way as the comparator 1 and the inverter 2 of FIG. 1 except that the two inputs of the comparator 11 are connected together at the reference voltage V REF . The output of the inverter 12 is connected to the input of an inverter 13 whose output 14 provides the bias voltage of the comparators 11 and 1. The circuit is dimensioned so that the inverter 12 normally provides a voltage almost equal to the threshold of the inverter 13 which is itself dimensioned so that its threshold voltage is practically equal to the threshold of an MOS transistor. Since the input voltage of the inverter 13 is practically equal and slightly greater than the conduction threshold of this inverter, a small current flows in this inverter and establishes at output an equilibrium bias voltage for the comparator of voltage.

Le fonctionnement de ce circuit sera mieux compris en relation avec la description d'un exemple de mise en oeuvre illustré en figure 4 où l'on retrouve le comparateur 11, l'inver­seur 12 et l'inverseur 13. Le comparateur 11 est identique au com­parateur 1 illustré en détail en figure 2. Les transistors MOS constituant ce comparateur sont désignés à la figure 4 par les mêmes références que celles de la figure 2 affectées d'un prime. L'inverseur de sortie 13 comprend un transistor MOS à enrichisse­ment M10 dont la grille reçoit la sortie de l'inverseur 12 et qui est relié à la tension VDD par l'intermédiaire d'une charge cons­tituée d'un transistor MOS è appauvrissement M11. La grille du transistor M11 est reliée à la connexion 14 des transistors M11 et M10 qui sert également de borne et sortie reliée à la connexion commune des transistors M6′ et M8′ qui correspond à l'entrée de polarisation du comparateur 11. De même, la borne 14 est reliée à la borne de polarisation du comparateur 1. Le transistor M10 est un transistor identique au transistor M que l'on veut polariser exactement à sa tension de seuil. Les circuits 11 et 12 sont tels que la tension Vp à l'entrée du transistor M10 est très légèrement supérieure à sa tension de seuil. Ainsi, la sortie de l'inverseur 2 vers le transistor M sera à une même valeur et on aura atteint le résultat souhaité. A l'équilibre :
Vp = VT + Ids * gm
où VT est la tension de seuil de grille du transistor M10 ou du transistor M, gm est la transconductance du transistor M10 et Ids est le courant dans le transistor M10.The operation of this circuit will be better understood in relation to the description of an exemplary implementation illustrated in FIG. 4 where there is the comparator 11, the inverter 12 and the inverter 13. The comparator 11 is identical to the comparator 1 illustrated in detail in FIG. 2. The MOS transistors constituting this comparator are designated in FIG. 4 by the same references as those in FIG. 2 assigned a premium. The output inverter 13 comprises a MOS enhancement transistor M10, the gate of which receives the output of the inverter 12 and which is connected to the voltage V DD by means of a load made up of a depletion MOS transistor M11 . The gate of transistor M11 is connected to connection 14 of transistors M11 and M10 which also serves as a terminal and output connected to the common connection of transistors M6 ′ and M8 ′ which corresponds to the polarization input of comparator 11. Similarly, terminal 14 is connected to the polarization terminal of comparator 1. Transistor M10 is a transistor identical to transistor M which we want to polarize exactly at its threshold voltage. The circuits 11 and 12 are such that the voltage V p at the input of the transistor M10 is very slightly greater than its threshold voltage. Thus, the output of the inverter 2 to the transistor M will be at the same value and we will have reached the desired result. Equilibrium :
V p = V T + I ds * g m
where V T is the gate threshold voltage of transistor M10 or of transistor M, g m is the transconductance of transistor M10 and I ds is the current in transistor M10.

Si l'on suppose que la tension de seuil VT du transistor M10 (et donc simultanément du transistor M formé sur le même cir­cuit intégré) augmente momentanément par rapport à une valeur d'équilibre par suite de variations de paramètres tels que la tem­pérature, il en résultera une diminution du courant dans le tran­sistor M10. Ceci amènera la tension de polarisation sur la borne 14 à croître, c'est-à-dire que la tension Vx au point de raccorde­ment des transistors M3′ et M4′ chute. Ceci provoquera une diminu­tion de la tension de sortie du comparateur Il et donc une augmentation de Vp. Une augmentation de Vp tendra à faire décroî­tre la tension de polarisation sur la borne 14. Cette action de la tension de polarisation est en sens opposé de l'influence d'une croissance de VT. Le même raisonnement s'applique dans le cas in­verse où VT tendrait à décroître. Ainsi, la tension de polarisa­tion est maintenue à l'équilibre de sorte que la sortie de l'inverseur 13 se trouve toujours immédiatement au dessus de la tension de seuil d'un transistor MOS.If it is assumed that the threshold voltage V T of the transistor M10 (and therefore simultaneously of the transistor M formed on the same integrated circuit) increases momentarily with respect to an equilibrium value as a result of variations in parameters such as the temperature, this will result in a decrease in the current in the transistor M10. This will cause the bias voltage on terminal 14 to increase, that is to say that the voltage V x at the connection point of the transistors M3 ′ and M4 ′ drops. This will cause a decrease in the output voltage of the comparator Il and therefore an increase in V p . An increase in V p will tend to decrease the bias voltage on terminal 14. This action of the bias voltage is in the opposite direction from the influence of a growth of V T. The same reasoning applies in the opposite case where V T would tend to decrease. Thus, the bias voltage is maintained at equilibrium so that the output of the inverter 13 is always immediately above the threshold voltage of an MOS transistor.

Si l'on considère le circuit de la figure 4, il convient bien entendu pour qu'il fonctionne que la résistance du transistor M11 soit élevée devant la résistance du transistor M10 au voisi­nage du seuil de conduction. Cette résistance au voisinage du seuil de conduction étant de l'ordre de la centaine d'ohms, on choisira la résistance M11 de l'ordre de la centaine de kilhons.If we consider the circuit of Figure 4, it should of course for it to work that the resistance of transistor M11 is high compared to the resistance of transistor M10 in the vicinity of the conduction threshold. This resistance in the vicinity of the conduction threshold being of the order of a hundred ohms, the resistance M11 will be chosen of the order of a hundred kilhons.

Claims (3)

1. Générateur stabilisé compris dans un circuit intégré MOS pour fournir une tension de polarisation à un premier com­parateur (1) relié à un premier inverseur (2) destiné à fournir une tension égale à une tension de seuil de transistor MOS (M) lorsque ses tensions d'entrée sont identiques, caractérisé en ce qu'il comprend un deuxième comparateur (11) dont les entrées sont reliées ensemble à une tension de référence et un deuxième inver­seur (12) identiques aux premiers, et un troisième inverseur (13) recevant la sortie du deuxième et dont la sortie (14) est reliée aux entrées de polarisation des comparateurs (1, 11), ce troisième inverseur étant dimensionné pour que sa tension de seuil soit identique à celle d'un transistor MOS.1. Stabilized generator included in an MOS integrated circuit for supplying a bias voltage to a first comparator (1) connected to a first inverter (2) intended to supply a voltage equal to a threshold voltage of MOS transistor (M) when its input voltages are identical, characterized in that it comprises a second comparator (11) whose inputs are connected together to a reference voltage and a second inverter (12) identical to the first, and a third inverter (13) receiving the output of the second and whose output (14) is connected to the polarization inputs of the comparators (1, 11), this third inverter being dimensioned so that its threshold voltage is identical to that of a MOS transistor. 2. Générateur stabilisé selon la revendication 1, carac­térisé en ce que le deuxième comparateur (11) comprend deux tran­sistors MOS de comparaison (M3′, M4′) dont les grilles sont interconnectées et reçoivent la même tension de référence que l'une des entrées du premier comparateur (1) et donc les sources sont connectées à la masse par l'intermédiaire d'un transistor de polarisation (M6′) qui reçoit sur sa grille la sortie (14) du troisième inverseur (13).2. Stabilized generator according to claim 1, characterized in that the second comparator (11) comprises two MOS comparison transistors (M3 ′, M4 ′) whose gates are interconnected and receive the same reference voltage as one of the inputs of the first comparator (1) and therefore the sources are connected to ground via a bias transistor (M6 ′) which receives on its grid the output (14) of the third inverter (13). 3. Générateur stabilisé selon l'une des revendications 1 ou 2, caractérisé en ce que le troisième inverseur (13) comprend un transistor à appauvrissement (M11) en série avec un transistor à enrichissement (M10), le transistor à enrichissement étant iden­tique au transistor (M) auquel on veut fournir une tension de po­larisation de seuil, le transistor à appauvrissement ayant une résistance à l'état passant élevée devant celle du transistor à enrichissement au voisinage de son seuil de conduction.3. Stabilized generator according to one of claims 1 or 2, characterized in that the third inverter (13) comprises a depletion transistor (M11) in series with an enrichment transistor (M10), the enrichment transistor being identical to the transistor (M) to which a threshold bias voltage is to be supplied, the depletion transistor having a resistance in the on state which is high compared to that of the enrichment transistor in the vicinity of its conduction threshold.
EP89420084A 1988-03-09 1989-03-08 Stabilized generator for the delivery of a threshold voltage for a mos transistor Expired - Lifetime EP0332548B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8803751A FR2628547B1 (en) 1988-03-09 1988-03-09 STABILIZED GENERATOR FOR PROVIDING MOS TRANSISTOR THRESHOLD
FR8803751 1988-03-09

Publications (2)

Publication Number Publication Date
EP0332548A1 true EP0332548A1 (en) 1989-09-13
EP0332548B1 EP0332548B1 (en) 1993-07-14

Family

ID=9364534

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89420084A Expired - Lifetime EP0332548B1 (en) 1988-03-09 1989-03-08 Stabilized generator for the delivery of a threshold voltage for a mos transistor

Country Status (6)

Country Link
US (1) US4954728A (en)
EP (1) EP0332548B1 (en)
JP (1) JPH0210917A (en)
KR (1) KR890015102A (en)
DE (1) DE68907504T2 (en)
FR (1) FR2628547B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110364992A (en) * 2018-04-10 2019-10-22 杰力科技股份有限公司 Voltage conversion circuit and its control circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2656174B1 (en) * 1989-12-15 1995-03-17 Bull Sa METHOD AND DEVICE FOR COMPENSATING FOR CURRENT DRIFT IN A MOS INTEGRATED CIRCUIT, AND RESULTING INTEGRATED CIRCUIT.
JPH05315852A (en) * 1992-05-12 1993-11-26 Fuji Electric Co Ltd Current limit circuit and constant voltage source for the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2016801A (en) * 1978-03-08 1979-09-26 Hitachi Ltd Reference voltage generating device
EP0019279A1 (en) * 1979-05-15 1980-11-26 Kabushiki Kaisha Toshiba Voltage comparator circuit
EP0045841A1 (en) * 1980-06-24 1982-02-17 Nec Corporation Linear voltage-current converter

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3546481A (en) * 1967-10-18 1970-12-08 Texas Instruments Inc Threshold circuit for comparing variable amplitude voltages
US4553098A (en) * 1978-04-05 1985-11-12 Hitachi, Ltd. Battery checker
JPS58221521A (en) * 1982-06-18 1983-12-23 Toshiba Corp Reference potential generating circuit and input circuit using said generating circuit
US4563595A (en) * 1983-10-27 1986-01-07 National Semiconductor Corporation CMOS Schmitt trigger circuit for TTL logic levels
US4584492A (en) * 1984-08-06 1986-04-22 Intel Corporation Temperature and process stable MOS input buffer
JPS61224192A (en) * 1985-03-29 1986-10-04 Sony Corp Reading amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2016801A (en) * 1978-03-08 1979-09-26 Hitachi Ltd Reference voltage generating device
EP0019279A1 (en) * 1979-05-15 1980-11-26 Kabushiki Kaisha Toshiba Voltage comparator circuit
EP0045841A1 (en) * 1980-06-24 1982-02-17 Nec Corporation Linear voltage-current converter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 8, no. 74 (E-236) 1511 06 avril 1984, & JP-A-58 221521 (TOKYO SHIBAURA DENKI) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110364992A (en) * 2018-04-10 2019-10-22 杰力科技股份有限公司 Voltage conversion circuit and its control circuit
CN110364992B (en) * 2018-04-10 2021-07-06 杰力科技股份有限公司 Voltage conversion circuit and control circuit thereof

Also Published As

Publication number Publication date
DE68907504T2 (en) 1994-01-05
DE68907504D1 (en) 1993-08-19
JPH0210917A (en) 1990-01-16
US4954728A (en) 1990-09-04
KR890015102A (en) 1989-10-28
FR2628547B1 (en) 1990-12-28
FR2628547A1 (en) 1989-09-15
EP0332548B1 (en) 1993-07-14

Similar Documents

Publication Publication Date Title
US6333571B1 (en) MOS integrated circuit device operating with low power consumption
FR2731570A1 (en) DIFFERENTIAL STAGE LOGIC CIRCUIT
FR2779293A1 (en) Transistor output circuit for logic applications
EP0223627B1 (en) Conversion circuit of a differential input in cmos logic levels
FR2655196A1 (en) DYNAMIC ISOLATION CIRCUIT OF INTEGRATED CIRCUITS.
JPH06204820A (en) Comparator circuit and method for comparing a pair of signals with each other
EP1380913A1 (en) Linear voltage regulator
EP0332548B1 (en) Stabilized generator for the delivery of a threshold voltage for a mos transistor
US4999567A (en) Constant current circuit
EP0772297B1 (en) A circuit for generating an output signal having a 50% duty cycle
US6356121B1 (en) Very low-power comparison device
JP3208002B2 (en) Signal processing device and level conversion circuit
US5479114A (en) Three-value input buffer circuit
EP0571302A1 (en) Amplifier with limited output current
EP1505735A1 (en) Circuit for converting signals varying between two voltages
FR2805682A1 (en) COMPARISON DEVICE WITH VERY BASIC CONSUMPTION
EP0050583B1 (en) Alternating voltage to direct current converter and oscillator circuit comprising said converter
EP0722217B1 (en) Threshold adjusting circuit of the signal attenuation characteristic
EP0715240B1 (en) Voltage regulator for logical circuit in coupled mode
FR2542526A1 (en) QUARTZ OSCILLATOR
EP0332499B1 (en) Fast comparator with an output stage operating in two phases
EP0187572B1 (en) Logic voltage excursion limiter circuit, and circuit using such an excursion limiter
JP3397803B2 (en) Level shift circuit
FR2957732A1 (en) OUTPUT STAGE OF AN ELECTRONIC CIRCUIT
JP2001325033A (en) Constant-current circuit

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT NL

17P Request for examination filed

Effective date: 19900222

17Q First examination report despatched

Effective date: 19921005

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT NL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19930714

REF Corresponds to:

Ref document number: 68907504

Country of ref document: DE

Date of ref document: 19930819

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19930723

ITF It: translation for a ep patent filed

Owner name: ING. GIOVANNI ARENA

NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: FR

Ref legal event code: D6

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20010228

Year of fee payment: 13

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20020326

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20020327

Year of fee payment: 14

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021001

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030308

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20030308

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20031127

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050308