EP0294318A2 - Circuit pour la commande de l'accès parallèle de mémoires décentralisées (mémoire d'adresses fautives) - Google Patents
Circuit pour la commande de l'accès parallèle de mémoires décentralisées (mémoire d'adresses fautives) Download PDFInfo
- Publication number
- EP0294318A2 EP0294318A2 EP88730127A EP88730127A EP0294318A2 EP 0294318 A2 EP0294318 A2 EP 0294318A2 EP 88730127 A EP88730127 A EP 88730127A EP 88730127 A EP88730127 A EP 88730127A EP 0294318 A2 EP0294318 A2 EP 0294318A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- addresses
- central data
- data processor
- controlling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 24
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 238000004891 communication Methods 0.000 claims abstract description 7
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000003936 working memory Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Definitions
- the invention relates to a circuit arrangement for controlling a digital communication system with a central data processor and with a plurality of peripheral devices controlling, decentralized input / output processors with memory devices, to which the central data processor and the respective decentralized input / output processor each act by means of multiple access control.
- Communication systems defined in this way represent modular private branch exchanges with a few standard interfaces, which are set up in a wide variety of system sizes in accordance with the tasks to be performed.
- the private branch exchanges can be connected to public networks and services - telephone network, teletex network etc. - as well as to private networks - sub-systems, cross-connection lines. Analog and digital terminals are provided as subscriber connections. In addition, there are additional connection options for external devices such as printers, operational terminals (PC), etc. via appropriate interfaces.
- the system architecture of the different communication systems is uniformly structured on three levels: periphery, decentralized input / output processors and central data processor.
- the periphery then includes modules as interfaces to the connected end devices and lines (subscriber circuits, line circuits) and modules for establishing a connection, such as signaling devices, transmitters and receivers.
- the time-critical processing of the periphery is carried out by the decentralized input-output processors, whereby the number the peripheral devices or that of the connection units for each input / output processor is limited depending on the maximum total amount of data to be processed.
- the input / output processors are therefore intended for the control of standard interfaces and local buses, the evaluation of digits, the connection of sound and call clocks and the safety-related displays.
- the central data processor coordinates the control of all devices in the communication system via corresponding bus connections.
- the reset logic and safety-related processes are controlled centrally by the central data processor.
- the interface between the periphery and the respective decentralized input / output processor is formed by an HDLC standard interface, which is contained in the peripheral device.
- the interface between the decentralized input / output processor and the central data processor is formed by a multiple access memory which can be written and read by both processors. This multiple access memory is usually controlled by the operating system used.
- the link between the central data processor and the periphery is the input / output processor with two peripheral devices.
- the peripheral devices are each equipped with an HDLC standard interface, via which the data exchange between the input-output processor and the connected peripheral devices takes place.
- these two HDLC standard interfaces are interleaved and operated in the so-called DMA mode, in the direct access method.
- the data processor accesses the multiple access memory, the corresponding input / output processor is put into the so-called hold state in order to avoid faulty data exchange via the HDLC standard interfaces.
- the input / output processor is blocked and data traffic via the HDLC standard interfaces is also prevented.
- the object on which the invention is based is to avoid this blocking state, but without having to change the operation of the HDLC standard interfaces, which is advantageous for dynamic reasons. According to the invention, this is achieved by combining the features of claim 1.
- the addresses of the multiple access memory can first be processed in a conventional manner in a nested manner, and then the addresses of the error address memory can be subsequently processed to be processed sequentially by the microprocessor of the input / output processor.
- simultaneous data traffic is imposed on both HDLC standard interfaces.
- the microprocessor of the input / output processor cannot be switched to the holding state either.
- the input / output processor IOP contains the microprocessor MC with the control of the direct access method DMA. Furthermore, it is indicated that the central data processor DP, like the microprocessor MC, has access to the memory device SP, which is formed from the multiple access memory DPR, the working memory MEM and the error address memory FSA. Furthermore, the peripheral devices PBC are shown with their HDLC standard interfaces, which are controlled by the microprocessor MC of the input / output processor IOP and by the memory device SP. The data exchange between the input / output processor IOP and the connected subscribers, not shown, takes place via the two HDLC standard interfaces shown in the exemplary embodiment.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Exchange Systems With Centralized Control (AREA)
- Communication Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT88730127T ATE85487T1 (de) | 1987-06-04 | 1988-05-27 | Schaltungsanordnung zur steuerung von parallelzugriffen zu dezentralen speichereinrichtungen (fehleradressenspeicher). |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19873718985 DE3718985A1 (de) | 1987-06-04 | 1987-06-04 | Schaltungsanordnung zur steuerung von parallelzugriffen zu dezentralen speichereinrichtungen (fehleradressenspeicher) |
DE3718985 | 1987-06-04 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0294318A2 true EP0294318A2 (fr) | 1988-12-07 |
EP0294318A3 EP0294318A3 (en) | 1990-05-09 |
EP0294318B1 EP0294318B1 (fr) | 1993-02-03 |
Family
ID=6329192
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP88730127A Expired - Lifetime EP0294318B1 (fr) | 1987-06-04 | 1988-05-27 | Circuit pour la commande de l'accès parallèle de mémoires décentralisées (mémoire d'adresses fautives) |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0294318B1 (fr) |
AT (1) | ATE85487T1 (fr) |
DE (2) | DE3718985A1 (fr) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0021254A1 (fr) * | 1979-06-20 | 1981-01-07 | Siemens Aktiengesellschaft | Procédé et appareil pour la connexion de plusieurs unités centrales de traitement de données à des appareils d'emmagasimage de données via l'une ou l'autre d'au moins deux unités périphériques de traitement de données |
-
1987
- 1987-06-04 DE DE19873718985 patent/DE3718985A1/de not_active Withdrawn
-
1988
- 1988-05-27 EP EP88730127A patent/EP0294318B1/fr not_active Expired - Lifetime
- 1988-05-27 AT AT88730127T patent/ATE85487T1/de not_active IP Right Cessation
- 1988-05-27 DE DE8888730127T patent/DE3878044D1/de not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0021254A1 (fr) * | 1979-06-20 | 1981-01-07 | Siemens Aktiengesellschaft | Procédé et appareil pour la connexion de plusieurs unités centrales de traitement de données à des appareils d'emmagasimage de données via l'une ou l'autre d'au moins deux unités périphériques de traitement de données |
Non-Patent Citations (3)
Title |
---|
ISS 1987, Phoenix, US, 15.-20. M{rz 1987, Seiten B2.5.1-B2.5.7; J. LAMY et al.: "CCS No. 7 Transfer Point" * |
ISS'81, Montréal, CA, 21.-25. September 1981, Seiten 23B.2.1-23B.2.6; F. BEHAGUE et al.: "CCITT No. 7 Commom Channel Signaling and the E10 and E12 Digital Switching Systems" * |
TELCOM REPORT (SIEMENS), Band 9, Heft 4, Juli/August 1986, Seiten 257-263; H. FELLINGER et al.: "Höhere Steuerleistung im EWSD durch den Koordinationsprozessor CP 113" * |
Also Published As
Publication number | Publication date |
---|---|
DE3878044D1 (de) | 1993-03-18 |
EP0294318A3 (en) | 1990-05-09 |
ATE85487T1 (de) | 1993-02-15 |
EP0294318B1 (fr) | 1993-02-03 |
DE3718985A1 (de) | 1988-12-22 |
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