EP0278194B1 - Elektrolumineszenzanzeige mit Speichereffekt, gesteuert durch mehrfache phasenverschobene Auffrischspannungen - Google Patents

Elektrolumineszenzanzeige mit Speichereffekt, gesteuert durch mehrfache phasenverschobene Auffrischspannungen Download PDF

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EP0278194B1
EP0278194B1 EP87402944A EP87402944A EP0278194B1 EP 0278194 B1 EP0278194 B1 EP 0278194B1 EP 87402944 A EP87402944 A EP 87402944A EP 87402944 A EP87402944 A EP 87402944A EP 0278194 B1 EP0278194 B1 EP 0278194B1
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Prior art keywords
electrodes
families
voltage
display
family
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French (fr)
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EP0278194A1 (de
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Pascal Thioulouse
Jean-Pierre Budin
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Etat Francais Represente Par Le Ministre Des Postes Et Telecommunications
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Etat Francais Represente Par Le Ministre Des Postes Et Telecommunications
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/088—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements using a non-linear two-terminal element
    • G09G2300/0885—Pixel comprising a non-linear two-terminal element alone in series with each display pixel element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G09G2360/147—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel
    • G09G2360/148—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel the light being detected by light detection means within each pixel

Definitions

  • the invention finds an application in opto-electronics in the production of electroluminescent displays with memory effect.
  • the invention is applicable to any type of electroluminescent display with memory effect.
  • An electroluminescent display is said to have a memory effect when the electro-optical property of the display has a hysteresis loop comprising two stable operating states.
  • Figure 1a there is shown schematically the hysteresis loop of the electro-optical property of an electroluminescent display with memory effect.
  • On the ordinate axis is represented the luminance L of the display and on the abscissa axis is represented the electric voltage V applied to the display.
  • the brightest state L a is said to be on, the other L e is said to be off.
  • the voltage applied to the display is temporarily increased to a value S a located beyond the hysteresis loop. Conversely, the display is turned off simply by temporarily decreasing the applied voltage.
  • a voltage V e is permanently applied to the entire display in order to keep all the pixels in their state.
  • electroluminescent displays with memory effect there are two types of electroluminescent displays with memory effect: the inherent memory effect display, obtained when the display comprises an electroluminescent layer based for example on zinc sulfide activated by manganese, sandwiched between two dielectric layers, and the extrinsic memory effect display, obtained when the display comprises an electroluminescent layer and a photoconductive layer superimposed.
  • FIG. 1b shows, by way of example, a photoconductive electroluminescent display.
  • the experimental data described below come from such a type of display. But the inherent memory effect display behaves similarly.
  • a photoconductive electroluminescent display comprises a transparent substrate 10, a first set of parallel transparent electrodes or line electrodes 12 (the perspective cut shown is assumed to be made along one of these lines), an electroluminescent layer 14, a photoconductive layer 16 and a second set of parallel transparent electrodes or column electrodes 18, perpendicular to the line electrodes 12.
  • the row and column electrodes are supplied from an alternating voltage generator 20. More specifically, the row electrodes 12 are connected to this generator 20 via a line addressing circuit 22 l and the column electrodes 18 by a column addressing circuit 22 c . The observation is preferably carried out through the substrate 10, at 23.
  • the display screen is made up of pixels, each of which is defined by the overlap area of a particular row electrode and a particular column electrode.
  • the actual display is, for example of the PC-EL type, that is to say made up of two layers 14 and 16, one light-emitting (EL) and the other photoconductive (PC).
  • EL light-emitting
  • PC photoconductive
  • the structure of the displayed image is defined and / or modified by the addressing function itself.
  • a conventional addressing method consists in sequentially scanning the line electrodes of the memory display. Instead of the potential U l , the selected line electrode is subjected to a potential U la , greater than U l .
  • the addressing circuit 22 c applies a potential U ca less than U c than those of the column electrodes which cross the excited line electrode at the level of the pixels to be lit.
  • U la -U ca is higher than a threshold S a , allowing the lighting of an extinct pixel, that is to say at the level of which the photoconductive layer is not very conductive.
  • V e is sufficient to maintain the ignition of the pixels thus excited.
  • the alternating maintenance voltage V e produces a current maintenance through the memory display.
  • This maintenance current is broken down into a displacement current I d independent of the pixel ignition rate, and into a conduction current I c which, on the contrary, is proportional to the number of pixels lit.
  • I d displacement current independent of the pixel ignition rate
  • I c conduction current
  • FIG. 2 is a timing diagram illustrating, for a pixel, on the one hand the alternating maintenance voltage V e , on the other hand the corresponding total maintenance current I t , the pixel being assumed to be on.
  • a maintenance cycle corresponds to a period of the alternating voltage V e , that is to say for example to the time interval between the instants 0 and T2.
  • T2 is for example of the order of 1 millisecond.
  • the alternating voltage V e In a maintenance cycle, the alternating voltage V e reaches its peak value twice, once in negative and once in positive. In theory, we could therefore address two lines sequentially during a period of the maintenance voltage. For an addressing rate of 1 kHz, we can then consider a writing speed of 2000 lines per second. However, for practical reasons, some of the current addressing integrated circuits can only switch unipolar voltages. One can only use one of the peaks of the alternating voltage Ve during a period of the latter. The maximum writing speed is therefore only 1000 lines per second.
  • the row electrodes are generally made of aluminum, the column electrodes made of tin and indium oxide.
  • the line electrodes can also be made of tin and indium oxide if it is desired to produce a completely transparent display.
  • the resistance of the transparent electrodes 12, made of tin oxide and indium is not negligible. If, on the other hand, reference is made to FIG. 2, it can be seen that during the maintenance of all the pixels defined by the zone of overlap of the column electrodes by a line electrode, the peak value of the total current I t se is roughly in phase with the maintenance voltage V e if all the pixels are lit. Consequently, a voltage drop occurs on the column electrode 18 concerned, the value of which is maximum when the maintenance voltage V e reaches its maximum value.
  • the potential U c of the column electrodes of the pixels which one does not wish to light up is taken as the reference potential, it is for example equal to 0.
  • the column electrodes of the pixels which one wishes to light up are brought at the negative potential U ca in a time T c .
  • C the capacity per unit area of an extinct pixel.
  • the switching current I co of a column electrode therefore has the value defined by formula (I) (which can be found in an appendix to this description, with the other formulas). This current I co is added to the maintenance current I c (t) + I d (t) defined above.
  • the maximum height L M that the display screen can have is given by the attached formula III. It follows, first of all, that the constraints linked to the maintenance and / or the switching of the pixels limit the size of the display screen.
  • the voltage drop which exists from one end to the other of the resistive electrodes has the disadvantage of producing a heterogeneity of the ignition characteristics and extinction of the pixels, at different points on the surface of the memory display. This heterogeneity can go so far as to cause stray ignitions or, on the contrary, ignition faults on the matrix screen.
  • the present invention provides a solution to this problem.
  • An object of the invention is to reduce, in a memory display, the peak value of the currents flowing in the column addressing circuits and in the column or row and column electrodes.
  • the invention also aims to increase the speed of writing an image.
  • the memory structure is surrounded by a first and a second family of electrodes orthogonal to each other.
  • a display point or pixel is defined by the crossing zone of a particular electrode of one family and a particular electrode of the other family.
  • the display also includes a generator capable of producing an alternating maintenance voltage for the electrodes, as well as addressing means for selectively applying voltage variations relative to the maintenance voltage to electrodes of the two families, in order to to allow the addressing of one or more particular pixels.
  • the generator is able to produce several alternating phase-shifted maintenance voltages of the same frequency, and at least one of the two families of electrodes is subdivided into at least two sub-families of electrodes each receiving one of these phase-shifted maintenance voltages.
  • Reducing the peak value and the average value of the currents flowing in the column addressing circuit and in the column electrodes offers several advantages. First of all, the energy consumption of the display is reduced. Then, reducing the current flowing through the addressing circuits makes it possible to resort to circuits and more common and less expensive connectors, which results in a significant reduction in manufacturing costs of the complete display.
  • the layer has an electro-optical property with a memory effect resulting from the superposition of a photoconductive layer and an electroluminescent layer.
  • the latter can be produced so as to emit any color, the photoconductive layer having the suitable composition.
  • the material of the layer having an electro-optical property with a memory effect is for example zinc sulphide activated by manganese or any other material having an inherent memory effect.
  • two maintenance voltages are in phase opposition with respect to each other, and each applied to one of the two sub-families of electrodes.
  • four maintenance voltages are in phase quadrature with respect to each other, and each applied to one of the four sub-families of electrodes.
  • Another interesting variant of the invention consists in use three maintenance voltages phase shifted by 120 electrical degrees with respect to each other, and three sockets of electrodes.
  • the electrodes which belong to them are connected so that those which follow one another on the screen belong respectively to each of the sub-families and this in the same order for the whole screen or in a variable order (nested networks).
  • the production of the various alternating voltages required by the voltage generator is ensured using a transformer.
  • the family of column electrodes is made of tin and indium oxide and the family of row electrodes is made of aluminum.
  • the families of row and column electrodes are made of tin and indium oxide.
  • the other of the two families of electrodes is divided into at least two sub-families of parallel electrodes receiving respectively as many phase-shifted maintenance voltages.
  • the voltage variations relative to the maintenance voltage intended to modify the displayed image are placed in the time intervals between the peaks of the maintenance current flowing in the electrodes of the sub-family considered.
  • the means allowing the addressing of the pixels comprise unipolar or bipolar addressing circuits of the push-pull type.
  • FIG. 3 there is shown the equivalent diagram of an example of an addressing circuit participating in the addressing of the pixels of the memory display, object of the invention.
  • the addressing circuit 22 l is used to apply a potential U l to the line electrodes for which the pixel is not to be switched, and to apply to the line electrodes for which the pixel is desired to switch a potential U la less than U l .
  • the addressing circuit 22 l comprises two parallel loops B1 and B2 each consisting of a transistor S, a diode D of an input and an output.
  • the input of loop B1 is subject to potential U la and the input of loop B2 is subject to potential U l .
  • the output of the two loops is common and is connected to a line electrode 12.
  • the transistors S1 and S2 have a switching role and are controlled at their base by a logic stage 40 bringing the data necessary for the selection of the line electrodes participating in the pixel switching.
  • the transistor S1 is of the bipolar NPN type and the transistor S2 is of the FET NMOS type.
  • the loop transistors, B1 and B2 thus give circuit 22 l the so-called "Push-Pull" configuration.
  • the circuit 22 l is unipolar insofar as U l -U la has a sign determined by the diodes D1 and D2 connected in parallel with the transistors S1 and S2.
  • the circuit 22 can be bipolar by replacing the diodes D1 and D2 by transistors.
  • a first means of reducing the currents flowing in the display is to subdivide the family of line electrodes into two sub-families of parallel electrodes receiving two respective control voltages which are in phase opposition with respect to the other.
  • FIG 4 there is shown schematically a voltage generator coupled to a transformer phase shifting the control voltages into two voltages in phase opposition to each other.
  • the transformer 30 is a transformer whose primary winding 31 is coupled to an alternating voltage generator 20 delivering the maintenance voltage.
  • the midpoint of the secondary winding 32 is grounded. At the ends of the secondary winding, there are thus two alternating voltages 33 and 34 in phase opposition to each other. Two voltages in phase opposition can be obtained by other means, in particular logic electronic means.
  • FIG. 5 there is shown schematically a first embodiment of a memory display making use of the generator of FIG. 4.
  • a column electrode 18 and four row electrodes 12 are supplied with voltage by its respective addressing circuit 22.
  • the four line electrodes 12 are broken down into two sub-families of line electrodes: in one of the two sub-families, the electrodes 12-1 and 12-3 receive a potential V e delivered by the voltage generator 20 through line circuits CI l1 and CI l3 ; in the other of the two sub-families, the electrodes 12-2 and 12-4 receive a potential -V e , in phase opposition with respect to V e , also delivered by the voltage generator 20 through the circuits CI l2 and CI l4 .
  • the column electrode 18 is connected to the potential U c or U ca by the addressing circuit 22 c .
  • the four pixels defined respectively by the overlap areas of the four row electrodes and of the column electrode have respective capacities C1 to C4.
  • FIG 6 there is shown the equivalent diagram of a memory display. This comprises, by way of illustration, four maintenance voltages V e1 to V e4 having between them an electrical phase shift of 90 °.
  • a group of four line electrodes has been shown (individualized in 12-1 to 12-4) each comprising schematically a pixel represented individually by its respective capacity in C1 to C4 The group constitutes an elementary period of the spatial distribution of the electrodes and the pixels of the family considered, which is that of the lines in this particular representation.
  • the elementary period of the memory display with l polyphase maintenance voltages comprises l electrodes each connected to one of these voltages via the addressing circuits of the family.
  • the pixels in the lit state do not have a purely capacitive behavior.
  • the current outside the loop is zero.
  • the compensation effect is no longer total. However, it remains effective since the displacement current is canceled. If we integrate this compensation effect on the entire column electrode, we can see that the least favorable case in terms of residual current is that where the pixels defined by the overlap area of the first subfamily of row electrodes with a column electrode are in the off state and the pixels defined by the overlap area of the second subfamily of row electrodes with the column electrode are in the on state.
  • the conduction current I c is not at all compensated.
  • the reduction in the peak value of the current flowing from one end to the other of the column electrode and in the addressing circuit thereof is significant compared to the least favorable case.
  • a memory display of the prior art which is that of the fully lit column.
  • the displacement current is largely compensated regardless of the distribution of the on and off pixels.
  • This current i is obtained by the difference of the total current flowing in one of the sub-families of cross-line electrodes with the column electrode and that flowing in the other or the other sub-families of cross-line electrodes with the column electrode.
  • ia the value defined by the appended formula IV where L and d are the length and the width of the electrode considered, and where I on and I off are respectively the current densities in an on pixel and in an off pixel.
  • FIG. 7 shows a timing diagram illustrating the control of the pixels, in the particular case of the invention at two maintenance voltages in phase opposition.
  • the maintenance voltage V e applied to the electrodes and the total maintenance current I t are shown .
  • I d is compensated in accordance with the invention, I t is therefore no longer represented except by a current whose variation as a function of time is the same as that of I c .
  • the current gain compared to the display described with reference to FIG. 2 is even greater when the pixel in the lit state is in a less excited state.
  • the lesser excitation corresponds to a lesser electronic injection into the electroluminescent layer. This is particularly the case for the display with inherent memory or that with PC-EL memory with different characteristics for the PC layer. This also corresponds to a lower maintenance voltage in the display.
  • the conduction current is therefore less important relative to the displacement current.
  • the first embodiment of a memory display described with reference to FIG. 5 returns, by compensating for the current of the displacement I d and by the fact that the lit area is twice less, in the most unfavorable case in terms of residual current, with respect to the memory matrix display of the prior art, to be replaced kC by in the attached formula III.
  • This formula is valid if the two sub-families are sufficiently nested so that one can consider that the distribution of the emission along the column is homogeneous.
  • k generally takes a value between 2 and 3, so the gain over the maximum length L M that the display screen can have is a factor of 1.7 to 2.
  • the PC-EL display of the prior art has a maximum length L M of 10 centimeters while the display according to the invention has a L M of worth 17 centimeters.
  • the invention has no direct effect on the current caused by the switching of a column electrode. It is therefore necessary to choose switching conditions such that the switching currents I co do not on the one hand increase the peak values of the maintenance current I c and on the other hand do not excessively disturb the peak maintenance voltage V e in particular at the end of the column.
  • the displacement current associated with the maintenance voltage V e is fully compensated. The displacement current is therefore zero except at the time of electronic injection into the electroluminescent layer. Referring to FIG.
  • the current peak I c corresponds to the electronic maintenance injection into the electroluminescent layer.
  • F1 and F2 where the maintenance current is zero. These two windows have a duration of the order of 300 microseconds under the conditions of the display previously described with reference to FIG. 5.
  • An improvement of the invention will consist in placing the sides of the trapezoidal potential increase U c -U ca in these two windows.
  • the first means of reducing the currents flowing in the display in accordance with the invention by subdividing the family of line electrodes into two sub-families of parallel electrodes receiving two respective control voltages which are in phase opposition one by compared to the other thus allows, compared to a display of the prior art, a reduction of the peak current passing through the column addressing circuits by a factor of 3 to 4, also resulting in an increase in the maximum length of the column electrodes by a factor of 1.7 to 2 and a doubling of the writing speed of an image.
  • the means of reducing the currents flowing in the memory display in accordance with the invention is to subdivide the family of line electrodes into several sub-families of parallel electrodes receiving as many respective control voltages whose phases are regularly distributed over 2 ⁇ radians.
  • the means of reducing the currents flowing in the memory display in accordance with the invention is to subdivide the family of line electrodes into several sub-families of parallel electrodes receiving as many respective control voltages whose phases are regularly distributed over 2 ⁇ radians.
  • each group R1 and R2 undergoes the subdivision described with reference to FIG. 5, the two groups R1 and R2 of n / 2 line electrodes each are thus divided into two subgroups of n / 4 line electrodes each, one sub-groups being maintained by a potential U l1 or U l2 and the other by a potential -U l1 or -U l2
  • the two sub-groups of each group R1 and R2 are nested or even interdigitated. In this way, the maintenance displacement currents are compensated for.
  • the most unfavorable case for the reduction of the currents flowing in the display is the case where the pixels of a sub-group of line electrodes of the group R1 and of the group R2 are all lit and where the pixels of the other sub-groups are all off.
  • the compensation for the conduction currents in the resistive column electrodes cannot be taken advantage of.
  • FIG. 8 there is shown a timing diagram illustrating the control of the pixels in the case where the voltages applied to the line electrodes are in phase quadrature with respect to each other.
  • Four maintenance voltages V e1 , V e2 , V e3 , V e4 are shown which are in phase quadrature with respect to each other.
  • the total maintenance current I t associated with these voltages is also shown, in the most unfavorable case where the pixels of the sub-families supplied by V e3 and V e4 are on, the others being off. According to the invention, the total maintenance current is therefore no longer represented except by a current varying in proportion to its component I c .
  • the maximum peak value of the total current I c is equal to that of one of the peaks constituting it.
  • each peak corresponds to the emission of n / 4 pixels from the column electrode only. Thanks to the invention, a factor 2 is therefore gained over the peak value of the current obtained in the display described with reference to FIG. 5.
  • the invention allows a gain of a factor of 7 on the current supplied by the column addressing circuits relative to the display of the prior art described with reference to FIGS. 1 and 2.
  • part b of FIG. 8 there is shown a timing diagram illustrating the switching of a column electrode when the voltages applied to the line electrodes are in phase quadrature with respect to each other.
  • the pixels addressed by the line electrodes subjected to V e1 and V e3 are extinguished here.
  • the dotted line placed between the two excess switching potentials U c1 -U ca1 and U c2 -U ca2 represents the additional switching potential corresponding to the ignition of the pixels addressed by the line electrodes subjected to V e3 .
  • the corresponding means of reducing the currents flowing in the display is to subdivide the family of line electrodes into three sub-families of parallel electrodes receiving three voltages of ordered which are 120 degrees electrical out of phase with each other.
  • FIG. 9 there are shown three maintenance voltages V e1 , V e2 and V e3 phase shifted by 120 electrical degrees relative to each other.
  • the total maintenance current I t associated with these voltages is, by reasoning similar to that described with reference to FIGS. 5 and 7, equal to the conduction current I c , since the displacement current I d of maintenance is fully compensated .
  • the total maintenance current I t is therefore represented by the sum of the conduction currents I c1 , I c2 and I c3 associated with the maintenance voltages.
  • These conduction currents are assigned a multiplying coefficient between 0 and 1 representing the ignition rate of the column electrode pixels belonging to the corresponding subfamily.
  • each conduction current peak I c can only take one polarity, only its amplitude can vary depending on the ignition rate of the pixels of the electrode column considered.
  • This advantageous procedure is applicable when the number of phases of the maintenance supply is, as is the case in the present example, odd.
  • the switching current I co of the pixel maintained by the maintenance voltage V e1 is placed in temporal coincidence with the peaks of maintenance conduction current I c2 associated with the maintenance voltage V e2 .
  • the additional switching potential U c1 -U ca1 is of trapezoidal shape.
  • windows with a duration of 110 microseconds are sufficient to switch a column electrode from 0 to 45 volts without exceeding a switching current of 4 milliamps per square centimeter.
  • the invention can be generalized to a set M of maintenance voltages out of phase with each other, in opposition two by two or not, each voltage being applied to a subset R i of neither line electrodes.
  • the maintenance voltage is of simple sinusoidal shape.
  • the invention is applicable to any type of symmetrical bipolar voltage: triangular, rectangular, trapezoidal or more complex. Constraints external to the display object of the invention can impose the use of asymmetric bipolar maintenance voltages. In this case, the invention no longer allows perfect compensation for the displacement current, but we still obtain a reduction in this.
  • the invention can be combined with other power reduction techniques circulating in the PC-EL display as described in the French Patent Application No. 8611808 of August 18, 1986.
  • This technique involves using pixels at low rates filling for a PC-EL display.
  • the current delivered by the column addressing circuits is 6/35 milli-amperes per square centimeter, that is to say 0.17 milli-amperes per square centimeter. Therefore, addressing a column 10 centimeters long and 300 micrometers wide requires peak currents of only 50 micro-amps.
  • the low pixel filling rate leads to an increase in the resistance of the column electrodes, therefore to an increase in the apparent surface resistance R.
  • an appropriate electrode design makes it possible to limit this increase in R to a factor 2 only, ie at a typical value of 50 ohms. Under these conditions, a gain of a factor 9 to 10.5 is obtained over L M compared to the prior art, ie an L M of 1 meter for a tolerance of 1% on the maintenance voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Claims (13)

  1. Elektrolumineszenzanzeige mit Speichereffekt mit:
    - einer ersten Familie paralleler Elektroden (12);
    - einer zweiten Familie paralleler Elektroden (18), die senkrecht zu denen der ersten Familie sind;
    - wenigstens einer Schicht, die eine elektro-optische Speichereffekteigenschaft besitzt und von den ersten und zweiten Elektrodenfamilien eingerahmt ist, wobei ein Anzeigepunkt oder Pixel durch den Überdeckungsbereich einer bestimmten Elektrode der ersten Familie und einer bestimmten Elektrode der zweiten Familie gebildet wird;
    - einem Spannungsgenerator (20) mit einer ersten Klemme, die geeignet ist, ein erstes Potential an die Elektroden der ersten Familie anzulegen, und einer zweiten Klemme, die geeignet ist, ein zweites Potential an die Elektroden der zweiten Familie anzulegen, um permanent zwischen den ersten und zweiten Elektrodenfamilien eine Betriebs-Wechselspannung anzulegen, die geeignet ist, den dauernden Anzeigezustand der Pixel aufrechtzuerhalten;
    - Adreßvorrichtungen (22c, 221), um selektiv Spannungsänderungen bezülglich der Betriebsspannung an Elektroden der beiden Familien (12, 18) anzulegen, um den dauernden Anzeigezustand eines oder mehrerer entsprechender Pixel zu modifizieren,
       dadurch gekennzeichnet, daß der Generator wenigstens zwei erste Klemmen (33, 34) umfaßt, die jeweils zwei erste Potentiale liefern, die gegenseitig phasenverschoben sind;
       daß wenigstens die eine der Elektrodenfamilien (12) in wenigstens zwei Unterfamilien paralleler Elektroden (12-1, 12-2) unterteilt ist;
       und daß die beiden ersten Klemmen (33 und 34) gleichzeitig mit den beiden Elektrodenunterfamilien (12-1 und 12-2) verbunden sind, um wenigsten die in der anderen Elektrodenfamilie (18) und in den Adreßvorrichtungen (22c, 221) zirkulierenden Ströme zu reduzieren.
  2. Anzeige nach Anspruch 1, dadurch gekennzeichnet, daß die Schicht mit einer elektro-optischen Speichereffekteigenschaft eine photoleitende Schicht (14) und eine elektrolumineszierende Schicht (16) umfaßt, die übereinander angeordnet sind.
  3. Anzeige nach Anspruch 1, dadurch gekennzeichnet, daß das Material der Schicht mit einer elektro-optischen Speichereffekteigenschaft zum Beispiel Zinksulfid ist, das durch Mangan aktiviert wird, oder jedes andere Material ist, das Licht unter der Wirkung einer elektrischen Spannung aussendet.
  4. Anzeige nach einem der Ansprüche 1 bis 3, gekennzeichnet durch die Tatsache, daß die Betriebsspannungen der Anzahl nach zwei sind und daß sie in der Phase gegenläufig sind.
  5. Anzeige nach einem der Ansprüche 1 bis 4, gekennzeichnet durch die Tatsache, daß die Betriebsspannungen der Anzahl nach vier sind und daß sie in der Phase um 90° gegeneinander verschoben sind.
  6. Anzeige nach einem der Ansprüche 1 bis 5, gekennzeichnet durch die Tatsache, daß die Betriebsspannungen der Anzahl nach drei sind und daß sie in der Phase um 120° gegeneinander verschoben sind.
  7. Anzeige nach einem der Ansprüche 1 bis 6, gekennzeichnet durch die Tatsache, daß der Spannungsgenerator mit wenigstens einem Spannungstransformator verbunden ist, um die untereinander in der Phase verschobenen Spannungen zu erzeugen.
  8. Anzeige nach einem der Ansprüche 1 bis 7, gekennzeichnet durch die Tatsache, daß die eine (12) der beiden Elektrodenfamilien aus Aluminium besteht und daß die andere Elektrodenfamilie (18) aus Indium-Zinnoxyd oder jedem anderen leitenden und durchsichtigen Material besteht.
  9. Anzeige nach einem der Ansprüche 1 bis 7, gekennzeichnet durch die Tatsache, daß die beiden Familien aus Zeilen- (12) und Spalten- (18) Elektroden aus Indium-Zinnoxyd oder jedem anderen leitenden und durchsichtigen Material bestehen.
  10. Anzeige nach einem der Ansprüche 1 bis 9, gekennzeichnet durch die Tatsache, daß die andere (18) der Elektrodenfamilien ebenfalls in wenigstens zwei Unterfamilien paralleler Elektroden unterteilt ist, die jeweils eine der gegenseitig phasenverschobenen Betriebsspannungen erhalten.
  11. Anzeige nach einem der Ansprüche 1 bis 10, dadurch gekennzeichnet, daß die Spannungsänderungen bezüglich der Betriebsspannung, die dazu bestimmt sind, das angezeigte Bild zu modifizieren, in Zeitintervallen erfolgen, die zwischen den Spitzen des in den Elektroden der in Betracht kommenden Unterfamilie zirkulierenden Betriebsstroms liegen.
  12. Anzeige nach einem der Ansprüche 1 bis 11, dadurch gekennzeichnet, daß die Vorrichtungen, die die Adressierung der Pixel ermöglichen, unipolare Adressierschaltkreise des Push-Pull-Typs umfassen.
  13. Anzeige nach einem der Ansprüche 1 bis 11, dadurch gekennzeichnet, daß die Vorrichtungen, die die Adressierung der Pixel ermöglichen, bipolare Adressierschaltkreise des Push-Pull-Typs umfassen.
EP87402944A 1986-12-22 1987-12-21 Elektrolumineszenzanzeige mit Speichereffekt, gesteuert durch mehrfache phasenverschobene Auffrischspannungen Expired - Lifetime EP0278194B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8617985A FR2608817B1 (fr) 1986-12-22 1986-12-22 Afficheur electroluminescent a memoire a tensions d'entretien multiples dephasees
FR8617985 1986-12-22

Publications (2)

Publication Number Publication Date
EP0278194A1 EP0278194A1 (de) 1988-08-17
EP0278194B1 true EP0278194B1 (de) 1992-06-17

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EP87402944A Expired - Lifetime EP0278194B1 (de) 1986-12-22 1987-12-21 Elektrolumineszenzanzeige mit Speichereffekt, gesteuert durch mehrfache phasenverschobene Auffrischspannungen

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US (1) US4963861A (de)
EP (1) EP0278194B1 (de)
JP (1) JPS6433590A (de)
DE (1) DE3779899T2 (de)
FR (1) FR2608817B1 (de)

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* Cited by examiner, † Cited by third party
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US5432015A (en) * 1992-05-08 1995-07-11 Westaim Technologies, Inc. Electroluminescent laminate with thick film dielectric
US5302966A (en) * 1992-06-02 1994-04-12 David Sarnoff Research Center, Inc. Active matrix electroluminescent display and method of operation
US5729093A (en) * 1995-08-08 1998-03-17 Ford Motor Company Control for multiple circuit electroluminescent lamp panel
US6229506B1 (en) 1997-04-23 2001-05-08 Sarnoff Corporation Active matrix light emitting diode pixel structure and concomitant method
JP2000310969A (ja) * 1999-02-25 2000-11-07 Canon Inc 画像表示装置及び画像表示装置の駆動方法
JP3485175B2 (ja) * 2000-08-10 2004-01-13 日本電気株式会社 エレクトロルミネセンスディスプレイ
US7190008B2 (en) * 2002-04-24 2007-03-13 E Ink Corporation Electro-optic displays, and components for use therein
US8314286B2 (en) * 2003-05-23 2012-11-20 Mcneil-Ppc, Inc. Flexible liquid absorbing structure
US7633470B2 (en) 2003-09-29 2009-12-15 Michael Gillis Kane Driver circuit, as for an OLED display
US7310077B2 (en) * 2003-09-29 2007-12-18 Michael Gillis Kane Pixel circuit for an active matrix organic light-emitting diode display

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US4035774A (en) * 1975-12-19 1977-07-12 International Business Machines Corporation Bistable electroluminescent memory and display device
US4316123A (en) * 1980-01-08 1982-02-16 International Business Machines Corporation Staggered sustain voltage generator and technique
US4613793A (en) * 1984-08-06 1986-09-23 Sigmatron Nova, Inc. Light emission enhancing dielectric layer for EL panel
FR2574972B1 (fr) * 1984-12-18 1987-03-27 Thioulouse Pascal Dispositif d'affichage a effet memoire comprenant des couches electroluminescente et photoconductrice superposees
US4733228A (en) * 1985-07-31 1988-03-22 Planar Systems, Inc. Transformer-coupled drive network for a TFEL panel
FR2602897B1 (fr) * 1986-08-18 1988-11-10 Thioulouse Pascal Afficheur electroluminescent a photoconducteur a faible taux de remplissage
JP2524221B2 (ja) * 1989-05-30 1996-08-14 富士写真フイルム株式会社 集積束受渡し装置

Also Published As

Publication number Publication date
FR2608817A1 (fr) 1988-06-24
DE3779899T2 (de) 1992-12-24
US4963861A (en) 1990-10-16
EP0278194A1 (de) 1988-08-17
FR2608817B1 (fr) 1989-04-21
JPS6433590A (en) 1989-02-03
DE3779899D1 (de) 1992-07-23

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