EP0265326A1 - Method of driving an electrooptical matrix display, and driving circuit for carrying it out - Google Patents

Abstract

Control method and control circuit of an electrooptical matrix screen in which: - a) during a frame time and during the control of certain lines, the screen is controlled by voltages of a determined polarity; - b) during the same frame and during the control of the other lines, the screen is controlled by voltages of reverse polarity; - c) during the next frame this command is reversed. A C.INV inversion control circuit makes it possible to invert the voltages supplied by input circuits INV, IN, ADD.C to the column electrodes and by an addressing circuit ADD.C to the line electrodes. The invention is applicable to the control of liquid crystal screens to eliminate display faults:

Description

The invention relates to a method for controlling an electrooptical matrix screen and a control circuit implementing this method. It is applicable in particular for the control of liquid crystal screens in which the control voltages are periodically reversed.

Currently, electro-optical display panels such as liquid crystal displays are controlled by alternating signals, with the aim of increasing their lifespan. The integrated control circuits being, for economic reasons, unipolar and generally controlled between 0 volts and V volts, it is necessary to reverse the phase of the control signals either all the lines, or all the frames to obtain voltages + Vrms and -Vrms across the capacitor trapping the electrooptical material.

To control an elementary screen, such as that of FIG. 1, comprising two lines L1, L2 and two columns C1, C2, and to switch on point A intersection of the line L1 and of column C1, the operation of the screen in control mode by line inversion is represented in FIG. 2. During the time t for controlling the points (A and B) of line L1, a voltage V _X of value + V _DD is applied to line L1 during a first half of time t. Simultaneously the column wire C1 which must allow the ignition of point A is set to a potential V _Y of substantially zero value. The potential difference applied to point A is therefore + V _DD and point A lights up. The column wire C2 is brought to a potential V _Y = + V₃ supplying at the terminals of point B, a potential difference + V _DD -V₃ which is insufficient to light this point. Line wire L2 which is not controlled at this time receives a potential + V₁. The potential difference at the terminals of point C is V₁ and that at the terminals of point D is V₁ - V₃. These points are not lit.

During the second half of time t, line L1 receives a potential of V _X = 0 volts, line L2, a potential of + V₂. Column C1 receives a potential V _Y = + V _DD , and column C2, a potential V₄.

The potential difference across point A is -V _DD . This point is on. The potential differences at the terminals of points B, C and D are respectively -V₄, V _DD -V₂and V _DD -V₄. These points are not lit.

During the command time of line L1, the command was therefore reversed. During the command time of line L2, the operation would be similar.

The operation of the same screen in frame inversion control mode is represented in FIG. 3. During a first frame, the potentials applied to the wires of lines L1 and L2 are + V _DD and + V₁ and those applied to the wires of columns C1 and C2 are 0 volts and + V₃.

The potential differences at the terminals of points A, B, C and D are respectively + V _DD , V _DD -V₃, + V₁and V₁-V₃. Only point A is on.

During a second frame, the line wires L1 and L2 receive the potentials 0 volts and + V₂, the column wires C1 and C2 receive the potentials + V _DD and + V₄. The potential differences at the terminals of points A, B, C and D are respectively -V _DD , -V₄, V _DD - V₂ and V _DD -V₄. Only point A is always on.

We thus realized a command by weft inversion.

However, when we observe a screen with a high rate of multiplexing, that is to say with a number of lines N greater than 3 2, we see that in the two control modes we obtain display faults.

In the command mode with line inversion we see that in the columns where a point is lit, the other points are slightly excited. In the example of the figure 4 where point A is lit and becomes black, point C is also excited and becomes gray when it should remain white like points B and D.

In the control mode with frame inversion, point A being lit is black. Column C2 should not have an excited point, and yet we see, as shown in Figure 5, that points B and D are gray.

These anomalies are due to voltage inversions which give rise to transients during each image time and this results in parasitic voltages. These display faults are troublesome for vision because they persist as long as certain columns do not contain addressed words and remain long enough for the observer to clearly distinguish them. Such faults are visible for screens comprising more than 32 lines and whose frame time duration is approximately 20 ms.

The object of the invention is to obtain an image showing the information to be displayed on a homogeneous background. For example, as shown in FIG. 6, the aim will be to obtain an image in which point A is black and points B, C and D all white or, indeed, all gray (but with the same shade of gray ).

The invention therefore relates to a method for controlling an electro-optical matrix screen, comprising a plurality of cells arranged in rows and columns, each cell being provided with control electrodes, providing for the application to the control electrodes of each cell of at least a first control voltage of a first determined sign and at least a second control voltage of a second sign opposite to the first, characterized in that:
the cell lines being controlled during line time intervals, said time intervals can be of a first type or of a second type;
- during a determined frame time, and during the intervals of the first type, the cell lines are controlled by said first control voltage and during the intervals of the second type, the lines of the frame are controlled by said second voltage;
- During the next frame and during the intervals of the first type, the cell lines are controlled by a second voltage while during the intervals of the second type, the lines are controlled by said first voltage.

The invention also relates to a circuit for controlling an electrooptical screen implementing the above method and comprising:
a liquid crystal screen comprising cells arranged in rows and columns, each cell being controlled by a row electrode and a column electrode, and the screen comprising a determined number of rows;
- supply circuits making it possible to supply at least a first control voltage of a first determined sign and at least a second control voltage of a second sign opposite to that of the first sign;
- an inversion circuit making it possible to apply to said row and column electrodes either the first control voltage or the second control voltage;
- a line time clock determining the command time for each line;
- a frame frequency signal generator determining the display time of a frame;
characterized in that it further comprises:
- a generator of N random codes, all different, in number equal to the number N of lines, connected to the inversion circuit and making it possible, according to the value of each code, to control the inversion circuit so that it applies to each line to be controlled, during each line time, either the first control voltage or the second control voltage;
a first frequency divider by two receiving the frame frequency signal and supplying a switching signal, during every other frame, to the reversing circuit to reverse the operation of this reversing circuit.

• - la figure 1, un écran de visualisation élémentaire de l'art connu ;
• - la figure 2, un diagramme de fonctionnement de l'écran de la figure 1 en mode de commande par inversions lignes, selon l'art connu, et déjà décrit précédemment ;
• - la figure 3, un diagramme de fonctionnement de l'écran de la figure 1 en mode de commande par inversions trames, selon l'art connu, et déjà décrit précédemment ;
• - les figures 4 et 5, des exemples d'images obtenues sur les écrans de l'art connu ;
• - la figure 6, un exemple d'image obtenue sur un écran commandé selon le procédé et le circuit de l'invention ;
• - la figure 7, un diagramme représentant deux temps trames selon l'invention ;
• - la figure 8, un exemple de circuit de commande d'un écran à cristal liquide selon l'invention ;
• - la figure 9, un exemple de circuit de commande pseudo-aléatoire ;
• - la figure 10, un diagramme de fonctionnement du circuit de la figure 8 ;
• - la figure 11, un exemple de circuit de commande détaillé selon l'invention ;
• - la figure 12, un diagramme de fonctionnement du circuit de la figure 11.
• - la figure 13, un diagramme de fonctionnement du procédé de l'invention.

The various objects and characteristics of the invention will appear more clearly in the description which follows, given with reference to the appended figures which represent:

• - Figure 1, an elementary display screen of the known art;
• - Figure 2, an operating diagram of the screen of Figure 1 in control mode by line inversions, according to the known art, and already described above;
• - Figure 3, an operating diagram of the screen of Figure 1 in control mode by frame inversions, according to the known art, and already described above;
• - Figures 4 and 5, examples of images obtained on the screens of the known art;
• - Figure 6, an example of image obtained on a screen controlled according to the method and the circuit of the invention;
• - Figure 7, a diagram representing two frame times according to the invention;
• - Figure 8, an example of a control circuit of a liquid crystal screen according to the invention;
• - Figure 9, an example of a pseudo-random control circuit;
• - Figure 10, an operating diagram of the circuit of Figure 8;
• - Figure 11, an example of a detailed control circuit according to the invention;
• - Figure 12, an operating diagram of the circuit of Figure 11.
• - Figure 13, an operating diagram of the method of the invention.

As we saw previously with reference to FIGS. 1, 2, 3, it is known to modify the control voltages of the image points of the screen during each line time.

It is also known to modify these control voltages from one frame to the next. However, known systems give rise to display faults as described above.

To avoid these faults, the method of the invention provides, during a frame time T corresponding to the display of an image on the screen and having distributed this frame time in line time intervals t, to distinguish in these line time intervals intervals of a first type ta and intervals of a second type tb.

During a first frame T1, and during the time intervals ta of the first type, the control of the screen is such that the voltage at the terminals of each cell (or point) of the image has a determined value and a polarity also determined. , positive for example.

Using the examples of polarities used in the description of FIGS. 1 and 2, according to the invention a line (L1), which should give rise to the display of information during a time ta, receives a potential + V _DD .

The other lines (L2) which should not give rise to the display of information receive a potential + V₁ (see FIG. 13). Columns, such as C1, whose intersection with the line to be controlled (L1) gives rise to the lighting of a point, receive a potential of O Volt and the point of intersection (A) is subject to a difference of potentials + V _DD .

The other columns (C2) receive a potential + V₃ and the points of intersection (B) with the commanded line (L1) are subjected to a potential difference V _DD -V₃.

In FIG. 13, it can then be seen that the other points of intersection C and D are subjected respectively to potential differences of V₁ and V₁-V₃.

The other lines of the screen are commanded to display either during a time of type ta as has just been described, or during a time of type tb as will now be described.

Indeed, during a second frame T2 the potentials used during times ta are those used during times tb of the previous frame and vice versa. Which means that by describing a time of ta of the frame T2 we describe at the same time a time tb of the frame T1.

The display of the line L1 which has just been described is therefore now done with different potentials and to display the same information on the screen, the command must be as shown on the right-hand side of FIG. 13. The potentials applied are:
- on line L1: O Volt
- on line L2: + V₂
- on column C1: + V _DD
- on column C2: + V₄

The potential differences applied to the different crossing points are then:
- for point A: -V _DD
- for point B: -V₄
- for point C: V₂-V _DD
- for point D: V₂-V₄

We therefore see that the polarities of the voltages are reversed between times ta and tb and from one frame to the next, due to the switching of the voltages from times ta to time tb and vice versa, the control of each line is reversed.

During a third frame the operation becomes identical to that of the first frame, during a fourth frame the operation becomes identical to that of the second frame, and so on by alternating from one frame to the next the utility of the two types of time ta and tb.

The different line times of each frame are distributed randomly in time intervals of the first type ta and in time intervals of the second type tb. However, it is also possible to provide substantially equal numbers of times ta and times tb.

In FIG. 7, two consecutive frame times T1 and T2 have been shown. Each frame time comprises, by way of example, 8 line times t1 to t8 for the frame time T1 and 8 times t'1 to t'8 for the frame time T2. These times are divided into time of the first type ta and time of the second type tb such that each time of the second frame T2 is of the same type as the time of the same rank of the first frame T1.

According to the example shown, the times t1, t3, t4, t7 of the frame T1 and tʹ1. tʹ3, tʹ4, tʹ7 of the T2 frame are of the first type. The times t2, t5, t6, t8 of the frame T1 and tʹ2, tʹ5, tʹ6, tʹ8 of the frame T2 are of the second type.

During the frame T1 and during the times of the first type ta, not hatched in FIG. 7, the control of the screen is done as shown on the left part of FIG. 13; and during the times of the second type tb, hatched in FIG. 7, the control of the screen is done as shown on the right part of FIG. 13.

During the frame T2, the times of the first type ta and of the second tb are used in a contrary manner, this is why the times ta of the frame T2 are hatched and the times tb are not hatched.

According to the invention, provision is also made to modify the distribution of times of the first type ta and of the second tb every two frames. The system operates, as shown in FIG. 7, for two frames, then the distribution of the times ta and tb is modified to operate during the next two frames with a new distribution of the times ta and tb, and so on. Thus the possible existence of display faults can only be fleeting and will not be annoying for an observer.

Referring to Figure 8, we will describe an example of a circuit implementing the method of the invention.

An electrooptical screen such as a liquid crystal screen CL has been represented by its row electrodes and its column electrodes. For simplicity, a screen is shown comprising only 15 row electrodes L1 to L15 and 15 column electrodes C1 to C15.

The line electrodes L1 to L15 are controlled and supplied by an addressing circuit ADD.L.

The column electrodes C1 to C15 are controlled and supplied by an addressing circuit ADD.C. This one was represented by a register comprising as many stages as there are column electrodes. This addressing register receives its control information from an inversion register IN which provides for each column electrode a bit 0 or 1 An IN.V inversion circuit makes it possible to invert the content of each stage of the IN inversion register. An inversion control circuit C.INV triggers the operation of the inversion circuit INV.

All of these circuits are placed under the control of a central control circuit CC, the operation of which is controlled by a frame frequency generator GFT and a line time clock HT.

The operation of the circuits of FIG. 8 is as follows:

The HT clock provides a line time signal CK at regular intervals and controls the display, by the circuit CC and the addressing circuit ADD.L (signal CC1), of a line of the screen by application of 'a potential such as + V _DD on the line to be displayed and a potential such as + V₁ on all the other lines of the matrix as has been described in relation to FIG. 2.

Furthermore, each line time signal CK controls the recording in the register IN of information INF 1/15 to be displayed on the line to be controlled.

This information consists of as many binary elements 0 or 1 as there are column electrodes. These bits are transmitted to the column electrodes C1 to C15 by an address register ADD.C. Thus, at each line time signal, information INF 1/15 is displayed on the column electrodes C1 to C15.

The potentials supplied on the row electrodes and the column electrodes correspond to the potentials indicated previously in the description of FIG. 13.

The inversion control circuit C.INV pseudo-randomly controls the control of the screen in time of type ta or in time of type tb. Under the control of this circuit C.INV, the circuit INV reverses the value of each binary element 0 or 1 contained in each stage of the register IN. The content of the address register ADD.C is also inverted in the same way and the potentials applied to the column electrodes C1 to C15 are also inverted. Simultaneously, the circuit C.INV controls, in the addressing circuit ADD.L, the inversion of the line potentials applied to the line electrodes L1 to L15.

These potential inversions thus produced are carried out in accordance with the potential inversions described in relation to FIG. 13.

The DC control circuits and the C.INV circuit authorize such operation for a whole frame time, the C.INV circuits controlling switching of control voltages from time ta to tb and vice versa.

During the next frame, triggered by a CH pulse, the C.INV circuit reverses the use of times ta and tb.

The C.INV circuit renews the operation of the screen for the two frames which follow the two frames which have just been displayed and so on.

According to a variant of the invention, at the end of the display of the two frames which have just been displayed, the circuit C.INV modifies, every two frames, the distribution of times of the first type ta and of the second type tb.

FIG. 9 represents an exemplary embodiment of the C.INV inversion control circuit produced in the form of a pseudo-random sequence generator. It includes a shift register RD. The number of stages in this register is such that the number of bit combinations it provides covers the number of lines of the liquid crystal screen. For a liquid crystal screen of fifteen lines we therefore take a 4 floors. This register therefore has 4 inputs, 4 outputs, an offset input (DEC) and a clock input (CK).

Certain outputs of the RD register are connected to a P3 type or EXCLUSIVE gate. By way of example, FIG. 9 comprises a door with two inputs to which are connected the outputs of stages 1 and 4 of the RD register. This gate delivers a level 1 signal when its two inputs are at different logic levels (one at level 0 and the other at level 1). It delivers a signal of level 0 in the case where the two inputs are at the same logic level (either 0 or 1).

This output signal is applied to the offset input DEC of the register RD. It is also supplied on a V _S link to be used as a reverse control signal.

At the start of operation, the register RD receives on its inputs a loading word CHR such as the word 1001 as indicated in FIG. 9. From this word, the content register RD takes at each clock pulse CK a different value by shifting its content to the left and by entering a binary element 0 or 1, depending on the state of gate P3, in stage 1 of the register.

FIG. 10 illustrates an operating diagram of the circuit of FIG. 9. A loading word CHR is loaded as indicated in FIG. 10. The register RD receives the different clock pulses CK. A signal is then obtained at the output V _S having the form indicated on the line V _S in FIG. 10.

The values of the signal V _S of logic level 1 would command, for example, the control of the screen by positive voltages and the values of the signal V _S of logic level O would command the control of the screen by negative voltages.

This operation occurs during a frame. During the following frame, it is therefore necessary to invert the signal V _S.

The circuits detailed in FIG. 11 allow this operation to be implemented on several frames.

We find in Figure 11, the register RD that we have shown with 6 floors instead of 4 and the door P3.

The GFT frame generator supplies a CH frame frequency signal to a frequency divider D1 by two. This divider D1, during the different successive frames, alternately supplies a level 1 signal and a signal level 0. This signal is applied to a P2 gate of the EXCLUSIVE OR type having two inputs and which also receives the inversion control signal. Gate P2 therefore provides an inversion control signal which is identical to the signal V _S when the divider D1 supplies a level 0 signal and which reverses the signal V _S when the divider D1 supplies a level 1 signal.

In this way, as shown in the diagram of FIG. 12, the circuits of FIG. 10 allow the method of the invention to be implemented as described above.

The circuits of FIG. 11 also allow the loading word CHR supplied to the register RD to be changed during operation.

For this, a counter CP having as many outputs as the register RD has inputs provides a loading word to the register RD.

A frequency divider D2 by two receives the signal supplied by the divider D1. It controls the advancement of the counter CP every two frames. Each time the counter CP advances, the loading word CHR changes value. Thus the loading word CHR supplied to the register RD remains the same for two frames allowing the reverse operations on two frames as explained above. During the following two frames, this operation is repeated with a different loading word.

It will be noted that a loading word of value 000000 would lead to a blocking of the register RD in this position. The circuits of FIG. 11 therefore plan to detect such a word supplied by the counter CP and to force the register RD into a position other than 000000. This detection and this forcing can be carried out in the following manner.

The detection is carried out by a gate P1 of the NAND type with 6 inputs connected to the outputs of the counter CP and the output of which is connected to a gate P4 of the EXCLUSIVE OR type. Forcing is carried out by gate P4 which receives a signal CP counter output and P1 gate output signal. Gate P4 controls an entry in the RD register.

It is obvious that the above description has been given by way of example only. The types of circuits (doors, registers, counters) in particular, as well as the numbers of rows and columns of the screen to be controlled, can be different without departing from the scope of the invention.

Claims (10)

1. A method of controlling an electrooptical screen comprising a plurality of cells arranged in rows and columns, each cell being provided with control electrodes, providing for the application to the control electrodes of each cell of at least a first voltage of control of a first determined sign and at least a second control voltage of a second sign opposite to the first, characterized in that:
the cell lines being controlled during line time intervals, said time intervals can be of a first type or of a second type;
- During a determined frame time, and during the intervals of the first type the cell lines are controlled by said first control voltage, and during the intervals of the second type, the lines of the frame are controlled by said second voltage;
- During the next frame and during the intervals of the first type the cell lines are controlled by said second voltage while, during the intervals of the second type, the lines are controlled by said first voltage. 2. Control method according to claim 1, characterized in that the line times are distributed in intervals of the first type and in intervals of the second type at the start of a frame, this distribution remaining unchanged during two frames and then being modified every frames. 3. Control method according to claim 1, characterized in that the times of the first type and the times of the second type are distributed randomly in the frame time. 4. Control method according to claim 1, characterized in that the number of line time intervals of the first type is substantially equal to that of line time of the second type. 5. Control circuit of an electrooptical screen implementing the method according to any one of the preceding claims, comprising:
- a liquid crystal screen comprising cells arranged in rows and columns each cell being controlled by a row electrode and a column electrode, and the screen comprising a determined number (N) of rows;
- supply circuits making it possible to supply at least a first control voltage of a first determined sign and at least a second control voltage of a second sign opposite to that of the first sign;
- an inversion circuit making it possible to apply to said row and column electrodes either the first control voltage or the second control voltage;
- a line time clock determining the command time for each line;
- a frame frequency signal generator determining the display time of a frame;
characterized in that it further comprises:
- a generator of N random codes, all different, in number equal to the number N of lines, connected to the reversing circuit and allowing, depending on the value of each code, to control the reversing circuit so that it applies to each line to be controlled, during each line time, either the first control voltage or the second control voltage;
- A first frequency divider by two receiving the frame frequency signal and providing a switching signal, during every other frame, to the inversion circuit to reverse the operation of this inversion circuit. 6. Control circuit according to claim 5, characterized in that the random code generator comprises
- a shift register (RD) comprising as many outputs as necessary to supply a number (N) of codes equal to the number (N) of lines;
- a combinational logic circuit connected to the outputs of this register detecting certain determined code values and supplying a binary signal 0 or 1 which is fed back to a register offset input and which is supplied to the inversion circuit to control, depending on the value signal binary, supplying either the first control voltage or the second control voltage. 7. Control circuit according to claim 6, characterized in that it comprises a logic gate with two inputs of the EXCLUSIVE OR type receiving on one input said binary signal and on the other input said switching signal and providing on an output a inversion control signal to the inversion circuit whose different successive sequences supplied during a frame are inverse with respect to the same sequences of a neighboring frame. 8. Control circuit according to claim 6, characterized in that the combinational logic circuit is an EXCLUSIVE OR gate comprising a number of inputs connected to outputs of the shift register (RD). 9. Control circuit according to claim 8, characterized in that the EXCLUSIVE OR gate has two inputs connected to two outputs of the shift register. 10. Control circuit according to claim 5, characterized in that it also comprises:
- a binary counter comprising as many outputs as the shift register has stages and connected to inputs of the shift register;
a loading command register connected to the first frequency divider, receiving the switching signal and controlling, at each transition of the switching signal, the loading of the content of the binary counter into the shift register;
a second frequency divider by two receiving said switching signal and providing a signal for advancing the binary counter.

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