EP2174315B1 - Integrated method of detecting an image defect in a liquid crystal screen - Google Patents

Integrated method of detecting an image defect in a liquid crystal screen Download PDF

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Publication number
EP2174315B1
EP2174315B1 EP08786848.5A EP08786848A EP2174315B1 EP 2174315 B1 EP2174315 B1 EP 2174315B1 EP 08786848 A EP08786848 A EP 08786848A EP 2174315 B1 EP2174315 B1 EP 2174315B1
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EP
European Patent Office
Prior art keywords
image
signal
display
video
chain
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EP08786848.5A
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German (de)
French (fr)
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EP2174315A1 (en
Inventor
Hugues Lebrun
Gérard Voisin
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Thales SA
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Thales SA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications
    • G09G2380/12—Avionics applications
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Definitions

  • the present invention relates to a method for detecting image defects in liquid crystal displays.
  • the invention applies more particularly to liquid crystal displays used on vehicle dashboards, in particular aircraft.
  • Liquid crystal color displays are universally used in aircraft and helicopter cockpit visualization systems. They constitute an essential human-machine interface, providing the pilot, with elaborate symbolic images, with the information he needs to carry out his various missions. This displayed information must therefore be very reliable.
  • n-bit shift register it is a semiconductor device comprising n cascading stages, the output of each stage forming the input of the next.
  • Each stage comprises a plurality of semiconductor transistors. These transistors must provide many switches. Some of these transistors are permanently subjected to a gate stress, which can lead to a drift of their threshold voltage and consequently a malfunction of the transistor: the transistor no longer switches. In a switching stage in which a transistor no longer switches, the transfer of data is no longer made; the data output from this floor and subsequent floors will therefore no longer change.
  • the lines controlled by the output of these stages will therefore always remain in the same unselected state: the scanning of the selection lines of the matrix is no longer done.
  • line scan interruption occurs.
  • the pixels of an LCD display have excellent information storage performance. The same image can thus be displayed for several seconds after this interruption.
  • Another display defect is the loss of video information in the transmission chain of the image, for example related to a failure of a color video channel.
  • the red color is used to display warning signals. It is conceivable that a failure of the red video channel is not quickly detected by the pilot on an operational image. In this case, the pilot may react too late. It is thus necessary to be able to identify this defect.
  • a driver may not notice a display defect, especially since some symbolic images associated with information useful to the pilot do not change very quickly. He could therefore continue to trust the image displayed, while it is not or more correct.
  • the safety recommendations of civil avionics prohibit this type of event. It is therefore necessary to provide a system for detecting a display error.
  • the detection of this defect is usually performed by ensuring in the output signal of the last stage shift registers, the synchronous presence of the line scan signal on this output.
  • This method has different disadvantages. It requires being able to physically measure the signal at the output of the last stage, and thus to provide an additional conductive line, dedicated to this measurement. In addition, the measured information is that of the last line of the shift register.
  • the fault can be located further, at the voltage rise circuit which is usually provided between the outputs of the shift register and the rows of the matrix, to pass digital voltage levels, in the shift registers, at the analog voltage levels necessary to control the picture points.
  • the fault detection consists of detecting the presence of a video signal at the input of the column control circuits, which is very insufficient. In particular, this gives no information on the operation of the shift register and / or the digital conversion circuit and / or the amplification circuit of the column control devices and does not ensure the integrity of the display of a particular color .
  • the red color corresponds to the display of information related to security. There is therefore a certain interest in being able to ensure the integrity of the display chain of this color at least.
  • the publication WO 2006/036391 proposes to measure the current consumed in a screen, in order to model the power consumption. This should make it possible to perfectly size the battery for the application, and also manage the battery according to the instantaneous consumption and manage the refreshing rate of the images.
  • the subject of the invention is a more efficient image defect detecting method, which reliably tests the integrity of the entire video display chain.
  • the invention relates to an integrated method for detecting an image display failure in an operationally operative LCD screen comprising pixel electrodes arrayed in a row of data and selection lines, a common counter electrode, and means for displaying an image driven by a video signal, and applying control voltage levels on said pixel electrodes via said data and selection lines and on the counter electrode, said video signal, the means for display, the selection and data lines and the pixel electrodes forming a video command chain for displaying an image, characterized in that it consists of a verification of the integrity of said video channel, said verification comprising activating a current measurement chain on at least one power supply bus of said display means to obtain a signal representative of current currents when capacitance charging or discharging of the data lines and / or selection of the LCD screen and comparison of this signal with an expected signal (Sc) derived and synchronous from a selection line scanning signal, to generate a signal detecting an image defect where appropriate, such as a measurement chain associated with the selection lines is activated during periods of video image displays, and /
  • the method comprises integrating a measurement chain comprising a resistor arranged in series on the power supply bus, a circuit for measuring the current in said resistor and outputting a corresponding digital measurement signal, and a comparing circuit of said digital measurement signal being provided to provide if necessary an image defect detection signal.
  • the invention also relates to a liquid crystal screen comprising corresponding integrated detection means.
  • the figure 1 takes an architecture of an LCD screen.
  • This architecture is well known. It comprises a matrix array of pixels or image dots, each constituted by a switching device and an electro-optical cell of which an electrode called a pixel electrode is connected to the switching device, and the other electrode referred to as the counterelectrode CE is an electrode common to all the pixels.
  • the matrix 10 comprising the pixel electrodes and their switching devices is made on a substrate plate.
  • the counter-electrode CE is made on a counter-plate of the screen which also supports the colored filters.
  • the display of an image on such a screen is achieved by means of display allowing the application of appropriate control levels on the electrodes of the pixels.
  • the common pixel electrode or against the CE electrode, it receives a control voltage VCE appropriate to the addressing mode of the screen, by a respective DC voltage supply bus.
  • the pixel electrodes their addressing is carried out via selection lines L i , i integer, i ⁇ [1, ... n], which each control the on or off state of the devices. switched on this line, and columns or lines of data, Col Rj , Col Gj , Col Bj , which each transmit a voltage corresponding to a gray level to be displayed, on the electrode of a selected pixel, arranged on the column.
  • a color screen was chosen, with a matrix of color filters with three colors R red, G green and B blue (made on the backplate). There is thus an arrangement of columns corresponding to the chosen color scheme.
  • the addressing circuits of these pixel electrodes comprise a control circuit 20 of the selection lines, called “line driver” in the technical literature and a data control circuit 30, called “column driver” in the technical literature.
  • These control circuits may be integrated circuits to the active matrix (that is to say they are made on the same substrate plate as the active matrix) or external circuits. In the latter case, they are connected to the active matrix by an appropriate connection mode, for example by heat-sealing, transfer of the integrated circuits on the glass called COG report (" Chip On Glass ”) or any other connection mode.
  • the control circuit 20 for selection lines mainly comprises a shift register 21 (which may in practice be formed of several linked circuits, depending on the number n of rows of the matrix), to address sequentially, to a vertical scanning frequency, each of the grid lines of the matrix: the scanning signal S swp is applied to the input of the first stage of the register and is progressively transferred to the following stages at the scanning frequency (line frequency) defined by the driver control clock line.
  • the circuit 20 also comprises a voltage booster circuit 22, connected between the register and the lines. Its function is to transform the low voltage levels at the output of the shift register (typically 3 volts logic) into analog signals, voltage levels Vgon and Vgoff, suitable for the technology of switching devices (transistors) pixels.
  • the voltage Vgon is that which switches the transistors of a line L i selected in the on state (closed), which makes it possible to apply the video voltage applied to the columns, on the corresponding pixels, all the transistors other lines L k , k ⁇ i, having their gate pulled at voltage Vgoff, to keep them in the off state (open).
  • the data control circuit 31 receives as input the video signal S video to be displayed, to apply the voltages on the columns of the matrix corresponding to the gray levels to be displayed for each image. It mainly comprises a shift register (which may in practice be formed of several circuits or components chained, as a function of the number m of columns of the matrix), which drives the sample-and-hold circuit which allows the memorization on a circuit 32 included in the circuit 30 of the video signal to be displayed on the columns. Each stored data indicates for a column of the matrix, the level of gray to apply. It is transferred to the rate of selection of the lines on a circuit 33 comprising digital / analog converters. Typically, a gray level is coded on 6 or 8 bits.
  • the circuit 33 thus comprises digital / analog converters and current amplifiers associated with coding tables for supplying and applying the corresponding analog voltage levels on the columns, at the selection line selection rate: at each new selected line the contents of the previously sampled data registers are input to the converters, which each output a corresponding analog voltage level. The output of these converters is connected to a current amplifier whose function is to quickly load the column during the selection of the line.
  • the digital-to-analog converters as well as the current amplifiers are powered by a DC voltage supply bus DDA (13 volts in one example).
  • the addressing circuits of the pixels of the screen comprise, in a known manner, other control devices, in particular to reverse the polarity of the voltage applied to the pixels (line, column or point inversion), or to take account of the structure the colored filter of the matrix (quad structure, stripe ...) ....
  • an integrated test method measures the current on the active associated power buses during the transmission. load columns with the analog voltage corresponding to the desired gray level in the image. It is shown that this current measurement makes it possible to check the integrity of the entire video display chain.
  • the rows and columns of the matrix are capacitive lines, which are loaded and / or discharged at the line or horizontal frequency.
  • the capacity of each line, and the equivalent capacity of the columns are high.
  • the columns also have a strong capacitive coupling with the V CE signal applied to the counter-electrode. It is thus possible to measure a positive or negative current call corresponding to the charging or discharging of these lines on a corresponding power bus: Vgon for the lines; V DDA and / or V CE for columns.
  • This current draw can only be done if the voltage is actually applied to the rows and / or the columns of the matrix: that is to say if the line is well selected and / or if the video data is correctly applied to the columns.
  • This current measurement thus makes it possible to verify not only the correct operation of the shift registers 21, or 31, but more generally upstream circuits, which bring the input signal S swp or S video , and downstreams which apply an analog voltage to a line / or corresponding column: for the addressing of the lines, it will be the circuit 22 of voltage rise. For the addressing of columns it will be all the chain of connection and storage, switching, digital conversion and amplification (circuits 32 and 33).
  • the figure 2 illustrates the principle of a current measuring chain 40 according to the invention. It mainly comprises a resistor Rm associated with a current measurement circuit A, which supplies a measurement signal Sm.
  • the resistor Rm is connected in series on the power supply bus V DD and a DRV driver of a capacitive line LC.
  • This signal is then compared (circuit 42) with an expected signal Sc, typically a synchronous pulse signal of the line scanning signal, to provide a fault detection signal Sd.
  • This signal is then typically processed by an alarm management device 50, generally external, specific to the application using the screen concerned, to provide an alarm signal AL if appropriate.
  • this detection signal Sd will thus typically be routed to the display system and more particularly to the alarm management part: audible alarm and / or safety message, by indicator light.
  • the measuring circuit 40 is placed upstream of the line and column or counter electrode control circuits 20 and 30, ie between the "analog" supply bus and the corresponding supply input. in the control circuit. Indeed, in this upstream part, it is outside the glass supporting the active area of the matrix and quite generally on a printed circuit, which facilitates the integration of the measurement chain.
  • the second measurement chain 40B can be replaced or completed by another measurement chain 40c shown in dashed lines in the figure, and placed on the supply bus VCE which supplies the counter-electrode CE. It comprises a resistor Rmc placed in series on the power bus, between the bus and the feed input of the counter-electrode. It outputs a corresponding detection signal Sdc. It has been seen that the columns have a strong capacitive coupling with the counter-electrode. The current measurement for the columns can thus be done on one and / or the other bus VDDA and / or VCE.
  • an image defect detecting method can, as shown in FIG. figure 2b , include a measurement string for the rows and a measurement string for the columns. This is the optimal configuration for detecting faults that lead to the problem of frozen image. However, depending on the needs of the intended application, one can be satisfied with a single string, either associated with the lines, or associated with the columns.
  • the implementation of the detection method differs. It is recalled that the display of an image on an LCD screen is sequenced by image, at a frame period T, comprising a display period VW of the image during which the selection lines are selected one by one in sequence, and the corresponding video data applied to the columns, and a non-display period NVW, during which no line is selected. Such a sequence is illustrated as an example on the figure 3 . For a 50 Hz video display, there is a frame period T of 20 ms of which about 16 ms are used for the effective image display, in the display period VW.
  • the measurement chain 40A associated with the lines must therefore be activated in the display period VW in which the lines are actually selected: outside this period, that is to say in the NVW periods, no line is selected; by therefore it is normal not to detect a current draw on the Vgon power supply.
  • the VW display period it is not possible to make a significant measurement of current, because the different voltage levels corresponding to the different gray levels to display for a given image can more or less compensate for charge / discharge depending on the nature of the image to display.
  • the Figures 4 and 5 thus illustrate more particularly the method of testing the control circuit of the selection lines.
  • This method integrates the measurement chain 40A previously described ( figure 2b ).
  • the lines are selected one by one in sequence, as illustrated on the figure 4 : a voltage pulse Vgon is applied on each line, at the vertical scanning frequency.
  • the lines are all Vgoff.
  • the measurement chain 40A will be able to measure a current corresponding to the current draw caused by the load of the corresponding selection line.
  • These current I calls on the Vgon power bus in correspondence with each Vgon pulse are illustrated on the figure 4 .
  • the current measuring circuit 41 of the chain is designed to output a measurement pulse signal Sm, each pulse corresponding to the detection of a current draw.
  • This signal is compared to a line frequency signal Sc, typically derived from a synchronous clock signal of sweep signal S swp .
  • this signal is "flat" in windows off NVW display.
  • This comparison circuit can be typically realized by means of a NAND gate type logic circuit. When there is no pulse in the measurement signal, this comparison circuit provides a logic voltage pulse output: it is the detection signal Sd.
  • This signal is processed by an alarm management device (device 50 - figure 2a ).
  • This management device can implement rules for generating a corresponding ALA alarm signal. For example, a rule can set a minimum number of (default Sd fault) faults for generate an alarm. In the example shown on the figure 5 As an illustration of the measurement method, a sequence of four faults is required to generate an alarm, which is then appropriately processed by a security system of the application concerned. It should be noted that any alarms are generated during the measurement / detection periods, that is to say in the VW periods.
  • a resistor RmA of low impedance is sufficient, of the order of 10 ohms for example.
  • a resistor RmA of low impedance is sufficient, of the order of 10 ohms for example.
  • a selection line of the order of 200 picofarads loaded in 0.5 ⁇ s at Vgon equal to 30 Volts, a peak charge current I (Vgon) of the order of 12mA.
  • FIGs 6 and 7 illustrate more particularly the method of testing the column control circuit. This method integrates the measurement chain 40B and / or the measurement chain 40c previously described ( figure 2b ), the detection principle applying identically on these two chains.
  • This detection principle consists in controlling the display of a test image S test in the non-display NWM periods: this test image is determined, programmed, to control on the columns of the matrix the same first level of gray, or the same second level of gray, alternatively to the line frequency (ie the frequency of selection of the lines, except that the lines are not selected).
  • the first and second gray levels correspond respectively to the lowest and the highest level of the gray scale, ie to the maximum voltage excursion.
  • NWM of a frame all these columns are then alternately brought to the maximum voltage, and the minimum voltage, to the line frequency. This significant modification of the line-frequency column signal creates a large current draw on the VDDA and VCE power buses, which is detected.
  • the implementation of the method thus causes the column driver 30 to operate during the entire frame, in the period VW, to display a video image S video , and in the period NVW to fictitiously display a test image S test .
  • the display is "fictitious" because in these NVW periods, the lines are not selected: the test image is not actually displayed on the screen.
  • test sequence maxima / minima is interesting because it allows to test the control of gray levels at both ends of the chain.
  • test sequence may only require the display of a predefined gray level, the same from one line to another. It is preferably the highest or lowest gray level of the greyscale, to cause a sufficient charging or discharging current draw.
  • the video test image will be one in two column views.
  • columns for displaying the test image are selected to correspond to a single color, the columns associated with the other one or the other colors being unselected.
  • the data to be displayed concern the only red columns Col Rj .
  • the other columns Col Gj , Col 8j remain at a stable voltage level during these periods NVW so as to reduce their contribution to current calls.
  • the test image is such that the red columns switch at the line frequency alternately from the black level to the white level, to have the maximum of the voltage swing, and the other columns keep a stable gray level, for example. example white.
  • Successive test sequences can be provided for successively testing each of the colors at test frequencies which can be chosen according to the importance of each color for the application in question.
  • the figure 7 illustrates the detection method with signals Sm, Sd and ALB, which is similar to that of the line driver ( Figure 5 ).
  • the comparison signal Sc used is also similar.
  • test sequence of the column driver 30 may also depend on the addressing mode of the screen that is tested.
  • a screen using an addressing mode of the at least one column inversion type typically an online repeat of a red pattern R, green V, blue B, two columns successive reds are one controlled with a positive voltage polarity, and the other a negative voltage polarity.
  • R, green V, blue B two columns successive reds are one controlled with a positive voltage polarity, and the other a negative voltage polarity.
  • the test sequence will use a video test image programmed to match a red color display every other column. This of course comes down to each color.
  • the display of a test image according to the invention results in a modification to the line frequency of the column signal on columns selected for the test, to create a corresponding large current draw in the bus.
  • VDDA and VCE supply possibly with other columns in an appropriate state reducing their contribution to current calls.
  • the measurement chain 40B and / or 40c is associated with means for storing / generating at least one test S test image . If one wants to test each of the colors, the same image can be used, each time, in combination with a selection of columns of the corresponding color.
  • These storage / generation means are made in any manner known to those skilled in the art.
  • the column driver or column driver circuit is in practice formed of a plurality of chained components, each controlling a group of columns.
  • the measurement chain for the columns 40B and / or 40c makes it possible to separately test a component of the column driver, to detect a possible fault.
  • a corresponding test method then comprises a command for displaying a test image, corresponding to a selection of the columns of this particular component of the column driver. It is thus possible to test each of the components of the column control circuit, with a sequence of test images, each image defined for a specific component of the driver by using the test method previously described in relation to the Figures 6 and 7 .
  • the figure 8 gives a practical example of a measurement chain that can be used in the invention.
  • the resistor Rm is inserted in series into the VDD power supply of the tested driver.
  • a differential amplifier for example an ANALOG DEVICE AD817 amplifier, makes it possible to reject the parasites of the power supply.
  • the amplifier is chosen with a fairly narrow bandwidth (Wien network) to improve the S / B ratio of the output Out of the amplifier.
  • a comparator 2 whose threshold can be set according to the LCD screen and the application converts the analog signal Out into a digital signal Sm. The presence and the duration of the pulses at the output of the comparator 2 depend on current calls in the measuring resistor Rm.
  • the image defect detection method which has just been described can be integrated simply into any liquid crystal screen which it contributes to guarantee the integrity.

Description

La présente invention concerne un procédé pour détecter des défauts d'image dans les écrans à cristal liquide. L'invention s'applique plus particulièrement aux écrans à cristaux liquides utilisés sur les tableaux de bord de véhicule, en particulier des aéronefs.The present invention relates to a method for detecting image defects in liquid crystal displays. The invention applies more particularly to liquid crystal displays used on vehicle dashboards, in particular aircraft.

Les écrans couleur à cristal liquide sont universellement utilisés dans les systèmes de visualisation des cockpits d'avions et d'hélicoptères. Ils constituent une interface homme-machine essentielle, fournissant au pilote, au moyen d'images symboliques élaborées, des informations qui lui sont nécessaires pour mener à bien ses différentes missions. Ces informations affichées doivent donc être très fiables.Liquid crystal color displays are universally used in aircraft and helicopter cockpit visualization systems. They constitute an essential human-machine interface, providing the pilot, with elaborate symbolic images, with the information he needs to carry out his various missions. This displayed information must therefore be very reliable.

Or il arrive que ces écrans présentent des défauts d'affichage, et notamment un défaut dit d'image figée, correspondant à un défaut dans la chaîne d'affichage vidéo, généralement du à un défaut de fonctionnement dans les registres à décalage des circuits intégrés de commande (drivers) ligne ou colonne par lesquelles l'affichage de la vidéo sur l'écran est contrôlé ou à un défaut de présence du signal de synchronisation du balayage vertical en entrée de l'écran LCD.However, it happens that these screens have display defects, and in particular a so-called frozen image defect, corresponding to a defect in the video display chain, generally due to a malfunction in the shift registers of the integrated circuits. command line or column (drivers) by which the display of the video on the screen is controlled or a lack of presence of the vertical scanning synchronization signal at the input of the LCD screen.

La structure d'un registre à décalage est bien connue. Considérons un registre à décalage de n bits : c'est un dispositif semiconducteur comprenant n étages en cascade, la sortie de chaque étage formant l'entrée du suivant. Chaque étage comprend une pluralité de transistors semi-conducteurs. Ces transistors doivent assurer de nombreuses commutations. Certains de ces transistors subissent en permanence un stress de grille, ce qui peut entraîner une dérive de leur tension de seuil et par suite, un dysfonctionnement du transistor : le transistor ne commute plus. Dans un étage de commutation dans lequel un transistor ne commute plus, le transfert des données ne se fait plus ; les données en sortie de cet étage et des étages suivants ne vont donc plus changer. S'agissant des registres à décalage du circuit de commande de sélection des lignes, les lignes commandées par la sortie de ces étages vont donc rester toujours dans le même état non sélectionné : le balayage des lignes de sélection de la matrice ne se fait plus. Supposons qu'une telle interruption du balayage ligne se produise. Compte tenu de la résistivité très élevée des cristaux liquides et des transistors dans l'état bloqué, les pixels d'un écran LCD ont une excellente performance de stockage de l'information. La même image peut ainsi rester affichée plusieurs secondes, après cette interruption.The structure of a shift register is well known. Consider an n-bit shift register: it is a semiconductor device comprising n cascading stages, the output of each stage forming the input of the next. Each stage comprises a plurality of semiconductor transistors. These transistors must provide many switches. Some of these transistors are permanently subjected to a gate stress, which can lead to a drift of their threshold voltage and consequently a malfunction of the transistor: the transistor no longer switches. In a switching stage in which a transistor no longer switches, the transfer of data is no longer made; the data output from this floor and subsequent floors will therefore no longer change. As regards the shift registers of the line selection control circuit, the lines controlled by the output of these stages will therefore always remain in the same unselected state: the scanning of the selection lines of the matrix is no longer done. Suppose that such line scan interruption occurs. Given the very high resistivity of the liquid crystals and the transistors in the off state, the pixels of an LCD display have excellent information storage performance. The same image can thus be displayed for several seconds after this interruption.

Un autre défaut d'affichage est la perte d'une information vidéo dans la chaîne de transmission de l'image, par exemple liée à une défaillance d'une voie vidéo couleur. Par exemple, la couleur rouge est utilisée pour afficher les signaux d'alerte. Il est concevable qu'une défaillance de la voie vidéo rouge ne soit pas rapidement détectée par le pilote sur une image opérationnelle. Dans ce cas, le pilote peut avoir une réaction trop tardive. Il est ainsi nécessaire de pouvoir identifier ce défaut.Another display defect is the loss of video information in the transmission chain of the image, for example related to a failure of a color video channel. For example, the red color is used to display warning signals. It is conceivable that a failure of the red video channel is not quickly detected by the pilot on an operational image. In this case, the pilot may react too late. It is thus necessary to be able to identify this defect.

Un pilote peut ne pas s'apercevoir d'un défaut d'affichage, d'autant plus que certaines images symboliques associées à des informations utiles au pilote, ne varient pas très vite. Il pourrait donc continuer à se fier à l'image affichée, alors qu'elle n'est pas ou plus correcte. Les recommandations de sécurité de l'avionique civile interdisent ce type d'événement. Il est donc nécessaire de prévoir un système de détection d'un défaut d'affichage.A driver may not notice a display defect, especially since some symbolic images associated with information useful to the pilot do not change very quickly. He could therefore continue to trust the image displayed, while it is not or more correct. The safety recommendations of civil avionics prohibit this type of event. It is therefore necessary to provide a system for detecting a display error.

Selon l'état de l'art, pour le circuit d'adressage des lignes de sélection, la détection de ce défaut est habituellement réalisée en s'assurant dans le signal de sortie du dernier étage des registres à décalages, de la présence synchrone du signal de balayage ligne sur cette sortie.According to the state of the art, for the addressing circuit of the selection lines, the detection of this defect is usually performed by ensuring in the output signal of the last stage shift registers, the synchronous presence of the line scan signal on this output.

Cette méthode a différents inconvénients. Elle nécessite de pouvoir mesurer physiquement le signal en sortie du dernier étage, et donc de prévoir une ligne conductrice supplémentaire, dédiée à cette mesure. En outre, l'information mesurée est celle de la dernière ligne du registre à décalage. Or le défaut peut se situer plus loin, au niveau du circuit d'élévation de tension qui est habituellement prévu entre les sorties du registre à décalage et les lignes de la matrice, pour passer des niveaux de tension numérique, dans les registres à décalage, aux niveaux de tension analogique nécessaires pour commander les points image.This method has different disadvantages. It requires being able to physically measure the signal at the output of the last stage, and thus to provide an additional conductive line, dedicated to this measurement. In addition, the measured information is that of the last line of the shift register. However, the fault can be located further, at the voltage rise circuit which is usually provided between the outputs of the shift register and the rows of the matrix, to pass digital voltage levels, in the shift registers, at the analog voltage levels necessary to control the picture points.

Pour le circuit de commande de l'affichage des données vidéo sur les colonnes, la détection de défaut consiste à détecter la présence d'un signal vidéo en entrée des circuits de commande de colonne, ce qui est très insuffisant. Notamment cela ne donne aucune information sur le fonctionnement du registre à décalage et /ou du circuit de conversion numérique analogique et/ou du circuit d'amplification des dispositifs de commande des colonnes et ne permet pas de s'assurer de l'intégrité de l'affichage d'une couleur en particulier. Or dans le contexte de l'avionique civile, la couleur rouge correspond à l'affichage d'informations liées à la sécurité. Il y a donc un intérêt certain à pouvoir s'assurer de l'intégrité de la chaîne d'affichage de cette couleur au moins.For the control circuit of the display of the video data on the columns, the fault detection consists of detecting the presence of a video signal at the input of the column control circuits, which is very insufficient. In particular, this gives no information on the operation of the shift register and / or the digital conversion circuit and / or the amplification circuit of the column control devices and does not ensure the integrity of the display of a particular color . In the context of civil avionics, the red color corresponds to the display of information related to security. There is therefore a certain interest in being able to ensure the integrity of the display chain of this color at least.

La publication WO 2006/036391 propose de mesurer le courant consommé dans un écran, dans le but de modéliser la consommation de courant. Cela doit permettre de dimensionner parfaitement la batterie pour l'application, et également gérer la batterie en fonction de la consommation instantanée et gérer la fréquence de rafraichissement des images.The publication WO 2006/036391 proposes to measure the current consumed in a screen, in order to model the power consumption. This should make it possible to perfectly size the battery for the application, and also manage the battery according to the instantaneous consumption and manage the refreshing rate of the images.

L'invention a pour objet un procédé de détection de défaut d'image plus performant, qui permet de tester de manière fiable l'intégrité de l'ensemble de la chaîne d'affichage vidéo.The subject of the invention is a more efficient image defect detecting method, which reliably tests the integrity of the entire video display chain.

L'invention concerne un procédé intégré pour la détection d'un défaut d'affichage d'une image dans un écran LCD fonctionnant en opérationnel et comprenant des électrodes pixels arrangées matriciellement en lignes de données et lignes de sélection, une contre-électrode commune et des moyens d'affichage d'une image pilotés par un signal vidéo, et appliquant des niveaux de tension de commande sur lesdites électrodes pixels via lesdites lignes de données et de sélection et sur la contre-électrode, ledit signal vidéo, les moyens d'affichage, les lignes de sélection et de données et les électrodes pixels formant une chaîne vidéo de commande d'affichage d'une image, caractérisé en ce qu'il consiste en une vérification de l'intégrité de ladite chaîne vidéo, ladite vérification comprenant l'activation d('une chaine de mesure de courant sur au moins un bus d'alimentation desdits moyens d'affichage pour obtenir un signal représentatif des appels de courants lors de charges ou décharges capacitives des lignes de données et/ou de sélection de l'écran LCD et la comparaison de ce signal à un signal attendu (Sc) dérivé et synchrone d'un signal de balayage des lignes de sélection, pour générer un signal de détection d'un défaut d'image le cas échéant, tel qu'une chaine de mesure associée aux lignes de sélection est activée pendant des périodes d'affichages d'image vidéo, et/ou une chaine de mesure associée aux lignes de données est activée hors desdites périodes d'affichage en combinaison avec l'affichage d'une image test.The invention relates to an integrated method for detecting an image display failure in an operationally operative LCD screen comprising pixel electrodes arrayed in a row of data and selection lines, a common counter electrode, and means for displaying an image driven by a video signal, and applying control voltage levels on said pixel electrodes via said data and selection lines and on the counter electrode, said video signal, the means for display, the selection and data lines and the pixel electrodes forming a video command chain for displaying an image, characterized in that it consists of a verification of the integrity of said video channel, said verification comprising activating a current measurement chain on at least one power supply bus of said display means to obtain a signal representative of current currents when capacitance charging or discharging of the data lines and / or selection of the LCD screen and comparison of this signal with an expected signal (Sc) derived and synchronous from a selection line scanning signal, to generate a signal detecting an image defect where appropriate, such as a measurement chain associated with the selection lines is activated during periods of video image displays, and / or a The measurement string associated with the data lines is activated outside said display periods in combination with the display of a test image.

Le procédé comprend l'intégration d'une chaîne de mesure comprenant une résistance disposée en série sur le bus d'alimentation, un circuit de mesure du courant dans ladite résistance et de fourniture en sortie d'un signal numérique de mesure correspondant, et un circuit de comparaison dudit signal numérique de mesure étant prévu pour fournir le cas échéant un signal de détection de défaut d'image.The method comprises integrating a measurement chain comprising a resistor arranged in series on the power supply bus, a circuit for measuring the current in said resistor and outputting a corresponding digital measurement signal, and a comparing circuit of said digital measurement signal being provided to provide if necessary an image defect detection signal.

L'invention concerne aussi un écran à cristal liquide comprenant des moyens intégrés de détection correspondant.The invention also relates to a liquid crystal screen comprising corresponding integrated detection means.

D'autres avantages et caractéristiques de l'invention sont détaillés dans la description suivante en référence aux dessins illustrés d'un mode de réalisation de l'invention, donné à titre d'exemple non limitatif. Dans ces dessins :

  • la figure 1 illustre les circuits de commande lignes et colonnes dans un écran LCD;
  • les figures 2a et 2b sont respectivement un schéma bloc d'une chaîne de mesure utilisée dans un procédé de détection de défaut d'image selon l'invention; et un schéma d'une matrice active d'écran LCD dans lequel une telle chaîne est intégrée pour tester l'intégrité de la fonction de balayage des lignes et de la fonction d'affichage des couleurs;
  • la figure 3 détaille une séquence d'affichage d'images vidéo dans un écran LCD;
  • la figure 4 est un chronogramme des signaux des lignes de sélection, dans une fenêtre d'affichage d'une image vidéo, et du courant dans le bus d'alimentation mesuré dans cette fenêtre par une chaîne de mesure selon l'invention;
  • la figure 5 illustre un exemple de chronogramme des signaux de détection et de génération d'alarme correspondant;
  • la figure 6 donne en exemple les signaux appliqués sur les colonnes dans les fenêtres pour tester une couleur,
  • la figure 7 illustre un chronogramme des signaux de détection et de génération d'alarme correspondant; et
  • la figure 8 est un schéma détaillé d'une réalisation électronique possible d'une chaîne de mesure utilisée dans un procédé selon l'invention.
Other advantages and features of the invention are detailed in the following description with reference to the illustrated drawings of one embodiment of the invention, given by way of non-limiting example. In these drawings:
  • the figure 1 illustrates the line and column control circuits in an LCD display;
  • the Figures 2a and 2b are respectively a block diagram of a measurement chain used in an image defect detection method according to the invention; and a diagram of an active LCD screen matrix in which such a string is integrated to test the integrity of the line scan function and the color display function;
  • the figure 3 details a sequence of displaying video images in an LCD screen;
  • the figure 4 is a timing diagram of the signals of the selection lines, in a display window of a video image, and the current in the power bus measured in this window by a measurement chain according to the invention;
  • the figure 5 illustrates an exemplary timing diagram of the corresponding detection and alarm generation signals;
  • the figure 6 gives as an example the signals applied to the columns in the windows to test a color,
  • the figure 7 illustrates a timing diagram of the corresponding detection and alarm generation signals; and
  • the figure 8 is a detailed diagram of a possible electronic realization of a measurement chain used in a method according to the invention.

La figure 1 reprend une architecture d'un écran LCD. Cette architecture est bien connue. Elle comprend un réseau matriciel de pixels ou points image, constitué chacun par un dispositif de commutation et d'une cellule électro-optique dont une électrode dite électrode pixel est connectée au dispositif de commutation, et l'autre électrode dite contre-électrode CE est une électrode commune à tous les pixels. La matrice 10 comprenant les électrodes pixels et leurs dispositifs de commutation est réalisée sur une plaque substrat. La contre-électrode CE est réalisée sur une contre-plaque de l'écran qui supporte également les filtres colorés. L'affichage d'une image sur un tel écran est réalisé par des moyens d'affichage permettant l'application de niveaux de commande appropriés sur les électrodes des pixels.The figure 1 takes an architecture of an LCD screen. This architecture is well known. It comprises a matrix array of pixels or image dots, each constituted by a switching device and an electro-optical cell of which an electrode called a pixel electrode is connected to the switching device, and the other electrode referred to as the counterelectrode CE is an electrode common to all the pixels. The matrix 10 comprising the pixel electrodes and their switching devices is made on a substrate plate. The counter-electrode CE is made on a counter-plate of the screen which also supports the colored filters. The display of an image on such a screen is achieved by means of display allowing the application of appropriate control levels on the electrodes of the pixels.

S'agissant de l'électrode pixel commune, ou contre-électrode CE, elle reçoit une tension de commande VCE appropriée au mode d'adressage de l'écran, par un bus d'alimentation de tension continue respectif.With regard to the common pixel electrode, or against the CE electrode, it receives a control voltage VCE appropriate to the addressing mode of the screen, by a respective DC voltage supply bus.

S'agissant des électrodes pixels, leur adressage s'effectue par l'intermédiaire de lignes de sélection Li, i entier, i ∈[1, ...n], qui commandent chacune l'état passant ou non-passant des dispositifs de commutation arrangés sur cette ligne, et de colonnes ou lignes de données, ColRj, ColGj, ColBj, qui transmettent chacune une tension correspondant à un niveau de gris à afficher, sur l'électrode d'un pixel sélectionné, arrangé sur la colonne. Dans l'exemple, on a choisi un écran couleur, avec une matrice de filtres colorés à trois couleurs rouge R, vert G et bleu B (réalisée sur la contre plaque). On a ainsi un arrangement de colonnes correspondant à l'arrangement couleur choisi. Dans l'exemple, on a choisi un arrangement simple de type stripe avec répétition d'un motif R G B sur les colonnes, et de ligne en ligne.As regards the pixel electrodes, their addressing is carried out via selection lines L i , i integer, i ∈ [1, ... n], which each control the on or off state of the devices. switched on this line, and columns or lines of data, Col Rj , Col Gj , Col Bj , which each transmit a voltage corresponding to a gray level to be displayed, on the electrode of a selected pixel, arranged on the column. In the example, a color screen was chosen, with a matrix of color filters with three colors R red, G green and B blue (made on the backplate). There is thus an arrangement of columns corresponding to the chosen color scheme. In the example, we chose a simple arrangement of stripe type with repetition of a RGB pattern on the columns, and line in line.

Les circuits d'adressage de ces électrodes pixels comprennent un circuit de commande 20 des lignes de sélection, dénommés "driver ligne" dans la littérature technique et un circuit 30 de commande des données, dénommés " driver colonne" dans la littérature technique. Ces circuits de commande peuvent être des circuits intégrés à la matrice active (c'est à dire qu'ils sont réalisés sur la même plaque substrat que la matrice active) ou des circuits externes. Dans ce dernier cas, ils sont raccordés à la matrice active par un mode de connexion approprié, par exemple par thermocollage, report des circuits intégrés sur le verre dit report COG ("Chip On Glass") ou tout autre mode de connexion.The addressing circuits of these pixel electrodes comprise a control circuit 20 of the selection lines, called "line driver" in the technical literature and a data control circuit 30, called "column driver" in the technical literature. These control circuits may be integrated circuits to the active matrix (that is to say they are made on the same substrate plate as the active matrix) or external circuits. In the latter case, they are connected to the active matrix by an appropriate connection mode, for example by heat-sealing, transfer of the integrated circuits on the glass called COG report (" Chip On Glass ") or any other connection mode.

Le circuit 20 de commande des lignes de sélection (driver ligne) comprend principalement un registre à décalage 21 (qui peut en pratique être formé de plusieurs circuits chaînés, en fonction du nombre n de lignes de la matrice), pour adresser séquentiellement, à une fréquence de balayage verticale, chacune des lignes de grille de la matrice : le signal de balayage Sswp est appliqué en entrée du premier étage du registre et est progressivement transféré vers les étages suivants à la fréquence de balayage (fréquence ligne) définie par l'horloge de commande du driver ligne. Le circuit 20 comprend aussi un circuit élévateur de tension 22, connecté entre le registre et les lignes. Sa fonction est de transformer les niveaux basse tension en sortie du registre à décalage (logique 3 volts typiquement) en signaux analogiques, de niveaux de tension Vgon et Vgoff, appropriés à la technologie des dispositifs de commutation (transistors) des pixels. Plus spécialement, la tension Vgon est celle qui commute les transistors d'une ligne Li sélectionnée à l'état passant (fermé), ce qui permet d'appliquer la tension vidéo appliquée sur les colonnes, sur les pixels correspondant, tous les transistors des autres lignes Lk, k≠i, ayant leur grille tirée à la tension Vgoff, pour les maintenir à l'état bloqué (ouvert).The control circuit 20 for selection lines (line driver) mainly comprises a shift register 21 (which may in practice be formed of several linked circuits, depending on the number n of rows of the matrix), to address sequentially, to a vertical scanning frequency, each of the grid lines of the matrix: the scanning signal S swp is applied to the input of the first stage of the register and is progressively transferred to the following stages at the scanning frequency (line frequency) defined by the driver control clock line. The circuit 20 also comprises a voltage booster circuit 22, connected between the register and the lines. Its function is to transform the low voltage levels at the output of the shift register (typically 3 volts logic) into analog signals, voltage levels Vgon and Vgoff, suitable for the technology of switching devices (transistors) pixels. More specifically, the voltage Vgon is that which switches the transistors of a line L i selected in the on state (closed), which makes it possible to apply the video voltage applied to the columns, on the corresponding pixels, all the transistors other lines L k , k ≠ i, having their gate pulled at voltage Vgoff, to keep them in the off state (open).

Le circuit 31 de commande de données reçoit en entrée le signal vidéo Svidéo à afficher, pour appliquer les tensions sur les colonnes de la matrice correspondant aux niveaux de gris à afficher pour chaque image. Il comprend principalement un registre à décalage (qui peut en pratique être formé de plusieurs circuits ou composants chaînés, en fonction du nombre m de colonnes de la matrice), qui pilote le circuit échantillonneur bloqueur qui permet la mémorisation sur un circuit 32 inclus dans le circuit 30 du signal vidéo à afficher sur les colonnes. Chaque donnée mémorisée indique pour une colonne de la matrice, le niveau de gris à appliquer. Elle est transférée à la cadence de sélection des lignes sur un circuit 33 comprenant des convertisseurs numériques/analogiques. Typiquement, un niveau de gris est codé sur 6 ou 8 bits. Le circuit 33 comprend donc des convertisseurs numériques/analogiques et des amplificateurs de courant associés à des tables de codage pour fournir et appliquer les niveaux de tension analogique correspondants sur les colonnes, à la cadence de sélection des lignes de sélection : à chaque nouvelle ligne sélectionnée, le contenu des registres de données préalablement échantillonné, est appliqué en entrée des convertisseurs, qui fournissent chacun en sortie un niveau de tension analogique correspondant. La sortie de ces convertisseurs est connectée à un amplificateur de courant dont la fonction est de charger rapidement la colonne pendant la sélection de la ligne. Les convertisseurs numériques/analogiques ainsi que les amplificateurs de courant sont alimentés par un bus d'alimentation VDDA de tension continue (13 volts dans un exemple).The data control circuit 31 receives as input the video signal S video to be displayed, to apply the voltages on the columns of the matrix corresponding to the gray levels to be displayed for each image. It mainly comprises a shift register (which may in practice be formed of several circuits or components chained, as a function of the number m of columns of the matrix), which drives the sample-and-hold circuit which allows the memorization on a circuit 32 included in the circuit 30 of the video signal to be displayed on the columns. Each stored data indicates for a column of the matrix, the level of gray to apply. It is transferred to the rate of selection of the lines on a circuit 33 comprising digital / analog converters. Typically, a gray level is coded on 6 or 8 bits. The circuit 33 thus comprises digital / analog converters and current amplifiers associated with coding tables for supplying and applying the corresponding analog voltage levels on the columns, at the selection line selection rate: at each new selected line the contents of the previously sampled data registers are input to the converters, which each output a corresponding analog voltage level. The output of these converters is connected to a current amplifier whose function is to quickly load the column during the selection of the line. The digital-to-analog converters as well as the current amplifiers are powered by a DC voltage supply bus DDA (13 volts in one example).

Les circuits d'adressage des pixels de l'écran comprennent de manière connue d'autres dispositifs de commande, notamment pour inverser la polarité de la tension appliquée sur les pixels (inversion ligne, colonne ou point), ou pour tenir compte de la structure du filtre coloré de la matrice (structure quad, stripe...) ....The addressing circuits of the pixels of the screen comprise, in a known manner, other control devices, in particular to reverse the polarity of the voltage applied to the pixels (line, column or point inversion), or to take account of the structure the colored filter of the matrix (quad structure, stripe ...) ....

On notera que l'invention ne se limite pas à un arrangement particulier, ni à des options d'adressage qui varient selon les produits et leurs applications. L'homme du métier saura appliquer l'invention qui va être maintenant présentée en référence aux figures 2a et suivantes, à un écran spécifique donné, en mettant en application les différents enseignements qui vont être donnés ci-après.It should be noted that the invention is not limited to a particular arrangement, nor to addressing options that vary according to the products and their applications. The skilled person will apply the invention which will now be presented with reference to Figures 2a and following, to a given specific screen, applying the different lessons that will be given below.

Pour vérifier l'intégrité de la chaîne d'affichage vidéo de la matrice, et plus particulièrement pour détecter un défaut d'image, un procédé de test intégré selon l'invention mesure le courant sur les bus d'alimentation associés actifs lors de la charge des colonnes avec la tension analogique correspondant au niveau de gris souhaité sur l'image. On montre que cette mesure de courant permet de vérifier l'intégrité de toute la chaîne d'affichage vidéo.To verify the integrity of the video display chain of the matrix, and more particularly to detect an image defect, an integrated test method according to the invention measures the current on the active associated power buses during the transmission. load columns with the analog voltage corresponding to the desired gray level in the image. It is shown that this current measurement makes it possible to check the integrity of the entire video display chain.

En effet, les lignes et colonnes de la matrice sont des lignes capacitives, qui sont chargées et/ou déchargées à la fréquence ligne ou horizontale. La capacité de chaque ligne, et la capacité équivalente des colonnes sont élevées. Les colonnes ont en outre un fort couplage capacitif avec le signal VCE appliqué sur la contre-électrode. Il est ainsi possible de mesurer un appel positif ou négatif de courant correspondant à la charge ou décharge de ces lignes sur un bus d'alimentation correspondant : Vgon pour les lignes ; VDDA et/ou VCE pour les colonnes. Cet appel de courant ne peut se faire que si la tension est effectivement appliquée sur les lignes et/ou les colonnes de la matrice : c'est à dire si la ligne est bien sélectionnée et/ou si les données vidéo sont bien appliquées sur les colonnes.Indeed, the rows and columns of the matrix are capacitive lines, which are loaded and / or discharged at the line or horizontal frequency. The capacity of each line, and the equivalent capacity of the columns are high. The columns also have a strong capacitive coupling with the V CE signal applied to the counter-electrode. It is thus possible to measure a positive or negative current call corresponding to the charging or discharging of these lines on a corresponding power bus: Vgon for the lines; V DDA and / or V CE for columns. This current draw can only be done if the voltage is actually applied to the rows and / or the columns of the matrix: that is to say if the line is well selected and / or if the video data is correctly applied to the columns.

Cette mesure de courant permet ainsi de vérifier non seulement le bon fonctionnement des registres à décalage 21, ou 31, mais plus généralement des circuits amonts, qui amènent le signal d'entrée Sswp ou Svidéo, et avals qui appliquent une tension analogique sur une ligne/ou colonne correspondante : pour l'adressage des lignes, il va s'agir du circuit 22 d'élévation de tension. Pour l'adressage des colonnes il va s'agir de toute la chaîne de connectique et de mémorisation, commutation, conversion numérique analogique et amplification (circuits 32 et 33).This current measurement thus makes it possible to verify not only the correct operation of the shift registers 21, or 31, but more generally upstream circuits, which bring the input signal S swp or S video , and downstreams which apply an analog voltage to a line / or corresponding column: for the addressing of the lines, it will be the circuit 22 of voltage rise. For the addressing of columns it will be all the chain of connection and storage, switching, digital conversion and amplification (circuits 32 and 33).

La figure 2 illustre le principe d'une chaîne 40 de mesure de courant selon l'invention. Elle comprend principalement une résistance Rm associée à un circuit A de mesure de courant, qui fournit un signal de mesure Sm. La résistance Rm est connectée en série sur le bus d'alimentation VDD et un driver DRV d'une ligne capacitive LC. Ce signal est alors comparé (circuit 42) à un signal attendu Sc, typiquement un signal impulsionnel synchrone du signal de balayage des lignes, pour fournir un signal de détection de défaut Sd. Ce signal est alors typiquement traité par un dispositif de gestion d'alarme 50, généralement externe, propre à l'application utilisant l'écran concerné, pour fournir le cas échéant un signal d'alarme AL. Dans une application avionique, ce signal de détection Sd sera ainsi typiquement routé vers le système de visualisation et plus spécialement vers la partie gestion des alarmes : alarme sonore et/ou message de sécurité, par voyant lumineux....The figure 2 illustrates the principle of a current measuring chain 40 according to the invention. It mainly comprises a resistor Rm associated with a current measurement circuit A, which supplies a measurement signal Sm. The resistor Rm is connected in series on the power supply bus V DD and a DRV driver of a capacitive line LC. This signal is then compared (circuit 42) with an expected signal Sc, typically a synchronous pulse signal of the line scanning signal, to provide a fault detection signal Sd. This signal is then typically processed by an alarm management device 50, generally external, specific to the application using the screen concerned, to provide an alarm signal AL if appropriate. In an avionic application, this detection signal Sd will thus typically be routed to the display system and more particularly to the alarm management part: audible alarm and / or safety message, by indicator light.

En pratique, le circuit de mesure 40 est placé en amont des circuits 20 et 30 de commande ligne et colonne ou de contre-électrode, c'est à dire entre le bus d'alimentation "analogique" et l'entrée d'alimentation correspondante dans le circuit de commande. En effet, dans cette partie amont, on est en dehors du verre supportant la zone active de la matrice et assez généralement sur un circuit imprimé, ce qui facilite l'intégration de la chaîne de mesure.In practice, the measuring circuit 40 is placed upstream of the line and column or counter electrode control circuits 20 and 30, ie between the "analog" supply bus and the corresponding supply input. in the control circuit. Indeed, in this upstream part, it is outside the glass supporting the active area of the matrix and quite generally on a printed circuit, which facilitates the integration of the measurement chain.

La figure 2b illustre ainsi une architecture correspondante d'un écran LCD à matrice active, intégrant des chaînes de mesure selon l'invention :

  • une première chaîne de mesure 40A est placée sur le bus d'alimentation Vgon, qui alimente le circuit d'élévation de tension 22 du circuit 20 de commande des lignes. Elle comprend une résistance RmA placée en série sur le bus d'alimentation, entre le bus et l'entrée alimentation du circuit 22. Elle fournit en sortie un signal de détection correspondant SdA.
  • une deuxième chaîne de mesure 40B est placée sur le bus d'alimentation VDDA, qui alimente le circuit 33 des convertisseurs numérique analogique du circuit 30 de commande des colonnes. Elle comprend une résistance RmB placée en série sur le bus d'alimentation, entre le bus et l'entrée alimentation du circuit 33. Elle fournit en sortie un signal de détection correspondant SdB.
The figure 2b thus illustrates a corresponding architecture of an active matrix LCD screen incorporating measurement chains according to the invention:
  • a first measurement channel 40A is placed on the Vgon supply bus, which supplies the voltage rise circuit 22 of the line control circuit. It comprises a resistor RmA placed in series on the power bus, between the bus and the power input of the circuit 22. It outputs a corresponding detection signal SdA.
  • a second measurement chain 40B is placed on the VDA supply bus DDA , which feeds the circuit 33 of the digital analog converters of the column control circuit 30. It comprises a resistor RmB placed in series on the power bus, between the bus and the power input of circuit 33. It outputs a corresponding detection signal SdB.

On peut remplacer, ou compléter, la deuxième chaîne 40B de mesure par une autre chaîne de mesure 40c représentée en pointillé sur la figure, et placée sur le bus d'alimentation VCE qui alimente la contre-électrode CE. Elle comprend une résistance Rmc placée en série sur le bus d'alimentation, entre le bus et l'entrée alimentation de la contre-électrode. Elle fournit en sortie un signal de détection correspondant Sdc. On a vu en effet que les colonnes ont un fort couplage capacitif avec la contre-électrode. La mesure de courant pour les colonnes peut ainsi se faire sur l'un et/ou l'autre bus VDDA et/ou VCE.The second measurement chain 40B can be replaced or completed by another measurement chain 40c shown in dashed lines in the figure, and placed on the supply bus VCE which supplies the counter-electrode CE. It comprises a resistor Rmc placed in series on the power bus, between the bus and the feed input of the counter-electrode. It outputs a corresponding detection signal Sdc. It has been seen that the columns have a strong capacitive coupling with the counter-electrode. The current measurement for the columns can thus be done on one and / or the other bus VDDA and / or VCE.

La mise en oeuvre d'un procédé de détection de défaut d'image selon l'invention, peut, comme représenté sur la figure 2b, comprendre une chaîne de mesure pour les lignes et une chaîne de mesure pour les colonnes. C'est la configuration optimale de détection des défauts qui conduisent au problème d'image figée. Cependant, selon les besoins de l'application visée, on peut se contenter d'une seule chaîne, soit associée aux lignes, soit associée aux colonnes.The implementation of an image defect detecting method according to the invention can, as shown in FIG. figure 2b , include a measurement string for the rows and a measurement string for the columns. This is the optimal configuration for detecting faults that lead to the problem of frozen image. However, depending on the needs of the intended application, one can be satisfied with a single string, either associated with the lines, or associated with the columns.

Selon que l'on teste la charge des lignes ou des colonnes, la mise en oeuvre du procédé de détection diffère. On rappelle que l'affichage d'une image sur un écran LCD est séquencé par image, à une période trame T, comprenant une période d'affichage VW de l'image pendant laquelle les lignes de sélection sont sélectionnées une à une en séquence, et les données vidéo correspondantes appliquées sur les colonnes, et une période hors affichage NVW, pendant laquelle aucune ligne n'est sélectionnée. Une telle séquence est illustrée en exemple sur la figure 3. Pour un affichage vidéo à 50 Hz, on a une période trame T de 20ms dont environ 16ms sont utilisés pour l'affichage effectif d'image, dans la période d'affichage VW.Depending on whether the load of the rows or columns is tested, the implementation of the detection method differs. It is recalled that the display of an image on an LCD screen is sequenced by image, at a frame period T, comprising a display period VW of the image during which the selection lines are selected one by one in sequence, and the corresponding video data applied to the columns, and a non-display period NVW, during which no line is selected. Such a sequence is illustrated as an example on the figure 3 . For a 50 Hz video display, there is a frame period T of 20 ms of which about 16 ms are used for the effective image display, in the display period VW.

S'agissant des lignes, la chaîne de mesure 40A associée aux lignes doit donc être activée dans la période d'affichage VW dans laquelle les lignes sont effectivement sélectionnées : en dehors de cette période, c'est à dire dans les périodes NVW, aucune ligne n'est sélectionnée ; par conséquent il est normal de ne pas détecter d'appel de courant sur l'alimentation Vgon. Par contre, s'agissant des colonnes, pendant la période d'affichage VW, il n'est pas possible ni de faire une mesure significative de courant, car les différents niveaux de tension correspondant aux différents niveaux de gris à afficher pour une image donnée peuvent plus ou moins se compenser en charge/décharge suivant la nature de l'image à afficher. En outre, il n'est pas possible de tester l'affichage d'une couleur spécifiquement sans perturber l'image. On prévoit donc d'activer la chaîne de mesure 40B et/ou 40c associée aux colonnes, dans les périodes "hors affichage" NWM.As regards the lines, the measurement chain 40A associated with the lines must therefore be activated in the display period VW in which the lines are actually selected: outside this period, that is to say in the NVW periods, no line is selected; by therefore it is normal not to detect a current draw on the Vgon power supply. As against the columns, during the VW display period, it is not possible to make a significant measurement of current, because the different voltage levels corresponding to the different gray levels to display for a given image can more or less compensate for charge / discharge depending on the nature of the image to display. In addition, it is not possible to test the display of a color specifically without disturbing the image. It is therefore planned to activate the measurement chain 40B and / or 40c associated with the columns, in the "off-display" periods NWM.

Les figures 4 et 5 illustrent ainsi plus particulièrement le procédé de test du circuit de commande des lignes de sélection. Ce procédé intègre la chaîne de mesure 40A précédemment décrite (figure 2b). Dans la période WM, les lignes sont sélectionnées une par une en séquence, comme illustré sur la figure 4 : une impulsion de tension Vgon est appliquée sur chaque ligne, à la fréquence de balayage vertical. Dans les périodes hors affichage NWM, les lignes sont toutes à Vgoff.The Figures 4 and 5 thus illustrate more particularly the method of testing the control circuit of the selection lines. This method integrates the measurement chain 40A previously described ( figure 2b ). In the WM period, the lines are selected one by one in sequence, as illustrated on the figure 4 : a voltage pulse Vgon is applied on each line, at the vertical scanning frequency. In off-display NWM periods, the lines are all Vgoff.

Pour chaque impulsion de tension, la chaîne de mesure 40A va pouvoir mesurer un courant correspondant à l'appel de courant provoqué par la charge de la ligne de sélection correspondante. Ces appels de courant I sur le bus d'alimentation Vgon en correspondance avec chaque impulsion Vgon sont illustrés sur la figure 4.For each voltage pulse, the measurement chain 40A will be able to measure a current corresponding to the current draw caused by the load of the corresponding selection line. These current I calls on the Vgon power bus in correspondence with each Vgon pulse are illustrated on the figure 4 .

Ainsi, le circuit de mesure de courant 41 de la chaîne est conçu pour fournir en sortie un signal de mesure Sm impulsionnel, chaque impulsion correspondant à la détection d'un appel de courant.Thus, the current measuring circuit 41 of the chain is designed to output a measurement pulse signal Sm, each pulse corresponding to the detection of a current draw.

Ce signal est comparé à un signal Sc de fréquence ligne, typiquement dérivé d'un signal d'horloge synchrone du signal de balayage Sswp. Dans l'exemple, ce signal est "plat" dans les fenêtres hors affichage NVW. Ce circuit de comparaison peut être typiquement réalisé au moyen d'un circuit logique type porte NAND. Quand il n'y a pas d'impulsion dans le signal de mesure, ce circuit de comparaison fournit une impulsion de tension logique en sortie : c'est le signal de détection Sd.This signal is compared to a line frequency signal Sc, typically derived from a synchronous clock signal of sweep signal S swp . In the example, this signal is "flat" in windows off NVW display. This comparison circuit can be typically realized by means of a NAND gate type logic circuit. When there is no pulse in the measurement signal, this comparison circuit provides a logic voltage pulse output: it is the detection signal Sd.

Ce signal est traité par un dispositif de gestion d'alarme (dispositif 50 - figure 2a). Ce dispositif de gestion peut mettre en oeuvre des règles de génération d'un signal d'alarme ALA correspondant. Par exemple, une règle peut édicter un nombre de défauts (d'impulsions de défaut Sd) minimum pour générer une alarme. Dans l'exemple illustré sur la figure 5 à titre illustratif du procédé de mesure, une suite de quatre défauts est nécessaire pour générer une alarme, qui est alors traitée de manière appropriée par un système de sécurité de l'application concernée. On note que les alarmes éventuelles sont générées pendant les périodes de mesure/détection, c'est à dire dans les périodes VW.This signal is processed by an alarm management device (device 50 - figure 2a ). This management device can implement rules for generating a corresponding ALA alarm signal. For example, a rule can set a minimum number of (default Sd fault) faults for generate an alarm. In the example shown on the figure 5 As an illustration of the measurement method, a sequence of four faults is required to generate an alarm, which is then appropriately processed by a security system of the application concerned. It should be noted that any alarms are generated during the measurement / detection periods, that is to say in the VW periods.

Dans un exemple pratique, une résistance RmA de faible impédance suffit, de l'ordre de 10 ohms par exemple. Pour un écran 10 pouces, et pour une capacité équivalente d'une ligne de sélection de l'ordre de 200 picofarads, chargée en 0.5µs à Vgon égal à 30 Volts, on obtient un courant pic de charge I(Vgon) de l'ordre de 12mA.In a practical example, a resistor RmA of low impedance is sufficient, of the order of 10 ohms for example. For a 10-inch screen, and for an equivalent capacity of a selection line of the order of 200 picofarads, loaded in 0.5μs at Vgon equal to 30 Volts, a peak charge current I (Vgon) of the order of 12mA.

Les figures 6 et 7 illustrent plus particulièrement le procédé de test du circuit 30 de commande des colonnes. Ce procédé intègre la chaîne de mesure 40B et/ou la chaîne de mesure 40c précédemment décrites (figure 2b), le principe de détection s'appliquant à l'identique sur ces deux chaînes.The Figures 6 and 7 illustrate more particularly the method of testing the column control circuit. This method integrates the measurement chain 40B and / or the measurement chain 40c previously described ( figure 2b ), the detection principle applying identically on these two chains.

Ce principe de détection consiste à commander l'affichage d'une image test Stest dans les périodes NWM hors affichage : cette image test est déterminée, programmée, pour commander sur des colonnes de la matrice un même premier niveau de gris, ou un même deuxième niveau de gris, alternativement à la fréquence ligne (c'est à dire à la fréquence de sélection des lignes, sauf que les lignes ne sont pas sélectionnées). Les premier et deuxième niveaux de gris correspondent respectivement au niveau le plus bas et le plus haut de l'échelle de gris, c'est à dire à l'excursion maximum de tension. Pendant dans la période NWM d'une trame, toutes ces colonnes sont alors alternativement portées au maximum de tension, et au minimum de tension, à la fréquence ligne. Cette modification importante du signal de colonne à la fréquence ligne crée un appel de courant important dans les bus d'alimentation VDDA et VCE, ce qui est détecté.This detection principle consists in controlling the display of a test image S test in the non-display NWM periods: this test image is determined, programmed, to control on the columns of the matrix the same first level of gray, or the same second level of gray, alternatively to the line frequency (ie the frequency of selection of the lines, except that the lines are not selected). The first and second gray levels correspond respectively to the lowest and the highest level of the gray scale, ie to the maximum voltage excursion. During the period NWM of a frame, all these columns are then alternately brought to the maximum voltage, and the minimum voltage, to the line frequency. This significant modification of the line-frequency column signal creates a large current draw on the VDDA and VCE power buses, which is detected.

En pratique, la mise en oeuvre du procédé entraîne ainsi le fonctionnement du driver colonne 30 pendant toute la trame, dans la période VW, pour afficher une image vidéo Svidéo, et dans la période NVW pour fictivement afficher une image test Stest. L'affichage est "fictifs' car dans ces périodes NVW, les lignes ne sont pas sélectionnées : l'image de test n'est pas réellement affichée sur l'écran.In practice, the implementation of the method thus causes the column driver 30 to operate during the entire frame, in the period VW, to display a video image S video , and in the period NVW to fictitiously display a test image S test . The display is "fictitious" because in these NVW periods, the lines are not selected: the test image is not actually displayed on the screen.

La séquence de test alternative maxima/minima est intéressante car elle permet de tester la commande des niveaux de gris aux deux extrémités de la chaîne.The alternative test sequence maxima / minima is interesting because it allows to test the control of gray levels at both ends of the chain.

Cependant, la séquence de test pourrait ne prévoir l'affichage que d'un niveau de gris prédéfini, le même d'une ligne à l'autre. C'est de préférence le niveau de gris le plus haut ou le plus bas de l'échelle de gris, pour provoquer un appel de courant de charge ou décharge suffisant.However, the test sequence may only require the display of a predefined gray level, the same from one line to another. It is preferably the highest or lowest gray level of the greyscale, to cause a sufficient charging or discharging current draw.

Pour un écran utilisant un mode d'adressage du type à inversion colonne au moins, l'image de test vidéo correspondra à un affichage une colonne sur deux.For a display using at least one column reversal addressing mode, the video test image will be one in two column views.

Si on considère un écran couleur, il est intéressant de pouvoir tester l'affichage d'une couleur spécifique. Selon l'invention, des colonnes pour afficher l'image de test sont sélectionnées pour correspondre à une unique couleur, les colonnes associées à l'autre ou aux autres couleurs étant non sélectionnées. Typiquement, et comme illustré sur la figure 6, si on veut tester le rouge, les données à afficher concernent les seules colonnes rouges ColRj. Les autres colonnes ColGj, Col8j, restent à un niveau de tension stable pendant ces périodes NVW de façon à réduire leur contribution aux appels de courants. Par exemple, l'image de test est telle que les colonnes rouges commutent à la fréquence ligne alternativement du niveau noir au niveau blanc, pour avoir le maximum de l'excursion de tension, et les autres colonnes gardant un niveau de gris stable, par exemple le blanc. On peut prévoir des séquences de test successives, pour tester successivement chacune des couleurs, à des fréquences de test qui peuvent être choisies selon l'importance de chaque couleur pour l'application considérée.If we consider a color screen, it is interesting to be able to test the display of a specific color. According to the invention, columns for displaying the test image are selected to correspond to a single color, the columns associated with the other one or the other colors being unselected. Typically, and as illustrated on the figure 6 , if we want to test the red, the data to be displayed concern the only red columns Col Rj . The other columns Col Gj , Col 8j , remain at a stable voltage level during these periods NVW so as to reduce their contribution to current calls. For example, the test image is such that the red columns switch at the line frequency alternately from the black level to the white level, to have the maximum of the voltage swing, and the other columns keep a stable gray level, for example. example white. Successive test sequences can be provided for successively testing each of the colors at test frequencies which can be chosen according to the importance of each color for the application in question.

La figure 7 illustre le procédé de détection avec les signaux Sm, Sd et ALB, qui est similaire à celui du driver ligne (Figure 5). Le signal de comparaison Sc utilisé est également similaire.The figure 7 illustrates the detection method with signals Sm, Sd and ALB, which is similar to that of the line driver ( Figure 5 ). The comparison signal Sc used is also similar.

La séquence de test du driver colonne 30 peut par ailleurs dépendre du mode d'adressage de l'écran qui est testé.The test sequence of the column driver 30 may also depend on the addressing mode of the screen that is tested.

Dans un écran utilisant un mode d'adressage du type à inversion colonne au moins, et pour un arrangement des couleurs sur la matrice de type stripe, typiquement une répétition en ligne d'un motif rouge R, vert V, bleu B, deux colonnes rouges successives sont l'une commandée avec une polarité de tension positive, et l'autre une polarité de tension négative. Dans ce cas on comprend que l'on a une compensation de charge et décharge de courant : on ne détectera pas d'appel de courant sur le bus VIDA. Dans ce cas la séquence de test utilisera une image de test vidéo programmée pour correspondre à un affichage de la couleur rouge une colonne sur deux. Cela se décline bien sûr sur chaque couleur.In a screen using an addressing mode of the at least one column inversion type, and for a color scheme on the stripe type array, typically an online repeat of a red pattern R, green V, blue B, two columns successive reds are one controlled with a positive voltage polarity, and the other a negative voltage polarity. In this case it is understood that there is a load compensation and current discharge: it will not detect current draw on the VIDA bus. In this case the test sequence will use a video test image programmed to match a red color display every other column. This of course comes down to each color.

De façon générale, l'affichage d'une image de test selon l'invention se traduit par une modification à la fréquence ligne du signal de colonne sur des colonnes sélectionnées pour le test, pour créer un appel de courant important correspondant dans les bus d'alimentation VDDA et VCE, avec éventuellement d'autres colonnes dans un état approprié réduisant leur contribution aux appels de courant.In general, the display of a test image according to the invention results in a modification to the line frequency of the column signal on columns selected for the test, to create a corresponding large current draw in the bus. VDDA and VCE supply, possibly with other columns in an appropriate state reducing their contribution to current calls.

Enfin, on connaît des écrans dans lequel le bus d'alimentation VDDA est coupé périodiquement, à la fréquence trame (non représenté). Dans ce cas, on prévoit que la mesure de courant est désactivée pendant ces coupures, pour ne pas générer de fausses détections de défaut.Finally, screens are known in which the VDDA power bus is cut off periodically, at the frame rate (not shown). In this case, it is expected that the current measurement is deactivated during these interruptions, so as not to generate false fault detections.

Ces différentes variantes de mise en oeuvre de l'invention ne posent pas de problèmes particuliers de réalisation pratique.These different variants of implementation of the invention do not pose particular problems of practical realization.

En pratique, la chaîne de mesure 40B et/ou 40c est associée à des moyens de mémorisation/génération d'au moins une image de test Stest. Si on veut tester chacune des couleurs, la même image peut être utilisée, à chaque fois, en combinaison avec une sélection des colonnes de la couleur correspondante. Ces moyens de mémorisation/génération sont réalisés de toute manière connue de l'homme de l'art.In practice, the measurement chain 40B and / or 40c is associated with means for storing / generating at least one test S test image . If one wants to test each of the colors, the same image can be used, each time, in combination with a selection of columns of the corresponding color. These storage / generation means are made in any manner known to those skilled in the art.

Pour des grands écrans, le circuit de commande des colonnes ou driver colonne est en pratique formé d'une pluralité de composants chaînés, chacun commandant un groupe de colonnes.For large screens, the column driver or column driver circuit is in practice formed of a plurality of chained components, each controlling a group of columns.

Dans un perfectionnement, la chaîne de mesure pour les colonnes 40B et/ou 40c permet de tester séparément un composant du driver colonne, pour détecter un éventuel défaut. Un procédé de test correspondant comprend alors une commande d'affichage d'une image de test, correspondant à une sélection des colonnes de ce composant particulier du driver colonne. On peut ainsi tester chacun des composants du circuit de commande des colonnes, avec une séquence d'images de test, chaque image définie pour un composant déterminé du driver en utilisant le procédé de test précédemment décrit en relation avec les figures 6 et 7.In an improvement, the measurement chain for the columns 40B and / or 40c makes it possible to separately test a component of the column driver, to detect a possible fault. A corresponding test method then comprises a command for displaying a test image, corresponding to a selection of the columns of this particular component of the column driver. It is thus possible to test each of the components of the column control circuit, with a sequence of test images, each image defined for a specific component of the driver by using the test method previously described in relation to the Figures 6 and 7 .

La figure 8 donne un exemple pratique d'une chaîne de mesure qui peut être utilisée dans l'invention. La résistance Rm est insérée en série dans l'alimentation VDD du driver testé. Un amplificateur différentiel 1, par exemple un amplificateur ANALOG DEVICE AD817, permet de rejeter les parasites de l'alimentation. L'amplificateur est choisi avec une bande passante assez étroite (réseau de Wien) pour améliorer le rapport S/B de la sortie Out de l'amplificateur. Un comparateur 2 dont le seuil peut être réglé en fonction de l'écran LCD et de l'application transforme le signal analogique Out en un signal numérique Sm. La présence et la durée des impulsions en sortie du comparateur 2 dépendent des appels de courant dans la résistance de mesure Rm.The figure 8 gives a practical example of a measurement chain that can be used in the invention. The resistor Rm is inserted in series into the VDD power supply of the tested driver. A differential amplifier 1, for example an ANALOG DEVICE AD817 amplifier, makes it possible to reject the parasites of the power supply. The amplifier is chosen with a fairly narrow bandwidth (Wien network) to improve the S / B ratio of the output Out of the amplifier. A comparator 2 whose threshold can be set according to the LCD screen and the application converts the analog signal Out into a digital signal Sm. The presence and the duration of the pulses at the output of the comparator 2 depend on current calls in the measuring resistor Rm.

Le procédé de détection de défaut d'image qui vient d'être décrit peut être intégré simplement dans tout écran à cristal liquide dont il contribue à garantir l'intégrité.The image defect detection method which has just been described can be integrated simply into any liquid crystal screen which it contributes to guarantee the integrity.

Claims (15)

  1. Integrated method for the detection of a display defect of an image in an LCD screen operating in operational mode, the screen comprising pixel electrodes arranged in a matrix-like manner in data lines (ColRj) and selection lines (Li), a common counter-electrode (CE) and image display means (20, 30, CE) piloted by a video signal, and applying control voltage levels to the pixel electrodes via the data and selection lines and to the counter-electrode (CE), the video signal, the display means, the selection and data lines and the pixel electrodes forming an image display control video chain, characterized in that it involves a verification of the integrity of the video chain, the verification comprising the activation of a current measurement chain on at least one power supply bus of the display means (20, 30, CE) in order to obtain at the output a signal which is representative of the current surges during capacitive charges or discharges of the data and/or selection lines of the LCD screen and the comparison of this signal with an anticipated signal (Sc) which is derived from and synchronous with a scanning signal (Sswp) of the selection lines, in order to generate a detection signal of an image defect (Sd) where applicable, so that a measurement chain which is associated with the selection lines (40A) is activated during the periods of video image display (NW), and/or a measurement chain which is associated with the data lines (40B, 40C) is activated outside the display periods in combination with the display of a test image.
  2. Method according to claim 1, characterised in that it uses a measurement chain (40) which comprises a measuring resistor (Rm) which is arranged in series on the power supply bus (VDD), a circuit (41) for measuring current in the resistor and for providing at the output a corresponding pulsed digital measurement signal (Sm).
  3. Method according to claim 1 or 2, characterised in that it is applied to a power supply bus (Vgon) of the control circuit (20) of the selection lines of rows of image elements of the screen, and in that it is activated at each new display window for a video image (VW), and deactivated or inhibited between two display windows.
  4. Method according to either claim 1 or 2, characterised in that it is applied to a power supply bus (VDDA) of the control circuit of the data lines associated with the image elements of the screen, and/or to a power supply bus of the counter-electrode (VCE), and in that it is activated in a period (NVW) between two display windows for a video image and deactivated during each display window for a video image (VW).
  5. Method according to claim 3 or 4, wherein the digital measurement signal (Sm) is compared with a pulsed periodic signal (Sc) of a frequency being the selection frequency of the selection lines.
  6. Method according to claim 4, comprising the use of a video test image (Stest) during the activation periods (NVW), the video image being programmed to control the same grey level on columns so as to generate a corresponding current surge in the power supply bus (VDDA, VCE).
  7. Method according to claim 6, the video image being programmed to control a same first grey level or a same second grey level on columns, alternatively, at the line frequency, the first and second grey levels corresponding to the lowest and the highest level of the grey scale, respectively.
  8. Method according to claim 6 or 7, for a screen using an addressing mode at least of the column inversion type, in which the video test image corresponds to a display involving one column out of two.
  9. Method according to any one of claims 6 to 8, for a colour screen, in which the selected columns for displaying the test image correspond to a unique colour.
  10. Method according to claim 9, characterised in that it is applied successively in order to test each colour.
  11. Method according to any one of claims 6 to 8, the column control circuit (30) comprising a plurality of elementary components, each controlling a given group of columns, characterized in that the video image corresponds to a display on columns of a particular component in order to detect a potential defect of the component.
  12. Method according to claim 11, characterised in that it comprises the use of a video image sequence, comprising an image for each of the components of the control circuit.
  13. Method according to any one of the preceding claims, for a screen in which the power supply provided by the bus is cut off periodically, characterized in that the method is deactivated during the cutoffs.
  14. LCD screen comprising pixel electrodes arranged in a matrix-like manner in data lines (ColRj) and selection lines (Li), a common counter-electrode (CE) and image display means (20, 30, CE) piloted by a video signal, and applying control voltage levels to the pixel electrodes via the data and selection lines and to the counter-electrode (CE), the video signal, the display means, the selection and data lines and the pixel electrodes forming an image display control video chain, characterized in that it comprises an integrated circuit for detecting a display defect of an image comprising
    - a current measurement chain (40) on at least one of the voltage supply buses of the display means (20, 30, CE) during capacitive charges or discharges of the data and/or selection lines of the LCD screen, the measurement chain providing at the output a signal which is representative of the current surges on the bus, and a circuit for comparing this representative signal with an anticipated signal (Sc) which is derived from and synchronous with a scanning signal (Sswp) of the selection lines, in order to generate a detection signal (Sd) of a corresponding image defect, indicating whether or not the video chain is integrated,
    - means for activating the measurement chain in order to activate a measurement chain (40A) which is associated with the selection lines during video image display periods (NW), and/or in order to activate a measurement chain (40B, 40C) which is associated with the data lines outside the display periods in combination with a display of a test image.
  15. Screen according to claim 14, characterised in that the measurement chain (40) comprises a measurement resistor (Rm) which is arranged in series between a supply bus (VDD) and a control circuit (DRV), a circuit (41) for measuring the current in the resistor and for supplying at the output a corresponding digital measurement signal (Sm), a comparison circuit (42) of the digital measurement signal being provided in order to supply where applicable the image defect detection signal (Sd).
EP08786848.5A 2007-08-07 2008-08-04 Integrated method of detecting an image defect in a liquid crystal screen Active EP2174315B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0705753A FR2919949B1 (en) 2007-08-07 2007-08-07 INTEGRATED METHOD FOR DETECTING AN IMAGE FAULT IN A LIQUID CRYSTAL DISPLAY
PCT/EP2008/060235 WO2009019253A1 (en) 2007-08-07 2008-08-04 Integrated method of detecting an image defect in a liquid crystal screen

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EP2174315A1 EP2174315A1 (en) 2010-04-14
EP2174315B1 true EP2174315B1 (en) 2017-10-04

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WO (1) WO2009019253A1 (en)

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JP2010536059A (en) 2010-11-25
JP2013178524A (en) 2013-09-09
JP2013167887A (en) 2013-08-29
US20110074664A1 (en) 2011-03-31
EP2174315A1 (en) 2010-04-14
JP5994711B2 (en) 2016-09-21
WO2009019253A1 (en) 2009-02-12
FR2919949B1 (en) 2010-09-17
KR101587291B1 (en) 2016-01-20
KR20100042278A (en) 2010-04-23
US8508524B2 (en) 2013-08-13
JP5821086B2 (en) 2015-11-24
FR2919949A1 (en) 2009-02-13

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