JP2005098901A - Tft array inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inspect abnormality in a shift register, in a TFT array inspection device for inspecting TFT arrays successively driven by the shift register. <P>SOLUTION: This TFT array inspection device 1 for inspecting the TFT arrays driven, in the order by the shift register is provided with an array driving part 2 for outputting a start signal to the shift register, and a shift register output detecting part 3 for detecting the output signal from the shift register, and inspects the drive abnormality in the shift register of the TFT array. The inspection device 1 inputs the start signal from the array drive part 2 into the shift register, and the shift register outputs the output signals in the order, from each bit to the each TFT array, based on the the start signal. The shift register output detecting part 3 determines the abnormality in the shift register, by detecting the output signal output from the shift register. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a TFT array inspection apparatus used for inspecting a TFT array substrate used in a liquid crystal display, an organic EL display, or the like.

  A liquid crystal device such as a liquid crystal display or an organic EL display, or an organic EL device is provided with a TFT (thin film transistor) array for providing a liquid crystal or an organic EL on a substrate and driving them.

  The TFT array includes a plurality of pixel electrodes arranged in a matrix and a counter electrode arranged to face these pixel electrodes, and a liquid crystal device or an organic EL device is provided with a liquid crystal or an organic EL interposed between the electrodes. Is configured. In the case of a liquid crystal device, the liquid crystal is voltage-driven, and in the case of an organic EL, the organic EL is current-driven. As a method of driving the TFT array, a method of sequentially driving the TFT array using a shift register is known.

  The inspection of the TFT array is usually performed electrically or optically by driving the TFT array with an inspection signal. Optical inspection is performed by visually observing the display state of liquid crystal or organic EL.

For example, Patent Document 1 is known as an inspection apparatus for inspecting a shift register-driven TFT array.
JP 2000-352706 A

  The conventional TFT array inspection apparatus inspects each pixel, and there is a problem that it is impossible to determine abnormality of a shift register that sequentially drives the TFT array. Further, when the display state by liquid crystal or organic EL is observed visually, there is a problem that it is impossible to distinguish whether the cause of the display state abnormality is in the TFT array or in the shift register that drives the TFT array. is there.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above problems and to inspect a shift register for an abnormality in a TFT array inspection apparatus for inspecting a TFT array sequentially driven by a shift register.

  In the present invention, an abnormality of a shift register is detected by observing the output of the shift register that drives the TFT array.

  The TFT array inspection apparatus of the present invention is a TFT array inspection apparatus that inspects a TFT array that is sequentially driven by a shift register, and detects an output signal from the shift register and an array drive unit that outputs a start signal to the shift register. And a shift register output detection unit for detecting an abnormality in driving of the shift register of the TFT array based on the presence / absence and timing of an output signal from the shift register.

  When the TFT array is sequentially driven by the shift register, the timing of the signal applied to the TFT array is controlled by the output signal of each bit of a plurality of shift registers connected in series.

  The inspection apparatus of the present invention inputs a start signal from the array driving unit to the shift register. Based on this start signal, the shift register sequentially outputs an output signal from each bit to each TFT array. The shift register output detection unit determines an abnormality of the shift register by detecting an output signal output from the shift register.

  The shift register output detection unit detects an output signal of an end bit of the shift register as one detection form. For example, if an end bit output signal is detected, it can be known that the shift register is normal. If an end bit output signal is not detected, one of the shift registers is faulty. Can know.

  The shift register output detection unit detects output signals of intermediate bits and end bits of the shift register as another detection form. For example, when an intermediate bit output signal is detected, it is determined that at least the first shift register to the shift register from which the output signal is detected is normal, and an intermediate bit output signal is not detected. In this case, it is possible to know that there is a failure in at least one of the shift registers from the first shift register to the shift register from which the output signal is detected.

  The array drive unit outputs a start signal only to the first bit and drives the shift register in order from the first bit, and selectively outputs a start signal to the shift register of the first bit and the shift register of the intermediate bit, Driving is performed sequentially from the shift register of the first bit or the shift register of the intermediate bit.

  By driving sequentially from the intermediate bit shift register, it is possible to limit the inspection range of the shift register and narrow the failure range.

  According to the TFT array inspection apparatus of the present invention, a shift register abnormality can be inspected.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram for explaining an outline of a TFT array inspection apparatus according to the present invention.

  In manufacturing the TFT array 4 used in a liquid crystal device such as a liquid crystal display or an organic EL display or an organic EL device, a plurality of substrates 5 on which the TFT array 4 is formed are formed on the panel 8 and then divided into the respective substrates 5. The TFT array 4 is driven by, for example, a signal line driving circuit 6 and a scanning line driving circuit 7. As one driving method of this driving circuit, one using a shift register is known, and a liquid crystal or an organic EL is driven by driving each TFT array based on signals sequentially output from each bit of the shift register. The TFT array 4 is inspected before a liquid crystal or organic EL element is provided on the substrate 5.

  The TFT array inspection apparatus 1 of the present invention has a function of inspecting a shift register constituting a drive circuit in a drive circuit such as a signal line drive circuit 6 or a scanning line drive circuit 7. The TFT array inspection apparatus 1 can also have a function of inspecting the TFT array itself in addition to the inspection of the shift register.

  The TFT array inspection apparatus 1 of the present invention includes an array drive unit 2 that drives a drive circuit of each TFT array 4 and a shift register output detection unit 3 that detects an output from a shift register of the drive circuit. FIG. 1 (a) shows one TFT array 4, but a plurality of TFT arrays 4 are usually formed on the panel 8 as shown in FIG. 1 (b). The inspection apparatus 1 can inspect the plurality of TFT arrays 4.

  The TFT array inspection apparatus 1 of the present invention performs inspection by forming the output of the shift register that drives the TFT array, and the detected shift register output can take various forms. The configuration of the shift register inspected by the TFT array inspection apparatus 1 of the present invention is not limited to a specific configuration, and can be applied to any configuration.

  Hereinafter, the form of a plurality of shift register outputs will be described using a configuration example of two shift registers. 2 to 10 are configuration examples of the first shift register, and FIGS. 11 to 14 are configuration examples of the second shift register.

  The shift register shown in FIGS. 2, 4, 6, and 9 has a plurality of shift registers SR1 to SRn each having an input terminal IN, an output terminal OUT, and a signal terminal A connected in series, and a start signal ( YST) is used as the first bit, the shift register SRn that outputs the final signal (Yend) is used as the end bit, and the check signal (YC1,. YC2) is input alternately. From each output terminal OUT, signals (Y1 to Yn-1) are output to the input terminal IN of the next shift register and the TFT array 4 in accordance with the output timing of the shift register. The final signal (Yend) is output from the end bit shift register SRn.

  Here, in the TFT array inspection apparatus 1 of the present invention, the array drive circuit 2 outputs these inspection signals (YC1, YC2) and the start signal (YST) to the drive circuit.

  In the first embodiment shown in FIGS. 2 and 3, the shift register output detector 3 detects the final signal (Yend) output from the end bit shift register SRn, and the TFT array based on the final signal (Yend). 4 shift register is inspected. Here, the signal detected by the shift register output detector 3 is represented by a signal (Send).

  FIG. 3 is a diagram for explaining the timing of each signal in the first embodiment. 3, (a) and (b) represent inspection signals (YC1) and (YC2), (c) represents a start signal (YST), (d) to (f),. Each of the shift registers represents a signal (Y1 to Yn-1) output to the TFT array, (i) represents a final signal (Yend) from the end bit shift register SRn, and (j) represents a shift register output detection unit. 3 represents a detection signal (Send) to be detected.

  If at least one of the shift registers SR1 to SRn is defective, the signal (Y1 to Yn-1) is not signaled or the timing of the signal is shifted, and the end bit is shifted. The final signal (Yend) of the register 1SRn is not output or the timing of the signal is shifted.

  The shift register output detection unit 3 detects this final signal (Yend), detects the presence or absence of the detection signal (Send), and the timing difference between the detected detection signal (Send) and the normal signal, thereby detecting the shift register. Inspect for defects.

  For example, when the detection signal (Send) is not detected, it is expected that at least one of the shift registers SR1 to SRn has a defect such as disconnection, and when the timing of the detection signal (Send) is shifted, Defects such as short circuit and capacitive coupling are expected.

  In the second embodiment shown in FIGS. 4 and 5, the shift register output detection unit 3 includes an intermediate bit shift register (SR 2, FIG. 4) in addition to the final signal (Yend) output from the end bit shift register SRn. .., SRn-2) output signals (Y2,..., Yn-2) output from the output terminal OUT are detected, and based on the output signals (Y2,..., Yn-2) and the final signal (Yend). The shift register of the TFT array 4 is inspected. Here, the intermediate bit output signal input by the shift register output detector 3 is represented by signals (S2,..., Sn-2).

  FIG. 5 is a diagram for explaining the timing of each signal in the second mode shown in FIG. 5, (a) to (i) are the same as the signals shown in FIG. 3, (j) to (l) represent detection signals detected by the shift register output detection unit 3, and (j), (k ) Represents detection signals (S2,..., Sn-) obtained by detecting the output signals (Y2,..., Yn-2) of the output terminals OUT of the intermediate bit shift registers (SR2,. 2) and (l) represents a detection signal (Send) obtained by detecting the final signal (Yend).

  Here, for example, regarding the detection signal (S2), if any of the shift registers SR1 and SR2 ahead of the output terminal of the shift register SR2 is defective, the detection signal (S2) is not signaled, or There is a shift in the timing of the signal. Similarly, if any of the shift registers SR1 to SRn-2 ahead of the output terminal of the shift register SRn-2 is defective, the detection signal (Sn-2) is not signaled or the signal Deviation in timing occurs. Looking at the detection signal (Send) of the final signal (Yend), if any of the shift registers SR1 to SRn is defective, the detection signal (Send) is not output or the timing of the signal is shifted.

  If there is a defect in the intermediate shift register, no abnormality is detected in the detection signal detected at the signal terminal in front of the shift register, and detection is detected at the signal terminal behind the shift register. An abnormality is detected in the signal.

  The shift register output detection unit 3 detects the output signal final signal (Yend) of the intermediate bit shift register, and detects the presence or absence of the signal and the deviation from the timing of the normal signal. And a shift register having a defect can be identified. Note that the shift register that can detect a defect is determined by the installation interval of the signal terminals of the detection signal, and the defect can be detected in units of the shift register sandwiched between the signal terminals of the detection signal.

  In the third embodiment shown in FIGS. 6, 7, and 8, the output signals (Y2,..., Yn-2, Yend) output from the output terminals OUT of the end bit and intermediate bit shift registers in the second embodiment are used. Based on the detected output signal (Y2,..., Yn-2) and the final signal (Yend), the shift register of the TFT array 4 is inspected and the shift register is started at the output terminal OUT of the intermediate bit shift register. Signals (YST2 to YSTn-2) are input. With this configuration, the shift register from the first bit to the predetermined bit can be inactivated, and driving can be started from the intermediate shift register behind the shift register for inspection.

  FIG. 7 is a diagram for explaining the timing of each signal in the third mode shown in FIG. 7, (a) to (l) are the same as the signals shown in FIG. 5 and show the signal states when the shift register is driven from the first bit.

  On the other hand, (m) to (l) show signal states when the start signal YST2 is input to the input terminal of the shift register SR3, the shift registers SR1 and SR2 are not driven, and driving is started from the shift register SR3. Yes.

  Here, for example, if any of the shift registers SR1 and SR2 ahead of the output terminal of the shift register SR2 is defective, the detection signal (Send) is not detected when the start signal YST is input, but the start signal YST2 When is input, the detection signal (Send) is detected.

  Therefore, according to the third aspect, the shift register position to which the start signal YST is input is changed to detect the presence or absence of the detection signal (Send) and the deviation from the timing of the normal signal. Presence / absence and a shift register having a defect can be identified. Note that the shift register that can detect a defect is determined by the input end of the start signal, and the defect can be detected in units of a shift register sandwiched between input terminals.

  FIG. 8 is a flowchart for explaining an operation example according to the third embodiment. This flowchart is based on the configuration example of FIG.

  The start signal (YST0) is input to start driving from the shift register of the first bit (step S1), and the presence or absence of the final signal (Yend) of the shift register is detected by the detection signal (Send) (step S2). In this detection, if the final signal (Yend) is detected, it is determined that there is no abnormality (step S3), and if the final signal (Yend) is not detected, it is determined that there is an abnormality.

  Next, a start signal (YST2) is input to start driving from the intermediate bit shift register SR3 (step S4), and the presence or absence of the final signal (Yend) of the shift register is detected by the detection signal (Send) (step S5). ). In this detection, if the final signal (Yend) is detected, it is determined that the shift registers SR1 and / or SR2 are abnormal (step S6). If the final signal (Yend) is not detected, there is an abnormality in another shift register. Is determined.

  Next, the start signal (YST-4) is input to start driving from the intermediate bit shift register SR5 (step S7), and the presence or absence of the final signal (Yend) of the shift register is detected by the detection signal (Send) ( Step S8). In this detection, if the final signal (Yend) is detected, it is determined that there is an abnormality in the shift registers SR3 and / or SR4 (step S9). If the final signal (Yend) is not detected, there is an abnormality in another shift register. Is determined.

  Thereafter, similarly, start signals are sequentially input to perform abnormality determination. Finally, a start signal (YSTn-1) is input to start driving from the intermediate bit shift register SR5 (step S10), and the presence or absence of the final signal (Yend) of the shift register is detected by the detection signal (Send) ( Step S11). In this detection, if the final signal (Yend) is detected, it is determined that there is an abnormality in the shift registers SRn-3 and / or SRn-2 (step S12). If the final signal (Yend) is not detected, the shift register SRn- It is determined that 1 and / or SRn is abnormal (step S13).

  In the fourth embodiment shown in FIGS. 9 and 10, in the first embodiment, in addition to the output signal Yend of the end bit, the output signal (Y1,..., Yn-1) of the output terminal OUT of the shift register of each bit is detected. The shift register of the TFT array 4 is inspected based on the output signals (Y1,..., Yn-1) and the final signal (Yend), and each output signal and the final signal are detected by a common signal line. It is a form to do.

  With this configuration, if any shift register is defective, the output signal is detected from the output terminal OUT of the defective bit from the first bit, and the output signal is output from the output terminal OUT of the bit after the defective bit. Is not detected. Therefore, it is possible to detect the defective bit that appears first when viewed from the first bit of the shift register.

  FIG. 10 is a diagram for explaining the timing of each signal in the fourth mode shown in FIG. 10, (a) to (i) are the same as the signals shown in FIG. 3, and show signal states when the shift register is driven from the first bit.

  At this time, the detection signal (Send) detects the output signal (Y1,..., Yn-1) and the final signal (Yend) at the output terminal OUT of the shift register of each bit (FIG. 10 (j)).

  Here, for example, when the third bit shift register SR3 is defective, detection signals corresponding to Y1 and Y2 are detected from the output terminals of the shift registers SR1 and SR2 of the front bits. The detection signals corresponding to Y3, Y4,..., Yend are not detected from the output terminals of the shift registers SR3, SR4,.

  Therefore, according to the fourth aspect, the shift register defect is detected by detecting the presence / absence of the detection signal (Send) and the deviation from the normal signal timing using the signal from the output terminal of the shift register of each bit as the detection signal. The shift register having the presence or absence and a defect can be specified. A shift register that can detect a defect is a shift register of a bit that appears first from the front.

  2, FIG. 4, FIG. 6, and FIG. 9 show the signal line driving circuit 6, the same applies to the scanning line driving circuit 7.

  Next, a configuration example of the second shift register will be described with reference to FIGS.

  The shift register configuration shown in FIGS. 11 to 14 includes shift registers SR1 to SRn and switches SW1 to SWn connected in cascade, and the switches SW1 to SWn switch signals based on the outputs of the shift registers SR1 to SRn. The signal input to the TFT array is controlled. The final signal (Yend) is output from the end bit shift register SRn.

  In the TFT array inspection apparatus 1 of the present invention, the array drive circuit 2 inputs the inspection signal YC to the switches SW1 to SWn and the start signal (YST) to the shift register SR1, as in the first shift register configuration example. Is output to the drive circuit.

  The fifth to eighth forms shown in FIGS. 11 to 14 are forms corresponding to the first to fourth forms of the configuration example of the first shift register described above.

  In the fifth embodiment, the final signal (Yend) of the final shift register SRn is used as the detection signal S, as in the first embodiment, and in the sixth embodiment, the final signal (Yend) of the final shift register SRn (as in the second embodiment). Yend), the output signal of the intermediate shift register is also set as the detection signal S, the seventh form is a form in which a start signal is input to the intermediate shift register as in the third form, and the eighth form is the fourth form. In the same manner as in the first embodiment, the output signal of the intermediate shift register is detected by a common signal line with the final signal (Yend) of the final shift register SRn. Each of the fifth to eighth embodiments can achieve the same effects as the first to fourth embodiments.

  The TFT array can be applied not only to a voltage-driven liquid crystal device but also to an organic EL device that is current-controlled.

  The present invention can also be applied to a device that is driven by a shift register.

It is a figure for demonstrating the outline of the TFT array test | inspection apparatus of this invention. It is the schematic for demonstrating the structure of the 1st form of the shift register of the TFT array test | inspection apparatus of this invention. It is a figure for demonstrating the timing of each signal in the 1st form of the TFT array test | inspection apparatus of this invention. It is the schematic for demonstrating the structure of the 2nd form of the shift register of the TFT array test | inspection apparatus of this invention. It is a figure for demonstrating the timing of each signal in the 2nd form of the TFT array test | inspection apparatus of this invention. It is the schematic for demonstrating the structure of the 3rd form of the shift register of the TFT array test | inspection apparatus of this invention. It is a figure for demonstrating the timing of each signal in the 3rd form of the TFT array test | inspection apparatus of this invention. It is a flowchart for demonstrating the operation | movement in the 3rd form of the TFT array test | inspection apparatus of this invention. It is the schematic for demonstrating the structure of the 4th form of the shift register of the TFT array test | inspection apparatus of this invention. It is a figure for demonstrating the timing of each signal in the 4th form of the TFT array test | inspection apparatus of this invention. It is the schematic for demonstrating the structure of the 5th form of the shift register of the TFT array test | inspection apparatus of this invention. It is the schematic for demonstrating the structure of the 6th form of the shift register of the TFT array test | inspection apparatus of this invention. It is the schematic for demonstrating the structure of the 7th form of the shift register of the TFT array test | inspection apparatus of this invention. It is the schematic for demonstrating the structure of the 8th form of the shift register of the TFT array test | inspection apparatus of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... TFT array test | inspection apparatus, 2 ... Array drive part, 3 ... Shift register output detection part, 4 ... TFT array, 5 ... Substrate, 6 ... Signal line drive circuit, 7 ... Scanning line drive circuit, 8 ... Panel, SR ... Shift register, SW ... switch.

Claims (4)

A TFT array inspection apparatus for inspecting a TFT array sequentially driven by a shift register,
An array driver for outputting a start signal to the shift register;
A shift register output detector for detecting an output signal from the shift register;
A TFT array inspection apparatus that inspects shift register driving of a TFT array based on the presence and / or timing of the output signal.   The TFT array inspection apparatus according to claim 1, wherein the shift register output detection unit detects an output signal of an end bit of the shift register.   2. The TFT array inspection apparatus according to claim 1, wherein the shift register output detection unit detects output signals of intermediate bits and end bits of the shift register.   The array driving unit selectively outputs a start signal to a first bit shift register, a first bit shift register, or an intermediate bit shift register. TFT array inspection equipment.

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