EP0263924B1 - Struktur zum Wiederordnen von Bits auf dem Chip - Google Patents

Struktur zum Wiederordnen von Bits auf dem Chip Download PDF

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Publication number
EP0263924B1
EP0263924B1 EP87110153A EP87110153A EP0263924B1 EP 0263924 B1 EP0263924 B1 EP 0263924B1 EP 87110153 A EP87110153 A EP 87110153A EP 87110153 A EP87110153 A EP 87110153A EP 0263924 B1 EP0263924 B1 EP 0263924B1
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EP
European Patent Office
Prior art keywords
bit
register
data
chip
gate
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EP87110153A
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English (en)
French (fr)
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EP0263924A3 (en
EP0263924A2 (de
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Frederick John Aichelmann, Jr.
Bruce Engle Bachman
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

  • the present invention relates generally to semiconductor memory chips, and more particularly to on-chip structure for randomly accessing data in a block of data held in memory and transferring that data block off-chip through a narrow N bit chip output interface which is smaller than the data block, in accordance with a given wrap protocol, and without incurring data gaps.
  • the main store memory is typically a very large semiconductor memory system that is used to supply data and/or instructions to a cache memory.
  • a cache memory is a small, fast, temporary submemory used to store words called up from the main store memory which are to be operated on. It has been found that when a word is called from the main store memory, that other words in its vicinity in the main store memory are generally also called up.
  • the main store memory is organized in blocks of words and is designed to transfer an entire word block when one word within the block is randomly accessed. Accordingly, a call up to the main store memory comprises multiple transfers of words constituting a block from the main store to the cache memory.
  • the block transfer rate and the size of each transfer is unique to each particular application of the memory, but the following points appear to be general.
  • the starting address of each multi-word block transfer is random, with the initial target address containing a requested word memory coordinate. Once the transfer has started anywhere within the block, a wrap protocol is used to complete the transfer of the entire block in a predetermined order.
  • FIG. 1 A typical design for a prior art memory system is shown in Fig. 1.
  • a user 10 is connected to a main store memory 14 through an interface 12, which provides timing, control and data buffering logic to the main store memory.
  • the main store memory 211 (Fig. 2) comprises a plurality of memory chips 214, connected in parallel to the interface 12.
  • each memory chip 214 provides one parallel bit of data to the cache memory.
  • the number of memory chips 214 is chosen to be equal to the number of bits in an ECC (error correction) word; 72 for many large computers.
  • ECC error correction
  • a set of chips 214 (72 in this example) transfers bits in parallel to form individual 72 bit ECC words in a register 218. This transfer is accomplished for each chip 214 by reading bits from the given chip into an associated external register 226, and then serially gating those bits via an associated gate 228 to the word register 218 in accordance with the counts from a counter 230 which counts in a prescribed wrap order. Note that there is an external register 226, a gate 228, and a counter 230 for each memory chip 214, although only a register 226, a gate 228 and a counter 230 for the memory chip number 1 is shown in Fig. 2 for purposes of clarity.
  • Each memory chip is organized to hold a plurality of separate blocks of data bits, with each of these bit data blocks containing M individual data bits, where M may, in one embodiment, be equal to the number of words in a word block.
  • M may, in one embodiment, be equal to the number of words in a word block.
  • each of these data blocks may contain 8 data bits representing an 8-bit word block.
  • Data in a memory chip is typically accessed by a target address which includes a row and a column address in the chip.
  • the row address generally called the RAS address, causes a series of data blocks stored in a given row to be accessed and held in the sense amplifier latches for the chip.
  • the column address results in one bit in a given data block in the row to be accessed first via register 221, followed by the remaining bits in that data block in the wrap protocol order.
  • This external register 226 then provides this 8 bit data block serially to one of the stages in the word register 218.
  • the memory chip It is essential that once the transfer of the bit data block begins, that it contains no gaps therein. This requirement results from a need that the memory contains a minimum number of chips, i.e., a single row of chips, that preserve a single bit per chip for ECC purposes. In order to ensure such a gapless transfer, it is generally required that the memory chip have a bit interface which is equal to the number of bits in the bit data block, i.e., 8 bits in the present example. However, such an 8 bit interface requires substantially more power than lower number bit interfaces, and has attendant chip cooling problems, increased switching noise, and significantly larger logic support requirements, resulting in lower reliability.
  • a series of transfers for example, two 4-bit transfers could be utilized to transfer the 8 bit data block through a 4 bit chip output interface to the previously noted external register 226.
  • Such a transfer would occur through a standard 8 bit internal holding register (double 4-bit buffer) which holds the addressed bit data block from the sense amplifier latches in the addressed row prior to output through the 4 bit chip output interface.
  • This 8 bit holding register is generally designed to sequentially provide non-overlapping 4 bit sets to the 4 bit output interface in a prescribed sequence, for example stages 1 - 4 from the holding register on one timing pulse, followed by stages 5-8 on the next timing pulse.
  • bit 5 is ready for serial transfer at the same reading rate period t EXT despite the requirement for two separate transfers from the memory chip.
  • the above-described gapless bit transfer operation is only valid if the initial bit address is bit 1 or bit 5, so that three other bits can be read from the external register 226 before the bits from the next 4-bit interface transfer are required.
  • the first word accessed be randomly addressable and that succeeding bits be transferred in a desired wrap protocol. If bit 2, 3, or 4, or bit 6, 7, or 8 is addressed, it can be seen that there will be a time gap until the next 4-bit chip interface transfer is completed. For example, assume that bit 8 is the addressed target bit. In this instance, the bits 5 - 8 are transferred to the external register 226. The gate 228 gates bit 8 to the word register 218 in accordance with the signal from the counter 230.
  • the t EXT stage reading rate period is considerably less than the t CHIP 4-bit chip interface reading rate period, bits 1, 2, and 3 are not yet available from the chip output. Instead, a highly undesirable gap time, tGAP, develops which can be several times the external register reading rate period t EXT .
  • Document GB-A-2 117 145 discloses a memory control system in which data stored in memory are fetched by specified data block depending upon the address signal requesting memory access fed from the execution unit, and the data corresponding to the unit of processing in the execution unit are fetched from the data block fetched and transferred to the execution unit.
  • the invention as claimed is intended to remedy this gapless transfer problem using a single memory chip per bit data block.
  • the advantage offered by the present invention is that a gapless bit data block transfer is achieved while minimizing the number of chips required for ECC integrity when the bit data block is larger than chip output interface. Concommitantly, this design eliminates the need for memory chips with large I/O interfaces and thus reduces the number of drivers, logic supports, and power and cooling requirements for a given memory card.
  • the present invention is a random access memory chip, comprising: a chip memory organized to hold a plurality of separate blocks of data, with each of said data blocks containing M individual data bits in contiguous groups of N bits, where M is greater than N, with each data bit having its own unique address within said blocks, said memory having a predetermined wrap protocol wherein calling for said M bits in a given data block starts with a designated target bit address and continues as if the bit at one end of a data block is contiguous with the bit at the other end of said data block; means for randomly addressing a data bit within a given block of data by means of a designated target address; a N bit chip output interface from said memory; chip register means for holding a block of data, said chip register means including a chip register having at least M register stages for holding said M data bits of said data block, wherein said M register stages are grouped into at least a first and a second register stage group, each group containing N stages, said chip register means further including first gating means for gating in
  • the steering means may include means for programming each gating means by generating control signals in response to a given target address for providing the target address bit along with N-1 bits having following contiguous addresses in the wrap protocol to the first group of N register stages, and for providing each successive set of N bits with following contiguous addresses in the wrap protocol to the second and higher register stage groups.
  • this programming means may comprise means for generating signals in accordance with a truth table in response to a target address, and means for generating TRUE and COMPLEMENT control signals for controlling the gating means for the M register stages.
  • Fig. 1 is a schematic block diagram of a prior art memory system.
  • Fig. 2 is a schematic block diagram of a memory configuration that may be used in the present invention.
  • Fig. 3 is a schematic block diagram of one embodiment of the present invention.
  • the present invention is directed to an on-chip circuit for performing a gapless bit data block transfer when the bit data block is larger than the chip output interface. This gapless transfer is accomplished by steering the data bits being accessed from the memory array of the chip to prescribed positions in a holding register, with the steering being accomplished in accordance with a specific target address.
  • the present invention is a new design for the control circuitry for a standard memory chip.
  • the present invention is designed to be utilized with a standard memory array chip composed of rows and columns of standard memory cells with multiple bit outputs.
  • a typical memory chip of this type could be either a 256k ⁇ 4 or a 2MX4 DRAM
  • the present invention has broad applicability to a wide variety of memory chips and memory arrays.
  • the present invention is not limited to a particular output interface size, or to a particular bit data block size, or to a given word size.
  • the present invention will be disclosed in the context of a memory chip organized in bit data blocks of 8 bits and using a 4-bit output interface.
  • a standard memory array composed of rows and columns of memory cells is designated by the block 10 in the Figure.
  • An address line 12 is applied to the memory array 10 in order to access a particular target address bit. This address causes an entire row of memory cells to be accessed and their data applied to associated sense amplifiers. The data bits are then applied from these sense amplifiers to associated sense amplifier latches or buffer stages, represented by the register 14 in the Figure.
  • each row contains a plurality of 8-bit data blocks.
  • the address on the address line 12 causes the sense amplifiers associated with one particular block of data bits to be selected and to provide those data bits to the sense amplifier latches or buffer stages 1-8, represented in the Figure by register 14.
  • the chip memory array is organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data bits in contiguous groups of N bits, where M is greater than N, with each data bit having its own unique address within the data blocks.
  • the chip further comprises chip register means 16 for holding a given block of bit data, with chip register means 16 having at least M register stages 18 for holding the M data bits of the given data block.
  • This chip register means 16 is organized with the M stages of the holding register 18 grouped into at least a first and a second contiguous group of N stages each, where N is the number of bits in the output interface for the chip.
  • the chip register means 16 further includes a register gating means 20 for gating the first stage group of N register stages to the N bit output interface, followed in sequence, by the second stage group and higher groups. It should be noted that the chip register means 16 is organized so that a bit at one end of a bit data block is considered to be contiguous with a bit at the other end of the bit data block.
  • the first gating means 20 of chip register means 16 may be implemented in a variety of configurations.
  • the first gating means 20 is shown to include a plurality of register gates 22 and 24, one for each register stage group of N stages. These register stages 22 and 24 gate the data in their associated register stage groups into an N bit output interface.
  • This N bit output interface may be composed simply of an OR gate 26, or a gate which follows therefrom.
  • Each of the register gates 22 and 24 operates to pass N parallel outputs in accordance with a timing signal.
  • Register gate 22 passes its N parallel outputs in accordance with a TOGGLE timing signal
  • register gate 24 passes its N parallel outputs in accordance with a NOT TOGGLE timing signal. Accordingly, either one or the other of the parallel sets of N outputs, but not both, is applied to the N bit output interface gate 26.
  • an 8-bit data block is utilized, so that there are 8 register stages 1 ⁇ - 8 ⁇ in the holding register 18.
  • the holding register 18 provides a first set of 4 parallel bit outputs from register stages 1′-4 ⁇ to the register gate 22 for application to the OR gate 26 upon the occurrence of a TOGGLE pulse.
  • the holding register 18 provides a second set of 4 parallel bit outputs from the register stages 5′-8 ⁇ to the register gate 24 for application to the OR gate 26 upon the occurrence of a NOT TOGGLE pulse.
  • the M, or 8 in this example, data bits held in the sense amplifier stages 1 - 8 of latches 14 can be provided directly to the respective individual stages 1 ⁇ - 8 ⁇ in the holding register 18.
  • the present memory array is randomly addressable and provides succeeding bits in a particular wrap protocol, the majority of bit transfers from the register 18 to the 4-bit output interface 26 will have gaps therein.
  • bit number 4 or bit 8 is the target address bit
  • the first four bits 1-4 are passed via the stages 1 - 4 in the register 14 and the holding register stages 1′-4 ⁇ to the register gate 22 and thence to the OR gate 26.
  • Chip steering means 30 operates to provide in a first set, and in any desired order, the bit at the target address along with N-1 bits having following contiguous addresses in the memory wrap protocol from within the data block to the first group of N register stages in the holding register 18.
  • the chip steering means 30 provides the bits 1, 2, 3 and 8 to the second group of four register stages 5′-8 ⁇ in the holding register 18.
  • the bits 5, 6, 7 and 4 are provided first through the 4-bit output interface 26, followed by the bits 1, 2, 3, and 8.
  • These bits are held in the external register 226 and are read therefrom in the proper order beginning with the target address bit 4 by means of the counter 230.
  • the counter 230 is set to begin its count at bit 4 by applying the lower 3 address bits A2, A1, A0 thereto. (The present counter is incremented after each data transfer and the results are decoded to select the appropriate bit to be outgated from the register 226.)
  • the basic logic circuit in the chip steering means comprises, for each register stage 1 ⁇ - 8 ⁇ in the holding register 18, means 30 associated therewith for providing a different bit from each of the different bit groups in a given data block in the memory, and second means 32 for gating one and only one data bit from the providing means 30 to its associated register stage in accordance with the target address to thereby effect the wrap protocol.
  • the steering means comprises, for each register stage, means 30 for providing a bit from its prescribed bit position from each of the bit groups in a given data block; and second means 32 for gating one and only one data bit from the providing means to its associated register stage in the holding register 18 in accordance with the target address to effect the wrap protocol.
  • Fig. 3 shows one embodiment for the providing means 30.
  • This second gating means 32 comprises a plurality of AND gates, with a different AND gate for each bit group in the data block for receiving data therefrom.
  • the AND gates associated with the 1 ⁇ stage of the holding register 18 comprises an AND gate 40 for receiving the 1 data bit from the 1 stage of the sense amplifier latches 14, while an AND gate 42 is provided for receiving the 5 data bit from the 5 stage in the sense amplifier latches 14.
  • Each of these AND gates 42 and 40 receives a control signal from a programming means 90, to be discussed below.
  • the output from one of the AND gates 40 or 42 is applied to an OR gate 44 for providing bit data to the associated register stage 1 ⁇ in the holding register 18.
  • the outputs from the AND gate 46 or the AND gate 48 is provided to the OR gate 50 for application to the 2 ⁇ stage in the holding register 18.
  • Bit number 6 and bit number 2 are applied via the AND gates 70 and 72, respectively, to the OR gate 74 and the 6 ⁇ stage in the holding register 18.
  • the data gates used for steering purposes may be implemented with the data gates normally used for partial stores within a multi-bit chip structure.
  • the providing means 30 further includes means for programming each of the second gating means 32 by generating control signals in response to a given target address for providing the target address bit along with the N-1 bits having following contiguous addresses in the memory wrap protocol to the first group of N register stages in the holding register 18, and for providing each successive set of N bits with following contiguous addresses in the wrap protocol to the second and higher register stage groups in the holding register 18.
  • the foregoing functional description is realized by applying a control signal from the programming means 90 as a second input to each of the AND gates 40, 42, 46, 48, 50, 52, 54, 58, 60, 64, 66, 70, 72, 76, 78, 82, and 84.
  • control signals ensure that one and only one data bit from the sense amplifier latches 14 is applied through the associated OR gate to each of the associated stages in the holding register 18. It should be noted that there are a variety of techniques available for generating control signals, and a variety of techniques for ORing the various bit numbers in the sense amplifier latches 14 for application to the holding register 18. In the embodiment shown in Fig. 3, 2M control signals are generated; one control signal for each AND gate in the second gating means 32. In this example embodiment, the programming means is implemented by means 92 for generating signals in accordance with a true table in response to the target address applied on line 94.
  • Means 96 is then provided for generating TRUE and COMPLEMENT control signals in response to the signals from means 92 for controlling the second gating means 32 for the register stages in the holding register 18.
  • this generating means 96 comprises a set of N data gates 98 and an associated set of inverting gates 100.
  • Each of the data gates receives a signal from the truth table generating means 92 and provides a TRUE signal in response thereto.
  • the output from each data gate is applied to control one of the pair of AND gates in each of the second gating means 32 which is associated with a prescribed bit position in each of the bit groups in a given bit data block.
  • data gate 98A applies the TRUE output to control one of the pair of AND gates in the second gating means 32 which is associated with the 4 ⁇ stage and the 8 ⁇ stage in the holding register 18. Additionally, the TRUE output from the data gate 98A is applied to an inverting gate 100A which generates a COMPLEMENT output. The COMPLEMENT output from the inverting gate 100A is applied to control the other of the AND gates for the second gating means 32 associated with the 4 ⁇ stage and the 8 ⁇ stage of the holding register 18. In the example of Fig. 3, the TRUE output from the data gate 98A is applied to AND gate 60 along with the bit 8 output from the sense amplifier latches 14.
  • the TRUE output from the data gate 98A is also applied to the AND gate 84 along with bit 4 from the sense amplifier latches 14.
  • the COMPLEMENT output from the inverting gate 100A is applied to the AND gate 58 along with the bit 4 output from the sense amplifier latches 14.
  • This COMPLEMENT output from the inverting gate 100A is also applied to the AND gate 82 along with the bit 8 output from the sense amplifier latches 14. Accordingly, it can be seen that when the TRUE output from the data gate 98A is high, and the COMPLEMENT output from inverting gate 100A is low, then bit 8 from the sense amplifier latches 14 is applied through the AND gate 60, and the OR gate 62 to the 4 ⁇ stage in the holding register 18.
  • bit 4 from the sense amplifier latches is applied through the AND gate 84 and the OR gate 86 to the 8 ⁇ stage in the holding register 18.
  • bit number 4 from the sense amplifier latches 14 is applied through the AND gate 58 and the OR gate 62 to the 4 ⁇ stage of the holding register 18.
  • bit number 8 from the sense amplifier latches 14 is applied through the AND gate 82 and the OR gate 86 to the 8 ⁇ stage of the holding register 18.
  • the data gates 98B, 98C and 98D and their associated inverting gates 100B, 100C and 100D are connected in a similar fashion to control the AND gates for the other prescribed bit positions n in the bit groups in the data block. Accordingly, the TRUE output from the data gate 98B is applied to AND gate 54 along with the bit 7 output from the sense amplifier latches 14. Likewise, a true output from the data gate 98B is applied to the AND gate 78 along with the bit 3 output from the sense amplifier latches 14. The associated inverting gate 100B applies its COMPLEMENT output to the AND gate 52 along with the bit 3 output from the sense amplifier latches 14 and to AND gate 76 along with the bit 7 output from sense amplifier latches 14.
  • bit number 7 from the sense amplifier latches 14 is applied through the AND gate 54 and the OR gate 56 to the 3 ⁇ stage in the holding register 18.
  • a high signal for the TRUE signal from the data gate 98B causes the bit number 3 from the sense amplifier latches 14 to be applied through the AND gate 78 and the OR gate 80 to the 7 ⁇ stage of the holding register 18.
  • Data gate 98C is likewise connected to have its TRUE output applied to the AND gate 48 along with bit number 6 from the sense amplifier latches 14.
  • the TRUE output from the data gate 98C is also applied to the AND gate 72 along with the bit number 2 from the sense amplifier latches 14.
  • the inverting gate 100C associated with the data gate 98C applies its COMPLEMENT output to AND gate 46 along with bit number 2 from the sense amplifier latches 14.
  • the inverting gate 100C also applies its COMPLEMENT output to the AND gate 70 along with the bit number 6 from the sense amplifier latches 14.
  • the TRUE output from the data gate 98D is applied to the AND gate 42 along with the data bit number 5 from the sense amplifier latches 14.
  • the TRUE output from the data gate 98D is also applied to the AND gate 66 along with the bit number 1 from the sense amplifier latches 14.
  • the associated inverting gate 100D applies its COMPLEMENT output to the AND gate 40 along with the bit number 1 from the sense amplifier latches 14 and to the AND gate 64 along with the bit number 5 from the sense amplifier latches 14.
  • truth table coder 92 the four input signals to the data gates 98A - 98D are generated by truth table coder 92 in response to the target bit address.
  • This truth table coder may be implemented by a variety of different circuit configurations based on a desired truth table. In the embodiment shown in Fig. 3, a truth table may be utilized to implement the bit steering.
  • This truth table includes a column for a target bit, the last three digits of the binary address for that target bit, and four additional columns; one column for each of the data gates A - D.
  • the purpose of the truth table is to steer the data bits so that the target data bit and N-1 bits having following contiguous addresses in the memory wrap protocol occur within the first N register stages in the holding register 18. For example, if the target bit is bit number 4 in the sense amplifier latch, then it is desired to have bits 4, 5, 6 and 7 (the target bit and the first N-1 bits following the target bits) steered to the first four register stages 1 ⁇ - 4 ⁇ in the holding register 18.
  • bit number 4 is applied through the AND gate 58 and the OR gate 62 to the 4 ⁇ stage of the holding register 18.
  • bit number 1 is applied through the AND gate 66 and the OR gate 68 to the 5 ⁇ stage
  • bit number 2 is applied through the AND gate 72 and the OR gate 74 to the 6 ⁇ stage
  • bit number 3 is applied through the AND gate 78 and the OR gate 80 to the 7 ⁇ stage
  • bit number 8 is applied through the AND gate 82 and the OR gate 86 to the 8 ⁇ stage of the holding register 18.
  • the four bits held in the stages 1 ⁇ - 4 ⁇ are gated by the TOGGLE signal through the gate 22 and the OR gate 26, which may be viewed as the N-bit output interface for the chip.
  • the bits 5, 6, 7, and 4 are held in the external register 226 in Fig. 2.
  • These four bits may be gated out via the gate 228 to the appropriate stage in the word register 218 in accordance with the counter 230.
  • the counter 230 and other support logic operates to provide the bits in the proper sequence of 4, 5, 6, and 7 to the appropriate stage in the word register 218.
  • the bits 1, 2, 3 and 8 held in the 5 ⁇ - 8 ⁇ stages of the holding register 18 may be transferred in accordance with the NOT TOGGLE timing signal through the gate 24 and the OR gate 26 output interface to the other four stages in the external register 226.
  • the truth table coder 92 provides the data gate 98D with a one output, 98C with a one output, 98B with a zero output and 98A with a zero output.
  • the control signals generated in response to these truth table signal inputs cause the 1 ⁇ - 4 ⁇ stages in the holding register 18 to hold the bits 1, 2, 7 and 8, respectively.
  • These bits are again gated upon the occurrence of the TOGGLE timing signal through the gate 222 and the OR gate 226 to the external register 226.
  • These bits are then gated by the gate 228 in the proper order of 7-8-1-2 in accordance with the counter 30 which begins at the target address 110 for the target bit number 7.
  • the 5 ⁇ - 8 ⁇ stages of the holding register 18 hold the bits 5-6-3-4, respectively. These bits are gated in accordance with the NOT TOGGLE signal through the gate 24 and the OR gate 26 to the other four stages in the external register 226. The gating of this second group of 4 bits occurs again during the gating of the first group of 4 bits to the appropriate stage in the word register 218. After these first four bits 1, 2, 7, 8 have been gated in the proper order to the word register 218, the next 4 bit group 5-6-3-4 is gated via the gate 228 in the proper order to the same stage in the word register 218.
  • a gapless bit data transfer has been achieved while minimizing the number of chips required for ECC integrity when the M bit data block is larger than the chip N-bit output interface.
  • the present design also eliminates the requirement for chips with large I/O interfaces, thereby reducing the number of required drivers, logic supports, and reducing the power and cooling requirements for a given memory card.
  • Such a memory card also has improved reliability because of the fewer required logic supports and the lower switching noise attendant to the use of a smaller I/O interface.
  • the present gapless transfer design provides the highest performance option for memory arrays where the chip data rate is larger than the system transfer rate.

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Claims (5)

  1. Ein Speicherchip mit wahlfreiem Zugriff, umfassend:
    einen Chipspeicher (10), organisiert, um eine Vielzahl einzelner Datenblöcke zu halten, wobei jeder der Datenblöcke M einzelne Datenbits in zusammenhängenden Gruppen von N Bits enthält, wobei M größer als N ist, wobei jedes Datenbit seine eigene einzelne Adresse innerhalb des Blocks besitzt, der Speicher ein vorherbestimmtes Schleifenprotokoll besitzt, wobei der Aufruf der M Bits in einem gegebenem Datenblock mit einer gegebenen Startbit-Adresse beginnt und fortgesetzt wird, als ob das Bit an einem Ende des Datenblocks mit dem Bit an dem anderen Ende des Datenblocks benachbart ist;
    Mittel (12) für die wahlfreie Adressierung eines Datenbits innerhalb eines gegebenen Datenblocks mittels einer vorherbestimmten Zieladresse;
    einem N-Bit-Chipausgangsinterface (26) von dem Speicher;
    Chipregistermittel (16) für das Halten eines Datenblocks, wobei das Chipregistermittel (16) ein Chipregister (18) umfaßt, das wenigstens M Registerstufen für das Halten der M Datenbits des Datenblocks besitzt, wobei die M Registerstufen in wenigstens eine erste (1', ..., 4') und eine zweite (5', ..., 8,) Gruppe von Registerstufen eingeteilt sind, jede Gruppe N Stufen enthält, wobei das Chipregistermittel (16) weiterhin erste Torsteuerungsmittel (20) für das nacheinderfolgende Verbinden der ersten Registerstufengruppe und der zweiten Registerstufengruppe zu dem N-Bit-Ausgangsinterface (26) enthält; und
    Chipsteuermittel (30), das eine Vielzahl von Liefermitteln enthält, jedes für die Lieferung einer N-Bit-Gruppe, jedes Bit verbunden mit einem anderen Datenbit von jeder der Bitgruppen in einem Datenblock in dem Speicher; eine Vielzahl von zweiten Torsteuerungsmitteln (40 bis 62; 64 bis 86), jedes verbunden mit der Bitgruppe eines der Liefermittel (30) für die Steuerung von Datenbits gemäß der Zieladresse um das Schleifenprotokoll zu beeinflussen,
    dadurch gekennzeichnet, das eines der Liefermittel und eines der zweiten Torsteuerungsmittel für jede der Registerstufengruppen der Chipregister (18) geliefert wird, wobei das zweite Torsteuerungsmittel die Daten zu den zugehörigen Registerstufengruppen des Chipregisters (18) leitet;
    daß er weiterhin einen Puffer (14) für das Halten der Bitgruppen des gegebenen Datenblocks, der das Zieladreßbit enthält, umfaßt; daß das Liefermittel (30) die Bitgruppen erhält, die in dem Puffer für die Versorgung des zweiten Torsteuerungsmittels (32) gehalten werden;
    daß jedes der zweiten Torsteuerungsmittel (40 bis 62; 64 bis 86) Logikgatterpaare (40, 42; 46, 48; ..) enthält und daß jedes Bit (z. B. 1) einer Bitgruppe (z. B. 1, .., 4) in dem Pufferregister (14) parallel mit zwei Logikgattern (40, 66) verbunden ist, wobei jedes zu einem Logikgatterpaar (40, 42; 64, 66) in unterschiedlichen zweiten Torsteuerungsmitteln gehört,
    wobei das Steuerungsmittel durch Anwenden des Schleifenprotokolls an die ersten und zweiten Registerstufengruppen das Zielbit (z. B. 4) gemeinsam mit N-1 Bits, die nachfolgende benachbarte Adressen (5, 6, 7) besitzen, an die erste und zweite Registerstufengruppe liefert, und das Bit (z. B. 8), das mit dem anderen Logikgatter des Logikgatterpaares verbunden ist, mit dem das Zielbit verbunden ist, gemeinsam mit N-1 Bits, die nachfolgende benachbarte Adressen (1, 2, 3) besitzen, an die zweite Registerstufengruppe liefert.
  2. Ein Speicherchip gemäß Anspruch 1 dadurch gekennzeichnet, daß das Steuerungsmittel Mittel (90) für die Programmierung jedes der zweiten Torsteuerungsmittel (40 bis 62; 64 bis 86) durch Erzeugung von Steuersignalen als Antwort auf eine gegebene Zieladresse umfaßt.
  3. Ein Speicherchip gemäß Anspruch 2 dadurch gekennzeichnet, daß das Programmiermittel (90) Mittel (96) für die Signalerzeugung gemäß einer Wahrheitstabelle als Antwort auf die Zieladresse und Mittel (98), empfindlich gegenüber dem Signalerzeugungsmittel für die Wahrheitstabelle, für die Erzeugung von TRUE (98A, ...) und KOMPLEMENT (100A, ...) Steuersignalen für die Steuerung der zweiten Torsteuerungsmittel (40 bis 86) für die M Registerstufen in dem Chipregister (18) umfaßt.
  4. Ein Speicherchip gemäß Anspruch 3, dadurch gekennzeichnet daß die Logikgatterpaare UND-Gatter (40, 42; 46, 48; ...) mit einem anderen UND-Gatter für jede Bitgruppe in dem Datenblock für die davon empfangenen Daten sind und mit jedem der UND-Gatter (40, 42; 46, 48; ...) ein Steuersignal von dem Programmiermittel (90) empfangen wird; und daß
    ein ODER-Gatter (44, 50) mit jedem der UND-Gatterpaare für die Lieferung von Einheitsdaten von einem der UND-Gatterpaare (40, 42) mit der zugehörigen Registerstufe des Chipregisters (18) verbunden ist.
  5. Ein Speicherchip gemäß Anspruch 4, dadurch gekennzeichnet, daß das erste Torsteuerungsmittel (22) eine Vielzahl Registergatter (22, 24), eines für jede Registerstufengruppe der Chipregister (18), umfaßt, wobei die Registergatter (22, 24) die Daten in den Registerstufengruppen zu den N-Bit Ausgangsinterface leiten.
EP87110153A 1986-09-15 1987-07-14 Struktur zum Wiederordnen von Bits auf dem Chip Expired - Lifetime EP0263924B1 (de)

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US06/907,192 US4845664A (en) 1986-09-15 1986-09-15 On-chip bit reordering structure
US907192 1986-09-15

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EP0263924A2 EP0263924A2 (de) 1988-04-20
EP0263924A3 EP0263924A3 (en) 1990-09-19
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EP (1) EP0263924B1 (de)
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US4845664A (en) 1989-07-04
EP0263924A3 (en) 1990-09-19
JPH0524596B2 (de) 1993-04-08
DE3788032D1 (de) 1993-12-09
JPS6373447A (ja) 1988-04-04
DE3788032T2 (de) 1994-05-11
EP0263924A2 (de) 1988-04-20

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