EP0250450A1 - Lead finishing for a surface mount package - Google Patents

Lead finishing for a surface mount package

Info

Publication number
EP0250450A1
EP0250450A1 EP86905650A EP86905650A EP0250450A1 EP 0250450 A1 EP0250450 A1 EP 0250450A1 EP 86905650 A EP86905650 A EP 86905650A EP 86905650 A EP86905650 A EP 86905650A EP 0250450 A1 EP0250450 A1 EP 0250450A1
Authority
EP
European Patent Office
Prior art keywords
solder
lead
leads
wettable
package body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86905650A
Other languages
German (de)
French (fr)
Inventor
Paul T. Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0250450A1 publication Critical patent/EP0250450A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10909—Materials of terminal, e.g. of leads or electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2081—Compound repelling a metal, e.g. solder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Un boîtier de montage en surface (60) comprend plusieurs conducteurs de boîtiers extérieurs (64) à double surface finie (66, 68). La partie inférieure du conducteur qui doit être liée à un bloc de liaison (74) d'un substrat (70), tel qu'un tableau de circuit imprimé, est pourvue d'une surface (68) mouillable avec de la soudure, ladite surface s'étendant uniquement sur une partie de la longueur du conducteur (64) afin de rencontrer une partie (66) de surface non mouillable. Alternativement ou additionnellement, les parties supérieures des conducteurs (64) peuvent être revêtues à l'aide d'une composition chimique, d'une composition plastique ou d'une autre composition rejetant la soudure (84), permettant d'obtenir la partie (66) de surface non mouillable. Les liens obtenus grâce à l'utilisation desdits conducteurs (64) sont plus résistants et plus fiables, grâce à l'affinité de la soudure (72) pour le conducteur (64) au niveau de la zone de contact (74) et grâce à la réticence de la soudure (72) à amener le conducteur, telle une mèche, dans la zone non mouillable (66) du conducteur (64) plus près du boîtier (60) éloignant ainsi la soudure (72) de la zone de liaison (74). La configuration de la liaison de soudure peut être modifiée rapidement et aisément en régulant la surface ou la profondeur de la région (68) revêtue par la soudure uniquement sur la partie inférieure des conducteurs (64) du boîtier de montage en surface (60) pour circuits intégrés.A surface mount box (60) includes a plurality of outer case conductors (64) with a finished double surface (66, 68). The lower part of the conductor which must be linked to a connection block (74) of a substrate (70), such as a printed circuit board, is provided with a surface (68) wettable with solder, said surface extending only over part of the length of the conductor (64) in order to meet a part (66) of non-wettable surface. Alternatively or additionally, the upper parts of the conductors (64) can be coated using a chemical composition, a plastic composition or another composition rejecting the solder (84), making it possible to obtain the part ( 66) of non-wettable surface. The links obtained through the use of said conductors (64) are more resistant and more reliable, thanks to the affinity of the solder (72) for the conductor (64) at the level of the contact zone (74) and thanks to the reluctance of the solder (72) to bring the conductor, like a wick, in the non-wettable zone (66) of the conductor (64) closer to the housing (60) thus moving the solder (72) away from the connection zone ( 74). The configuration of the solder joint can be changed quickly and easily by controlling the area or depth of the region (68) coated by the solder only on the bottom of the conductors (64) of the surface mount box (60) to integrated circuits.

Description

Field of the Invention
This invention relates to integrated circuit packages and more particularly relates to surface mountable integrated circuit packages and the solder bonding thereof.
Background of the Invention
Integrated circuits were early encased in dual-in-line packages (DIPs), which are small, elongated plastic boxes with the exterior leads coming out on either side of the box and turning down in two parallel rows, one along each side of the package. DIPs are mounted into corresponding holes in a printed circuit board that have been plated through and to which the DIPs are soldered to make electrical and mechanical connection.
As integrated circuits became smaller and more complex, the number of leads coming out of the package increased, even though the package size remained the same or decreased. One solution to this problem was the flat, plastic leaded chip carrier (PLCC) , which typically is a small, flat, square package having the leads coming out and formed around each of the four edges of the package. PLCCs are typically mounted in sockets with contacts that mate with the leads on the PLCCs.
More recently PLCCs have been surface mounted directly on the corresponding pattern of electrical contact pads on a printed circuit board. Surface mounting of parts has gained widespread interest of late because of the ease with which the parts can be picked up and placed on the printed circuit board in contrast to a through-hole package which must be much more precisely aligned. Not only may a printed circuit board be more easily populated with ICs, but they may also be more easily removed. In addition, it is possible to achieve a higher density of ICs on a printed circuit board with surface mount pac ages. so, e ea s on e pac ages o e sur ace mounted are often much shorter and better protected than leads that are mounted through holes in the printed circuit board so that there is less danger of damage to the leads during handling of surface mountable packages. The leads on surface- mounted packages such as PLCCs, quad packs or DIPs tend to be of one of three types: J-lead, butt joint and gull wing. J-Leads come out from the side of the package body and turn down and curl under and into the package bottom. The mounting surface for a J-lead is the bottom of the curl. Butt joint leads come out from the side of the package body and turn down and meet the mounting substrate head-on and perpendicular to the mounting surface. Finally, gull wing leads come out from the side of the package body and turn down and then turn out away from the package parallel to the mounting substrate surface.
Typically, for all of the surface mount lead forms, both the leads and the bonding pads on the mounting substrate, such as a printed circuit board, are plated or coated with tin or solder. A solder mask for the printed circuit (PC) board must be defined and generated, after which the solder paste must be applied to the PC board which requires an alignment step of the mask. The actual application of solder paste is typically done using a stencil process or a screen process, as in silk screen printing, both of which involve many variables and can be complex. The leads of the surface mount devices are also plated or coated with tin or solder in some fashion and then picked up and* positioned onto the PC board, which has two patterns thereon, the PC artwork and the solder mask artwork. This positioning constitutes a second alignment step. Finally, the solder undergoes reflow to make the surface joint by either a vapor phase or an infrared (IR) treatment. Often, the leads do not have tin or solder on their ends which produces weak bonds as will be described later.
The solder reflow step to make the mechanical and electrical bond of the lead to the substrated bonding pad can run afoul in a number of different ways. For example, FIG. 1 demonstrates the appropriate bond 10 of J-lead 12 of package 14 to bonding pad 16 of substrate 18 which is difficult to achieve in practice. If as in FIG. 2, the solder 20 does not properly wet the plating on lead 22 of package 24, dewetting occurs and the bond area of lead 22 to bonding pad 26 of substrate 28 shrinks undesirably to give a bond that is weak both mechanically and electrically. This solder dewetting problem typically occurs in cases where the leads have been solder plated. The typical solution includes additional fusing or reflow steps for the uncoated or thin lead ends, where this is a particular problem for gull wing and butt joint leads.
An opposite effect may also commonly occur as shown in FIG. 3 where the solder paste 30 sufficiently wets the lead 32 of package 34 but tends to wick up the lead 32 rather than stay near bonding pad 36 of substrate 38, again reducing the bonding area forming a weak mechanical and electrical bond. The wicking problem tends to occur if the leads are wave soldered or solder dipped. Another problem with the wave soldering or solder dipping of the entire lead is that only a limited solder coating thickness may be applied and that often the coating on the lead corners of the resulting bond is too thin. This is particularly a problem with J-leads.
Proposed solutions to the dewetting and wicking problems of surface mount leads include using physical solder dams around the bonding pads of the substrate to shape the bond as it is being formed, and to use a clad or sandwich lead as shown in FIG. 4. Lead 40 of package 42 is made up of three layers, the interior layer 44 which is the lead metal and the bulk of lead 40, an outer wettable material layer 46 such as nickel and an inner non-wettable material layer 48 such as an aluminum bronze. While such a structure helps alleviate the wicking problem up the interior portion of the lead, wicking of solder 50 may still occur on the outer layer 46, again reducing the bonding area of lead 40 to bonding pad 52 on substrate 54. Additionally, such a lead 40 is much more complex in structure and therefor more costly than the standard plated lead.
One problem with the tin plating that is sometimes use on e e tin whiskers or intermetallic lines often form between leads over a period of time which cause leakage problems. Another problem with tin or solder plated leads is that, in general, the leads have uncoated, bare metal ends, because the parts are plated in strip form and cut to size to form the leads. Uncoated, bare metal ends are a problem, particularly in the butt joint form of surface mount devices because the end of the lead is thus not wettable by solder and voids under the lead end tend to form which compromise the electrical and mechanical integrity of the bond.
It would be an advance in the art if an inexpensive lead for surface mountable packages could be devised which would avoid the dewetting and wicking problems described.
Summary of the Invention
Accordingly, it is an object of the present invention to provide a lead for surface mountable packages which is solder wettable but which does not permit the solder to wick up the lead during a bonding operation.
Another object of the invention is to provide a surface mountable package lead that is inexpensive and readily manufacturable.
Yet another object of the present invention is to provide a lead for surface mountable packages that avoids thin solder coatings.
Still another object of the invention is to provide a butt joint surface mountable package having the above-noted features and wherein the ends of the leads are also made solder-wettable.
In carrying out these and other objects of the invention, there is provided, in one form, a surface mountable integrated circuit package having a package body and a plurality of exterior leads depending therefrom in which only the upper portions of the exterior leads adjacent the package body are provided with a non-solder-wettable surface. Brief Description of the Drawings
FIG. 1 is a cross-section of a portion of a surface mountable integrated circuit (IC) package of the prior art illustrating a proper solder bond;
FIG. 2 is a cross-sectional illustration of a portion of a surface mounted IC package having a solder bond that is unacceptable due to a problem with dewetting of the lead;
FIG. 3 is a cross-sectional illustration of a portion of a surface mountable IC package having a solder bond that is improperly formed due to wicking of the solder up the wettable lead;
FIG. 4 is another cross-sectional illustration of a portion of a surface mountable IC package, showing a prior art solution to part of the bonding problems;
FIG. 5 is a cross-sectional drawing of a portion of a surface mountable IC package which illustrates the leads of the present invention;
FIG. 6 is a cross-sectional illustration of another embodiment of the. invention revealing how the surface of the upper portions of the exterior leads may be provided with a chemical coating to render them non-wettable by solder or flux; and
FIG. 7 is another cross-section of an alternate embodiment illustrating a surface mountable DIP where the entire package body as well as the upper portions of the exterior leads have been coated.
Detailed Description of the Invention
The prior art forms of leads to surface mountable IC packages have already been discussed, but it should be remembered that the correct and proper solder bond 10 shown in FIG. 1 is, in actual practice, difficult to achieve due to the problems of solder dewetting seen in FIG. 2 and solder wicking seen in FIG. 3. It should be noted that the term "solder" as used herein includes flux, solder paste and all other means of orm ng a me a - o-me a means of a flowable material that may be changed in some manner to form at least a hard bond.
The prior art solution to the surface mount problems using double clad lead 40 of FIG. 4 is only a partial solution to these problems in that while dewetting does not happen on outside layer 46, a wicking problem of the solder 50 up the lead 40 may still occur.
Shown in FIG. 5 is a surface mountable IC package 60 housing an integrated circuit chip 62, having a plurality of partially finished J-leads 64 of the present invention. While J-leads are illustrated, it will be understood that butt joint and gull wing leads also suffer from the problems described above which may also be solved by the structure of the present invention. J-leads have been chosen to illustrate the invention since the dewetting and wicking problems with solder are particularly pronounced with J-leads.
J-Leads 64 have two portions, one of which is an upper or dewetting portion 66 which may comprise the bare lead metal or the lead which has been entirely plated with a dewetting substance such as a lead/tin solder composition where the proportion by weight of lead to tin is 90/10 or more. There is an apparent inconsistency in calling the upper part of lead 64 "non-solder-wettable" when in fact it is plated with a lead/tin formulation. It should be noted that the plating substance while indeed a formulation of lead and tin and therefore a solder in the broadest sense, has such a high lead content that it may be considered "non-wettable" by the solder formulations required to be used to obtain the acceptable electrical and physical bond of a lead 64 to a bonding pad 74.
On the lower portion of leads 64 is a solder wettable surface 68 which extends only part-way up the lead 64. In one form of the invention, solder wettable surface 68 covers only the lower half or less of lead 64. The solder wettable surface 68 may be a metal surface or a plated surface that is wettable by solder or may be a surface that already has a thin solder coating thereon. In a more particular embodiment, the region 68 is a solder coating having a composition with a lead to tin weight ratio of 63/37 or less, such as 60/40, which is applied by wave soldering the lower ends of leads 64 or by dipping just the ends of leads 64 into a solder paste or molten solder bath. Ordinarily this procedure would give a wicking problem, but since the solder-philiσ region is only part-way up the length of the lead and meets with a solder-phobic region, a proper bond may be formed without the wicking problem. It is anticipated that the leads of the present invention could be assembled in a variety of ways including covering the entire lead 64 with a solder wettable surface 68 and then applying a non-wettable surface, coating or plating 66 on the upper half or more of the lead. Alternately, lead 64 could be partially covered with a non-wettable surface 66 and partially covered with a wettable surface 68 in any appropriate sequence.
The exact proportion of lead 64 covered by solder coated area 68 is not important. In most cases, solder coated area 68 should cover an area equal to and slightly more than that area of lead 64 needed to obtain a good or ideal solder bond 72 to the substrate 70. One will have to optimize where the wettable/non-wettable interface is to be as a function of pad size and shape on the substrate. For most surface mountable packages 60, solder coated area 68 may be at least the lower half of lead 64.
The mounting of IC package 60 onto printed circuit (PC) board substrate 70 is conducted in the customary fashion. Solder 72 in the form of a paste or coating is placed on the the bonding pads 74 of the PC board substrate 70. Leads 64 are then aligned to correspond to the pattern of bonding pads 74 on PC board 70 and a solder reflow operation is performed to create the solder bonds. Since the lower portion 68 of the leads is solder wettable, a good bond forms, particularly because the solder 72 cannot wick up past the boundary of coated and wettable region 68; it being repelled by upper non-wettable region 66.
Thus, the leads 64 of the present invention avoid thin solder coatings thereon due to the presence of solder wettable region 68. Since the lead ends are provided with solder paste , those areas of lead 64 and bonding pad 74 actually involved in the solder bond. Because the bonding structure and method of this invention do not involve tin plating, tin whisker leakage and tin intermetalliσ formation problems are avoided.
It should also be noted that the substrate level solder joint configuration can be controlled by controlling the depth of the solder dip onto the leads, that is the wettable surface area 68. If more solder is needed for a proper bond, the leads 64 may be dipped or wave soldered somewhat deeper, or if less solder 72 is needed on the leads 64, the package should not be dipped or wave soldered as deeply. In other words, adjustments may be made to the solder application step quickly and easily. In addition, burn-in can be performed between the step of solder plating of the entire lead 64 to form non-wettable upper region 66 and a solder dipping step to form wettable area 68 in order to minimize lead surface oxidation.
Shown in FIG. 6 is an alternate embodiment of the invention in the form of PLCC 76 having a package body 78 bearing an integrated circuit chip 80, from which a plurality of exterior J-leads 82 depend. The upper non-solder-wettable surface of the J-leads 82 is provided by a non-solder-wettable coating 84 which as illustrated also covers part of the package body 78. The coating 84 may be of any suitable material as long as it adheres to the package body 78 and exterior leads 82 and is solder-phobic. Any of a number of chemical coating substances would be suitable, and an example of a suitable material is an ultraviolet (UV) light-curable polymer plastic. The coating 84 may be applied simply by inverting the PLCC 76 and dipping it top down into the liquid chemical and then curing the chemical by the appropriate mechanism. It may be readily seen that coating 84, not being solder-wettable, will effectively prevent solder from wicking up lead 82 in a solder reflow operation.
Coating 84 provides the additional advantage of sealing any stress cracks 86 that may be present at the point the J-leads 82 project from the package body 78, which is a common problem with PLCCs. Stress cracks 86 are undesirable because they provide a means whereby moisture and other contaminants may enter package body 78 and damage chip 80.
As in the other embodiments of the invention, exterior leads 82 have a lower solder coated portion 88 which is positioned over bonding pad 90 of substrate 92 and processed through a reflow operation to form solder bonds 94 as described previously.
FIG. 7 illustrates still another form of the invention; in this case a DIP 96 having a package body 98sand a plurality of exterior butt joint leads 100 designed to correspond with the bonding pads 102 on substrate 104. As in the case of the PLCC 76 of FIG. 6, a coating 106 is present to provide the upper non-wettable surface to exterior leads 100. However, in this case, package body 98 is entirely sealed in coating 106 to provide further protection to the package body 98 and the integrated circuit therein. Of course, the DIP 96 additionally has the characteristics of the PLCC 76 of FIG. 6, including the sealing of any microcracks that may be present.

Claims

I Claim:
1. A surface mountable integrated circuit package comprising a package body and a plurality of exterior leads extending therefrom, wherein the leads have proximal ends adjacent to the package body and distal ends away from the package body and in which only the proximal ends of the exterior leads adjacent the package body are provided with a non-solder-wettable surface.
2. The surface mountable integrated circuit package of claim 1 in which the non-solder-wettable surface is a surface provided with a lead-heavy formulation having a lead to tin ration of at least 90/10.
3. The surface mountable integrated circuit package of claim 1 in which the non-solder-wettable surface is a coating covering the exterior leads as they project from the package body as well as only the proximal ends of the exterior leads.
4. The surface mountable integrated circuit package of claim 3 in which the coating is an ultraviolet curable plastic.
5. A surface mountable integrated circuit package comprising a package body and a plurality of exterior leads depending therefrom, wherein the leads have upper portions adjacent to the package body and lower portions away from the package body in which only the upper portions "of the exterior leads adjacent the package body are provided with a non-solder-wettable surface, wherein the non-solder-wettable surface is different from the package body. . 5 in which the non-solder-wettable surface is a surface provided with a lead-heavy formulation having a lead to tin ratio of at least 90/10.
7. The surface mountable integrated circuit package of claim 5 in which the non-solder-wettable surface is a coating covering the exterior leads as they project from the package body as well as only an upper portion of the exterior leads.
8. A surface mountable integrated circuit package comprising a package body and a plurality of exterior leads extending therefrom, each lead having a proximal end connected to the package body and a distal end to be surface mounted to a substrate and a solder-σoatable surface on only the distal ends thereof.
9. The surface mountable integrated circuit package of claim 8 in which the- proximal ends of the exterior leads are provided with a non-wettable surface different from the package body and the distal ends of the exterior leads are provided with a solder coated surface by a process selected from the group consisting of wave soldering, solder paste dipping and molten solder dipping.
10. The surface mountable integrated circuit package of claim 8 in which the proximal ends of the exterior leads are provided with a non-wettable solder surface having a lead to tin ratio of at least 90/10 and in which the distal ends of the exterior leads are provided with a solder coated surface having a lead to tin ratio of less than or equal to 63/37.
EP86905650A 1985-12-18 1986-09-15 Lead finishing for a surface mount package Withdrawn EP0250450A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81045285A 1985-12-18 1985-12-18
US810452 2004-03-26

Publications (1)

Publication Number Publication Date
EP0250450A1 true EP0250450A1 (en) 1988-01-07

Family

ID=25203876

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86905650A Withdrawn EP0250450A1 (en) 1985-12-18 1986-09-15 Lead finishing for a surface mount package

Country Status (2)

Country Link
EP (1) EP0250450A1 (en)
WO (1) WO1987004008A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE1007856A3 (en) * 1993-12-06 1995-11-07 Philips Electronics Nv COMPOSITION OF A PCB AND AT LEAST A COMPONENT AND METHOD FOR ATTACHING A COMPONENT TO A PCB.
US5844308A (en) * 1997-08-20 1998-12-01 Cts Corporation Integrated circuit anti-bridging leads design
JPH11317326A (en) * 1998-03-06 1999-11-16 Rohm Co Ltd Electronic component
US6378758B1 (en) * 1999-01-19 2002-04-30 Tessera, Inc. Conductive leads with non-wettable surfaces
US7696611B2 (en) * 2004-01-13 2010-04-13 Halliburton Energy Services, Inc. Conductive material compositions, apparatus, systems, and methods
US7419084B2 (en) * 2004-11-24 2008-09-02 Xerox Corporation Mounting method for surface-mount components on a printed circuit board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132856A (en) * 1977-11-28 1979-01-02 Burroughs Corporation Process of forming a plastic encapsulated molded film carrier CML package and the package formed thereby
US4147889A (en) * 1978-02-28 1979-04-03 Amp Incorporated Chip carrier

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8704008A1 *

Also Published As

Publication number Publication date
WO1987004008A1 (en) 1987-07-02

Similar Documents

Publication Publication Date Title
US20020185304A1 (en) Method of packaging electronic components with high reliability
KR100338167B1 (en) Electrical contactor and its manufacturing method
EP0250450A1 (en) Lead finishing for a surface mount package
US4708885A (en) Manufacturing method for an electronic component
DE19611407B4 (en) Semiconductor device and method for its production
US20020179323A1 (en) Structure comprising a printed circuit board with electronic components mounted thereon and a method for manufacturing the same
CN101553091B (en) Printed circuit board and process for promoting qualification rate of lead-free process
JPH0331785B2 (en)
US8159826B2 (en) Surface treatments for contact pads used in semiconductor chip packagages and methods of providing such surface treatments
JPH03185754A (en) Semiconductor device
JPH03241813A (en) Method of covering chip type electronic part
JPH0760881B2 (en) Solder application method for semiconductor devices
US6924440B2 (en) Printed wiring board, apparatus for electrically connecting an electronic element and a substrate, and method for manufacturing a printed wiring board
JPH0445273Y2 (en)
JPH04137657A (en) Hybrid integrated circuit board
JPH03220792A (en) Mounting structure of pga-type integrated circuit
JP2836887B2 (en) How to mount surface mount chip components
JPH0714970A (en) Semiconductor device and its mounting method
JPS6223136A (en) Semiconductor device
JPH05251607A (en) Jig for plating outer lead of semiconductor device and plating method using said jig
JPS5947749A (en) Resin package type semiconductor device
JPH01218092A (en) Manufacture of printed wiring board
JPH02113592A (en) Manufacture of circuit board
JPS61220447A (en) Semiconductor package
JPH01110754A (en) Resin-sealed semiconductor integrated circuit device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT NL

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19870921

RIN1 Information on inventor provided before grant (corrected)

Inventor name: LIN, PAUL, T.