JPH03241813A - Method of covering chip type electronic part - Google Patents

Method of covering chip type electronic part

Info

Publication number
JPH03241813A
JPH03241813A JP2038673A JP3867390A JPH03241813A JP H03241813 A JPH03241813 A JP H03241813A JP 2038673 A JP2038673 A JP 2038673A JP 3867390 A JP3867390 A JP 3867390A JP H03241813 A JPH03241813 A JP H03241813A
Authority
JP
Japan
Prior art keywords
resin
chip
type electronic
coated
liquid resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2038673A
Other languages
Japanese (ja)
Inventor
Hisaaki Tachihara
久明 立原
Kazuhiko Nasu
那須 和彦
Kunio Oshima
大嶋 邦雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2038673A priority Critical patent/JPH03241813A/en
Publication of JPH03241813A publication Critical patent/JPH03241813A/en
Pending legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To prevent generation of a short-circuit by soldering even when a high density surface packaging operation is conducted by a method wherein, after liquid resin has been transfer-coated on both cut surfaces of an element formed by conducting a cutting work, the above-mentioned liquid resin is hardened. CONSTITUTION:After the process of formation of an electrode 2 on a base element has been finished, a process of formation of individual element 1 by cutting the base element 1 is conducted, and after both cut surfaces 4 of the element 2, formed by the above-mentioned process, are transfer coated with liquid resin 9 using a gravure roller 8, and then a process of hardening the above-mentioned liquid resin 9 is performed. For example, ultraviolet-ray-hardening resin 9a is carried on the gravure roller 8 by a lifting up roller and an intermediate transfer roller 6, and the excessive resin 9b, which does not go into the printing plate 3 of the gravure roller 8, is scraped off by a doctor blade 5, and the resin 9a is coated on the cut surface 4 only of the capacitor element 1. The coated ultraviolet-ray-hardening resin 9c is hardened by the irradiation of ultraviolet rays emitted from an ultraviolet ray lamp 10, and the resin 9c is thermoset further by a thermostatic vessel and the like as necessary.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、積層型フ4)Vムコンデンサ等のチップ型電
子部品の外装方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for packaging chip-type electronic components such as multilayer film capacitors.

従来の技術 チップ型電子部品は、プリント基板に直接端子を半田付
けされ、かつ非常に小型であるために電子回路の高集積
化設計に適している。チップ型電子部品の外装としては
樹脂モールド型のタイプと、樹脂塗膜で被覆したタイプ
釦よび無外装タイプのものがある。
Conventional chip-type electronic components have terminals soldered directly to printed circuit boards and are extremely small, making them suitable for highly integrated designs of electronic circuits. The exterior of chip-type electronic components includes a resin mold type, a button type covered with a resin coating, and a type without exterior.

また、電極の形状については、第5図に示すような、例
えばチップ型積層セラミックコンテ゛ンサやチップ型抵
抗器釦よびチップ型積層フィルムコンデンサでは、素子
11の両端の電極2が素子端面だけではなく、素子端面
近傍の上下面及び左右面(側面)にも形成されている。
Regarding the shape of the electrodes, for example, in chip-type multilayer ceramic capacitors, chip-type resistor buttons, and chip-type multilayer film capacitors as shown in FIG. They are also formed on the upper and lower surfaces and the left and right surfaces (side surfaces) near the end faces of the element.

樹脂モールド型のタイプは、電極がリードフレームによ
り形成されているので、素子13の両端の電極2は素子
端面と素子端面近傍の下面にのみ形成されている。
In the resin mold type, the electrodes are formed by a lead frame, so the electrodes 2 at both ends of the element 13 are formed only on the element end face and the lower face near the element end face.

この状態をミンクlし電解コンデンサを例にとって第6
図に示す。
Let's consider this state and take an electrolytic capacitor as an example.
As shown in the figure.

発明が解決しようとする課題 チップ型電子部品はフロー法、リフロー法等により半田
付け(表面実装)されているが、近年、高集積化される
につれて半田付けが難しくなってきている。すなわち、
回路パターンが微細になってきているために、半田付け
する際に余分な半田が不必要な部分に付着して、短絡不
良が発生しやすいという課題かある。
Problems to be Solved by the Invention Chip-type electronic components are soldered (surface mounted) by a flow method, a reflow method, etc., but in recent years, soldering has become more difficult as the degree of integration has increased. That is,
As circuit patterns become finer, there is a problem in that when soldering, excess solder adheres to unnecessary parts, making short circuits more likely to occur.

この課題は、チップ型積層セラミンクコンデンサやチッ
プ型抵抗器およびチップ型積層フィルムコンテ゛ンサの
ように電極が素子端面だけではなく、素子端面近傍の上
下面及び左右面(側面)にも形成されているタイプの電
子部品では、特に発生しやすい。
This problem arises in chip-type multilayer ceramic capacitors, chip-type resistors, and chip-type multilayer film capacitors in which electrodes are formed not only on the element end face, but also on the top, bottom, left and right (side) faces near the element end face. This is particularly likely to occur with electronic components of this type.

この課題について図面を用いて説明する。第7図a、b
において、11//i従来の積層セラミックコンデンサ
、12Fi基板上に形成されているランド(銅箔製)で
ある。説明のためランドの幅を素子幅と同じとする。第
7図乙のように高密度でない場合は、余分な半田が残っ
たとしても素子間の間隔が広いので短絡しないが、第9
図すのように高密度の場合は、余分の半EIllIが素
子側面の電極の半田濡れ性によってつな7′l;って短
絡しやすい。
This problem will be explained using drawings. Figure 7 a, b
11//i is a conventional multilayer ceramic capacitor with a land (made of copper foil) formed on a 12Fi substrate. For the sake of explanation, the width of the land is assumed to be the same as the element width. If the density is not as high as in Figure 7 B, even if excess solder remains, there will be no short circuit because the spacing between the elements is wide.
In the case of high density as shown in the figure, the extra half EIllI is likely to be connected by the solder wettability of the electrode on the side of the element, resulting in a short circuit.

本発明の目的は、高密度に表面実装した場合でも、半田
による短絡のないチップ型電子部品の外装方法を提供す
ることにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a packaging method for chip-type electronic components that does not cause short circuits due to solder even when surface-mounted at high density.

課題を解決するための手段 上記課題を解決するために本発明のチップ型電子部品の
外装方法は、母素子に電極を形成する工程の後に母素子
を切断して個別の素子とする工程と、前記切断工程によ
り形成される素子の両切断面にのみ液状樹脂をグラビア
ローラを用いて、転写塗布した後に、前記液状樹脂を硬
化する工程を含むことを特徴とする。
Means for Solving the Problems In order to solve the above problems, the method for packaging a chip-type electronic component of the present invention includes the steps of: forming electrodes on the mother element, and then cutting the mother element into individual elements; The present invention is characterized in that it includes a step of applying a liquid resin only to both cut surfaces of the element formed by the cutting step using a gravure roller, and then curing the liquid resin.

作用 本発明の外装方法により、電極の素子側面部は樹脂によ
り被覆されるので、半田付は時に電極の素子側面部に半
田が付着したう、素子側面部に半田を呼び込むことがな
いので、短絡不良となることがない。したがって高密度
の表面実装に対応できるチップ型電子部品を実現するこ
とができる。
Function: With the packaging method of the present invention, the side surface of the element of the electrode is coated with resin, so solder sometimes adheres to the side surface of the element of the electrode, and solder is not drawn into the side surface of the element, thereby preventing short circuits. It never becomes defective. Therefore, it is possible to realize a chip-type electronic component that is compatible with high-density surface mounting.

実施例 以下、本発明の実施例について図面を参照しな25;ら
説明する。
EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

本発明の一実施例として、チップ型積層フィルムコンデ
ンサについて説明する。積層フィルムコンデンサはその
製造工程に訃いて第3図に示すように、母素子14を切
断刃15により切断して個別のコンデンサ素子を形成す
る。切断により形成された切断面4は、電極端面が露出
しているので、コンデンサ特性を劣下させないように樹
脂等で外装される。
As an example of the present invention, a chip-type multilayer film capacitor will be described. According to the manufacturing process of the laminated film capacitor, as shown in FIG. 3, a mother element 14 is cut by a cutting blade 15 to form individual capacitor elements. The cut surface 4 formed by cutting has the electrode end surface exposed, so it is covered with resin or the like so as not to deteriorate the capacitor characteristics.

第1図は、チップ型積層フィルムコンデンサの切断面に
紫外線硬化樹脂を用いて外装する工程の一例を示す斜視
図である。第1図において、1は積層フィルムコンデン
サ素子、2はコンテ′ンサの電極引き出し端面に、金属
溶射法により形成された後、半田めっきを施してなる電
極である。積層フィルムコンデンサ素子の切断面4の上
に、グラビアローラ8を用いて紫外線硬化樹脂9cを所
定の厚さに塗布する。
FIG. 1 is a perspective view showing an example of a step of packaging a cut surface of a chip-type multilayer film capacitor with an ultraviolet curing resin. In FIG. 1, reference numeral 1 indicates a laminated film capacitor element, and reference numeral 2 indicates an electrode formed by metal spraying and solder plating on the electrode extension end face of the capacitor. An ultraviolet curable resin 9c is applied to a predetermined thickness on the cut surface 4 of the laminated film capacitor element using a gravure roller 8.

ここで、紫外線硬化樹脂9aばかき上げローラ7と中間
転写ローラ6によってグラビアローラ8上に運ばれ、グ
ラビアの版目3に入らない余分な樹脂9bはドクターブ
レード5によってかき落とされる。第2図に示すように
グラビアローラ8の版目でない部分には樹脂が付着して
いないので、樹脂はコンデンサ素子の切断面にのみ塗布
され、電極端面(第4図中矢印ム、A′によシ示す面)
にははみ出さない。電極端面に樹脂がはみ出さないこと
は、!極面積を損失せず、半田付は性を確保するために
重要な要件である。
Here, the ultraviolet curing resin 9a is carried onto the gravure roller 8 by the scraping roller 7 and the intermediate transfer roller 6, and the excess resin 9b that does not fit into the gravure plate 3 is scraped off by the doctor blade 5. As shown in FIG. 2, since the resin is not attached to the non-plate portion of the gravure roller 8, the resin is applied only to the cut surface of the capacitor element, and the electrode end surface (arrow A' in FIG. 4) is coated only on the cut surface of the capacitor element. side)
It doesn't stick out. Ensure that the resin does not protrude from the electrode end surface! Soldering without loss of polar area is an important requirement to ensure properties.

樹脂塗布方法を種々検討の結果、グラビアローラによる
塗布がこの点にふ・いて最も優れており、さらに樹脂粘
度、樹脂温度、塗布速度等を一定にすれば、樹脂の厚さ
を再現性良く一定にすることができる。
As a result of examining various resin application methods, we found that application using a gravure roller is the best in this respect, and furthermore, by keeping the resin viscosity, resin temperature, application speed, etc. constant, the resin thickness can be maintained at a constant level with good reproducibility. It can be done.

塗布された紫外線硬化樹脂9Cは紫外線ランプ10によ
って紫外線を照射して硬化し、必要に応じて恒温槽など
で熱硬化する。
The applied ultraviolet curable resin 9C is cured by irradiating ultraviolet rays with an ultraviolet lamp 10, and if necessary is thermally cured in a constant temperature bath or the like.

このようにして得られた太発明のチップ型積層フィルム
コンデンサId、第4図に示すように切断面4が樹脂9
により外装されてフ・す、かつ切断面と同一面内にある
電極の側面(第6図B、B’で示す。)にも外装が施さ
れているが、電極端面(第6図A、ム′で示す。)Ki
d樹脂がはみ出していない。
As shown in FIG.
The sides of the electrode (shown as B and B' in Figure 6) that are in the same plane as the cut surface are also coated, but the end faces of the electrode (shown as A and B' in Figure 6) are also coated. ) Ki
dResin is not protruding.

太発明のチップ型積層フィルムコンデンサ100個を、
側面の間隔が0.6Hになるように1列に10個ずつ、
10列に基板に並べて、フロー法により半田付けした。
100 chip-type multilayer film capacitors invented by Tai
10 pieces in each row so that the side spacing is 0.6H,
They were arranged in 10 rows on a board and soldered using the flow method.

なお、ランドの幅は素子の幅と同一にした。比較例とし
て前記の樹脂外装を施していないチップ型積層フィルム
コンデンサを同時に半田付けした。半田付は後の状態を
観察すると、比較例では、第7図aに示すような短絡が
7箇所見られたが、太発明のコンデンサ素子では1つも
発生しなかった。
Note that the width of the land was made the same as the width of the element. As a comparative example, a chip-type multilayer film capacitor without the above-mentioned resin exterior was soldered at the same time. When observing the state after soldering, seven short circuits as shown in FIG. 7a were observed in the comparative example, but none occurred in the capacitor element of the invention.

以上のように本発明のアイlレムコンデンサは、隣接す
る素子の電樺間で半田による短絡が生じにくいので、コ
ンデンサ素子の側面の間隔をつめて高密度の表面実装を
することができる。
As described above, in the Il-Rem capacitor of the present invention, short circuits due to solder do not easily occur between the wires of adjacent elements, so that high-density surface mounting can be performed by narrowing the spacing between the sides of the capacitor elements.

なお、前記実施例ではフィNムコンデンサの例を示した
が、本発明はこれに限るものではなく、tiが素子端面
だけではなく、素子端面近傍の上下面及び左右面(側面
)にも形成されているチップ51Jitセラミツクコン
デンサやチップ型抵抗などにも適用できる。筐た外装樹
脂も実施例に限るものではなく、熱硬化型の樹脂等、電
子部品の外装に一般的に用いられる液状の樹脂であれば
用いることができる。また、電極表面の金属も半田に限
るものではなく、半田付は性を向上させることが期待で
きる。例えば錫を含む金属で被覆されていれば本発明の
目的にかなう。
In addition, although the example of the film capacitor was shown in the above embodiment, the present invention is not limited to this, and ti may be formed not only on the element end face but also on the upper and lower surfaces and left and right surfaces (side surfaces) near the element end face. It can also be applied to chip 51Jit ceramic capacitors and chip type resistors. The exterior resin of the casing is not limited to the embodiments, and any liquid resin commonly used for the exterior of electronic components, such as thermosetting resin, can be used. Furthermore, the metal on the electrode surface is not limited to solder, and soldering can be expected to improve properties. For example, the object of the present invention can be achieved if it is coated with a metal containing tin.

発明の効果 以上のように本発明の外装方法によれば、チップ型の電
子部品の電極を短絡させることなく、高密度で表面実装
可能なチップ型電子部品を実現することができる。
Effects of the Invention As described above, according to the packaging method of the present invention, a chip-type electronic component that can be surface-mounted at high density can be realized without short-circuiting the electrodes of the chip-type electronic component.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のチップ型積層フィルムコン
デンサの切断面に紫外線硬化樹脂を用いて外装する工程
の一例を示す斜視図、第2図は同工程での要部上面図、
第3図は積層フィルムコンデンサの切断工程を示す斜視
図、第4図は本発明の外装方法による積層フィ〃ムコン
デンサの外観斜視図、第6図、第6図は従来のチップ型
コンデンサの外観斜視図、第7因a、bFiチツプ型コ
ンデンサの表面実装後の状態を示す斜視図である。 1・・・・・・チップ型積層フィルムコンデンサ、2・
・・・・−電極、3・・・・・・グラビアローラの版目
、4・・・・・・切断面%5・・・・・・ドクターブレ
ード、6・・・・・・中間ローラ、T・・・・・・かき
あげローラ、8・・・・・・クラビアローラ、9・・・
・・・外装樹脂、sa、sb、sc・・・・・・紫外線
硬化樹脂、10・・・・・・紫外線ランプ。 子ラブ型!l壜フィルム コンナンす 第 5 第 図 図 第 図 // /2
FIG. 1 is a perspective view showing an example of the step of sheathing the cut surface of a chip-type multilayer film capacitor according to an embodiment of the present invention using an ultraviolet curable resin, and FIG. 2 is a top view of essential parts in the same step.
Fig. 3 is a perspective view showing the cutting process of a multilayer film capacitor, Fig. 4 is an external perspective view of a multilayer film capacitor manufactured by the packaging method of the present invention, and Fig. 6 is an external appearance of a conventional chip type capacitor. FIG. 7 is a perspective view showing a state of a seventh factor a, bFi chip type capacitor after surface mounting. 1... Chip type multilayer film capacitor, 2.
・・・・Electrode, 3・・・・・・Gravure roller plate number, 4・・・・・・Cut surface % 5・・・Doctor blade, 6・・・・・・Intermediate roller, T...Kakiage roller, 8...Claviar roller, 9...
...Exterior resin, SA, SB, SC...UV curing resin, 10...UV lamp. Child love type! L Bottle Film Container No. 5 Figure Figure Figure // /2

Claims (4)

【特許請求の範囲】[Claims] (1)母素子に電極を形成する工程の後に、母素子を切
断して個別の素子とする工程と、前記切断工程により形
成される素子の両切断面にのみ液状樹脂をグラビアロー
ラを用いて転写塗布した後に、前記液状樹脂を硬化する
工程を含むことを特徴とするチップ型電子部品の外装方
法。
(1) After the step of forming electrodes on the mother element, there is a step of cutting the mother element into individual elements, and using a gravure roller to apply liquid resin only to both cut surfaces of the element formed in the cutting step. A method for packaging a chip-type electronic component, comprising the step of curing the liquid resin after transfer coating.
(2)素子の切断面に樹脂を塗布する工程で、グラビア
ローラ上に液状樹脂を塗布し、前記グラビアローラの版
目に入らない余分の樹脂をドクターブレードによりかき
落とした後、前記素子切断面に転写塗布することを特徴
とする請求項1に記載のチップ型電子部品の外装方法。
(2) In the process of applying resin to the cut surface of the element, liquid resin is applied onto the gravure roller, and after scraping off the excess resin that does not enter the plate of the gravure roller with a doctor blade, the resin is applied to the cut surface of the element. 2. The method for packaging a chip-type electronic component according to claim 1, wherein transfer coating is performed.
(3)素子の切断面に塗布された樹脂を紫外線により硬
化することを特徴とする請求項1に記載のチップ型電子
部品の外装方法。
(3) The method for packaging a chip-type electronic component according to claim 1, characterized in that the resin applied to the cut surface of the element is cured by ultraviolet rays.
(4)素子としての積層型フィルムコンデンサの電極の
下地層が金属溶射法により形成され、かつ電極表面が半
田もしくは少なくともすずを含む金属で被覆されている
ことを特徴とする請求項1に記載のチップ型電子部品の
外装方法。
(4) The base layer of the electrode of the multilayer film capacitor as an element is formed by a metal spraying method, and the electrode surface is coated with solder or a metal containing at least tin. Exterior packaging method for chip-type electronic components.
JP2038673A 1990-02-20 1990-02-20 Method of covering chip type electronic part Pending JPH03241813A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2038673A JPH03241813A (en) 1990-02-20 1990-02-20 Method of covering chip type electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2038673A JPH03241813A (en) 1990-02-20 1990-02-20 Method of covering chip type electronic part

Publications (1)

Publication Number Publication Date
JPH03241813A true JPH03241813A (en) 1991-10-29

Family

ID=12531795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2038673A Pending JPH03241813A (en) 1990-02-20 1990-02-20 Method of covering chip type electronic part

Country Status (1)

Country Link
JP (1) JPH03241813A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8773839B2 (en) 2009-12-11 2014-07-08 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component
US8773840B2 (en) 2009-12-11 2014-07-08 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component
WO2014178134A1 (en) * 2013-05-01 2014-11-06 小島プレス工業株式会社 Film capacitor
US9082556B2 (en) 2009-12-11 2015-07-14 Murata Manufacturing Co., Ltd. Monolithic ceramic capacitor
US9245688B2 (en) 2009-12-11 2016-01-26 Murata Manufacturing Co., Ltd. Monolithic ceramic capacitor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180114A (en) * 1981-04-30 1982-11-06 Nissei Electric Method of producing film condenser
JPS6477912A (en) * 1987-09-18 1989-03-23 Matsushita Electric Ind Co Ltd Capacitor
JPH01173614A (en) * 1987-12-28 1989-07-10 Nitsuko Corp Manufacture of chip-type film capacitor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180114A (en) * 1981-04-30 1982-11-06 Nissei Electric Method of producing film condenser
JPS6477912A (en) * 1987-09-18 1989-03-23 Matsushita Electric Ind Co Ltd Capacitor
JPH01173614A (en) * 1987-12-28 1989-07-10 Nitsuko Corp Manufacture of chip-type film capacitor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8773839B2 (en) 2009-12-11 2014-07-08 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component
US8773840B2 (en) 2009-12-11 2014-07-08 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component
US9082556B2 (en) 2009-12-11 2015-07-14 Murata Manufacturing Co., Ltd. Monolithic ceramic capacitor
US9245688B2 (en) 2009-12-11 2016-01-26 Murata Manufacturing Co., Ltd. Monolithic ceramic capacitor
WO2014178134A1 (en) * 2013-05-01 2014-11-06 小島プレス工業株式会社 Film capacitor
JP5990325B2 (en) * 2013-05-01 2016-09-14 小島プレス工業株式会社 Film capacitor
US9666368B2 (en) 2013-05-01 2017-05-30 Kojima Industries Corporation Film capacitor

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