Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
  • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
  • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator

Definitions

• the devices may be processors or peripheral devices.
• the invention also relates to video display apparatus, more specifically apparatus for generating a video signal for a raster-scan display.
• Priority resolution systems of the above kind are known and examples are described in "Introduction to a Simple but Unconventional Multiprocessor System and Outline of an Application", Rolf Linder, Technische Hochhoff Darmstadt, Presented at the NATO Advanced Study Institute on Computer Architectures for Spatially Distributed Data, Cetraro, Italy, June 83. and in published application GB 2 143 349. GB 2 143 349 explains how the priority numbers may be assigned dynamically so as to achieve desired allocation of a shared resource or determination as to which of a plurality of processors provides image data in a situation where images can overlay each other.
• Each device has priority logic with wired - AND (open collector) connections to the bus lines to pull down bus lines.
• the logic is such that the device providing the most significant "1" bit in its priority number wins and is granted access to a data bus (maximum priority resolution).
• the system described in GB 2 143 349 is moreover pipelined so that bit-wise comparisons ripple through the logic.
• the performance of these systems is dependant on the number of devices which are connected.
• the maximum clock speed decreases as the physical size of priority and data buses increases because a longer settling time is required.
• the total number of contending processors (or devices) is limited by the electrical loading on the wired -OR lines of the priority bus.
• An object of the present invention is to provide a system which does not suffer from these problems and which can be used at very high clock rates, e.g. a pixel clock rate of 160 MHz or greater. It is a further object to provide a system which places no limit on the number of devices which may be incorporated and in which the maximum usable clock rate is not affected by the number of devices (although latency is increased as devices are added).
• the priority resolution system according to the invention is defined in claim 1 below and advantageous developments are defined in the claims dependent on claim 1.
• priority resolution is in relation to computer generated image systems, in which case priority values correspond to z-values, i.e. values of the depth coordinate.
• z-values i.e. values of the depth coordinate.
• higher priority images are required to overlay lower priority images.
• Various approaches are known but all are relatively complex. It is necessary to be able to make the resolution on a pixel by pixel basis. Many systems use a frame buffer and sort the image data into the frame buffer. Sorting is notoriously difficult to implement quickly. The z-buffer algorithm is simpler but requires a large z-buffer to store a z-value for every pixel. Systems as described in GB 2 143 349 and also in GB 1 532 275 which rely on real-time selection of the highest priority device suffer from the kind of problems discussed above in relation to the priority resolution process.
• Fig. 1 is a block diagram of a system embodying the invention
• Fig. 2 is a block diagram of the priority logic associated with one device
• Figs. 3 and 4 are tables illustrating the operation of Fig. 2;
• Fig. 5 is a diagram illustrating pipelined operation.
• the system illustrated in Fig. 1 comprises an ordered plurality of devices such as microprocessors P 1 , p 2 etc. up to P n . n must be at least 2 and may well be substantially larger than 2.
• the processors operate synchronously with respect to video sync signals for a raster scan display; these signals are passed from processor to processor on a line S.
• Each processor outputs video signals on a corresponding port V 1 to V n shown as comprising three lines to cater for R, G and B signals, although the number of lines is not important to the present invention; only one is needed for a monochrome display.
• the video lines do not necessarily carry signals which determine colour directly. It is well known to translate the video signals on a plurality of lines by use of a colour look-up table.
• the nature of the devices P 1 to P n is not important. They may generate their video signals from bit-plane buffers or by real-time scan conversion, for example.
• the video signals are fed to respective pixel insertion circuits M 1 to M n , which are essentially two-input, three channel multiplexers through which a video bus X 1 to X n is chained.
• Each multiplexer outputs whatever it receives on the bus X 1 to X n when a corresponding selection signal D 1 to D n has a first logic state and outputs what it receives on the corresponding port V 1 to V n when its selection signal has the other logic state.
• the complete image is thus built up from the signals provided from the processors p 1 to P n and the signals from higher order processors may overlay the signals from lower order processors.
• the invention is concerned in part with the way in which the selection signals D 1 to D n are provided by priority logic units L 1 to L n associated with the processors P 1 to P n . These units are chained by an m-bit priority bus A 1 , A 2 ... A n where m is large enough to select between the number of processors involved, i.e. the minimum value of m is given by the relation n ⁇ 2m ⁇ 2n.
• Each of the priority logic units also receives a corresponding m-bit input B 1 to B n which is the corresponding device's priority number. These numbers may emanate from the devices P 1 to P n themselves or may be assigned by a common priority allocation unit, as in GB 2 143 349.
• the indexes 1 to n pertain to the processors P 1 to P n and associated entities. If the index i is used for the general case, the properties of each priority logic unit L 1 to L n may be described as follows. A unit L i compares A i and B i in bit-wise fashion, working from the most significant to the least significant bit. The first mis-match indicates whether the bus number A i or the device number B i indicates the higher priority. D i is set accordingly and A i+1 becomes whichever of A i and B i indicates the higher priority.
• the first priority logic unit L 1 is shown receiving A 1 and B 1 .
• a 1 may be set to a minimum priority value to provide a threshold below which a processor cannot be selected. More likely, A 1 will be set to all zeroes (maximum priority resolution) or to all ones (minimum priority resolution) so that A 2 always equals B 1 and D 1 always effects selection.
• the same result can be achieved by omitting the unit L 1 , connecting B 1 directly to A 2 and wiring D 1 to effect selection. Going further it is also possible to omit the pixel insertion multiplexer M 1 and connect V 1 to X 2 .
• M 1 may be provided to cater for a case in which there is already video information on X 1 , provided by a separate system.
• a i a 1 ... a j ... a m
• Each priority logic unit (Fig. 2) comprises m bit logic units T 1 to T m .
• T j receives the bits a j and b j and outputs z j .
• the unit T j also receives inputs c j- 1 and d j-1 from the next more significant unit T j-1 and outputs c j and d j to the next less significant unit.
• the signal c j indicates whether or not priority has been resolved at the unit T j or at a unit of higher significance and d j indicates, when priority has been resolved, in whose favour.
• the final bit d m constitutes the selection signal D i . z j becomes a j for the next priority logic unit.
• c j c j-1 + (a j b j ) (1)
• d j c j-1 .d j-1 + a j .
• z j a j .b j + c j-1 .(b j .d j-1 + a j .
• Fig. 3 tabulates all possible combinations of the input quantities a j , b j , C j-1 and d j- 1 and the resultant output quantities c j , d j and z j .
• the bracketed values for d j are the values arising from equation (2) although they are actually "don't care" values.
• c o can be tied to logical 0.
• the processor could be given control over both c o and d o to allow it to effect forced selection, overriding the priority contest.
• d o is tied to 0 and c o is provided as an ACTIVE signal which is logical 1 only during that part of each scanline traversing an object processed by the processor in question.
• each processor is prevented from attempting to contribute to the signals on the video bus except in areas which contain image data so far as that processor is concerned.
• Fig. 4 is the corresponding table of input and output quantities.
• each priority logic unit produces its output virtually instantaneously (subject only to the gate delays in rippling through the bit logic units). This may be a practical implementation for some applications but an important development of the invention allows pipelined operation.
• Every bit logic unit is provided with latches (not shown) for all its output quantities z j , c j and d j .
• These latches are clocked by a bit-rate clock CK (Fig. 2) so that, if resolution of the most significant bits a o , b o is effected in one clock cycle, a 1 and b 1 will be resolved in the next clock cycle and so on.
• k i1 means a first bus priority number handled by a unit L i
• a i2 means the next bus priority number handled by L i
• a i3 means a third bus priority number handled by L i .
• a device priority number B i when a device priority number B i is changed it should either be changed during an inactive phase of the system (e.g. during the field blanking interval in a computer graphics application) or be changed bit by bit over m clock cycles, starting with the most significant bit.
• the maximum clock speed of the system does not depend upon the number of devices P 1 to P n .
• Each priority logic unit L i merely has to drive lines long enough to carry the bus priority number to the next unit.
• the invention may be used in many applications, including priority resolution in computer generated image systems, including object-based systems. Other applications are to priority resolution between contending processes in computer systems and to data transfer between processors in multiprocessor systems.
• the circuitry may also be used to resolve number comparisons for numbers other than priority numbers, i.e. as a pipelined hardware comparator.
• the pipelined nature of the system means that it does not select just one device with highest priority. Selection is a progressive process along the pipeline and a device is selected if it has higher priority than the bus priority at that point along the pipeline. This form of priority resolution is particularly suited to image overlay processes. It is not applicable when solely the highest priority device is to be selected.
• the assigned priority numbers may be such that equal priority situations are never encountered. If they can arise, the logic must be designed to give the required resolution. Reverting to
• Simple additional logic can be used to force D i to whichever state is desired when c m is false.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Human Computer Interaction (AREA)
• Image Processing (AREA)

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• 1985
  • 1985-07-18 GB GB8518130A patent/GB2180125B/en not_active Expired
• 1986
  • 1986-07-18 EP EP19860904306 patent/EP0231240A1/de active Pending
  • 1986-07-18 WO PCT/GB1986/000422 patent/WO1987000658A1/en unknown

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