GB2180125A - Priority resolution system and video display apparatus - Google Patents
Priority resolution system and video display apparatus Download PDFInfo
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- GB2180125A GB2180125A GB08518130A GB8518130A GB2180125A GB 2180125 A GB2180125 A GB 2180125A GB 08518130 A GB08518130 A GB 08518130A GB 8518130 A GB8518130 A GB 8518130A GB 2180125 A GB2180125 A GB 2180125A
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- resolution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
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- General Engineering & Computer Science (AREA)
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Abstract
Devices (processors) P1 to Pn provide device priority numbers B1 to Bn to corresponding priority logic units L1 to Ln through which a bus priority number is relayed on an m-bit priority bus A1 to An. Each priority logic unit (e.g. L1) effects pipelines bit-wise comparison between its input numbers A1 and B1 (in order of decreasing significance) and outputs as the bus number A2 whichever of A1 and B1 indicates higher priority. Moreover a selection signal D1 is output to indicate when B1 has higher priority than A1. The selection signals D1 to Dn selectively enable outputs V1 to Vn from the processors into a video bus X1 to Xn+1 in the illustrated application.
Description
SPECIFICATION
Priority resolution system and video display apparatus
The present invention relates to a priority resolution system for a plurality of devices to which priority numbers are assigned for determination of priorities in accordance with the rule higher number = higher priority (maximum priority resolution) orthe rule lower number = higher priority (minimum priority resolution). The devices may be processors or peripheral devices. The invention also relates to a video display apparatus, more specifically apparatus for generating a video signal for a raster-scan display.
Priority resolution systems of the above kind are known and examples are described in "Introduction to a
Simple but Unconventional Multiprocessor System and Outline of an Application", Rolf Linder, Tech nische Hochschule Darmstadt, Presented at the NATO Advanced Study Institute on ComputerArchitectures for Spatially Distributed Data, Cetraro, Italy, June 83. and in published application GB 2 143 349. GB 2 143349 explains how the priority numbers may be assigned dynamically so asto achieve desired allocation ofa shared resource or determination as to which of a plurality of processors provides image data in a situation where images can overlay each other.
The systems described in the references above use multibit priority buses. Each device has priority logic with wired-AND (open collector) connections to the bus lines to pull down bus lines. The logic is such that the device providing the most significant "1" bit in its priority number wins and is granted access to a data bus (maximum priority resolution). The system described in GB 2 143349 is moreover pipelined so that bit-wise comparisons ripple through the logic. The performance ofthese systems is dependent on the number of devices which are connected. The maximum clock speed decreases as the physical size of priority and data buses increases because a longer settling time is required.The total number of contending processors (or devices) is limited by the electrical loading on the wired -OR lines ofthe priority bus. Thus large numbers of contending devices will degrade system performance and ultimatelyceaseto makethisaworkablesolution.
The loading problem is recognised in GB 2143349 and buffering of lines is accordingly proposed. The maximum clock rate is still reduced (one buffer propagation delay is added for each device) and the circuit complexity is increased.
An object of the present invention isto provide a system which does not suffer from these problems and which can be used at very high clock rates, e.g. a pixel clock rate of 160 M Hz or g reater. It is a further objectto provide a system which places no limit on the number of devices which may be incorporated and in which the maximum usable clock rate is not affected by the number of devices (although latency is increased as devices are added). The priority resolution system according to the invention is defined in claim 1 below and advantageous developments are defined in the claims dependent on claim 1.
As already noted, one application of priority resolution is in relation to computer generated image systems, in which case priority values correspond to z-values, i.e. values of the depth coordinate. In synthesizing a picture, higher priority images are required to overlay lower priority images. Various approaches are known but all are relatively complex. It is necessaryto be able to make the resolution on a pixel by pixel basis. Many systems use a frame buffer and sort the image data intotheframe buffer. Sorting is notoriouslydifficultto implement quickly. Thez-buffer algorithm is simpler but requires a largez-bufferto store a z-valueforevery pixel.Systems as described in GB 2 143349 and also in GB 1 532275 which rely on real-time selection ofthe highest priority device suffer from the kind of problems discussed above in relation to the priority resolution process.
It is a further object ofthis invention to provide an improved apparatus for generating a video signal fore raster-scan display, which does sufferfrom the aforementioned disadvantages.
The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a system embodying the invention;
Figure 2 is a block diagram of the priority logic associated with one device; Figures3and 4aretables illustrating the operation of Figure 2; and Figure 5 is a diagram illustrating pipelined operation.
The system illustrated in Figure 1 comprises an ordered plurality of devices such as microprocessors P1,P2 etc. up to Pn. fl must be at least 2 and may well be substantially larger than 2. The processors operate synch ronously with respect to video sync signals for a raster scan display; these signals are passed from processor to processor on a line S. Each processor outputs video signals on a corresponding portal to V, shown as comprising three lines to caterfor R, G and B signals, although the numberoflines is not important to the present invention; only one is needed for a monochrome display. The video lines do not necessarily carry signals which determine colour directly.It is well known to translate the video signals on a plurality of lines by use of a colour look-up table.
The nature ofthe devices P1 to Pn is not important. They may generate their video signals from bit-plane buffers or by real-time scan conversion, for example.
The video signals are fed to respective pixel insertion circuits M1 to Mn, which are essentially two-input, three channel multiplexers through which a video bus X1 to Xn is chained. Each multiplexer outputs whatever it receives on the bus X1 to Xn when a corresponding selection signal D1 to Dn has a first logic state and outputs what it receives on the corresponding port V1 to Vn when its selection signal has the other logic state. The complete image is thus built up from the signals provided from the processors P1 to Pn and the signals from higher order processors may overlay the signals from lower order processors.
The invention is concerned in part with the way in which the selection signals D1 to Dn are provided by priority logic units L1 to Ln associated with the processors P1 to Pn. These units are chained by an m-bit priority busA1,A2... An where is large enough to select between the number of processors involved, i.e.the minimumvalueofm is given by the relation n # 2m < 2n.
In practice it may be more convenient to choose a largervalue form.
Each ofthe priority logic units also receives a corresponding m-bit input B1 to Bn which is the corresponding device's priority number. These numbers may emanate from the devices P1 to Pn themselves or may be assigned by a common priority allocation unit, as in GB 2143349.
The indexes 1 ton pertain to the processors P1 to Pn and associated entities. If the index iis used forthe general case,the properties of each priority logic unit L1 to Ln may be described as follows. A unit Li compares Ai and Bi in bit-wisefashion, working from the most significant to the least significant bit. The first mis-match indicates whetherthe bus number A1 or the device number indicates the higher priority. Dj is set accordingly and A1+1 becomes whichever of at and Bi indicates the higher priority.
Before describing an embodiment of a priority logic unit, certain special cases will be considered. Thefirst priority logic unit L1 is shown receiving A1 and B1.A1 may be set to a minimum priorityvaluetoprovidea threshold below which a processor can not be selected. More likely, A1 will be set to all zeroes (maximum priority resolution) orto all ones (minimum priority resolution) so that A2 always equals B1 and D1 always effects selection. The same result can be achieved by omitting the unit L1, connecting B1 directly to A2 and wiring D1 to effect selection. Going further it is also possible to omit the pixel insertion multiplexer M1 and connect V1 to X2.On the other hand M1 may be provided to caterfor a case in which there is alreadyvideo information on X1, provided by a separate system.
Turning now to the structure of a representative priority logic unit L1, the bits ofthe numbers A1, B1 and A1+1 will be denoted as follows:
Aj = a1 ... aj ... am
Bj = b1 ... bj ... bm Aj+, = z, ... zj ... zm where the subscripts 1 and m denote the most and least significant bits respectively andjdenotes a general bit.
Each priority logic unit (Figure 2) comprises m bit logic units T1 to Tm. Considering the general units, it receives the bits aj and by and outputs 4. The unit Tj also receives inputs c.1 and dti from the next more significant unitTj 1 and outputs c1 and dj to the next less significant unit. The signal c1 indicates whether or not priority has been resolved at the unitTj or at a unit of higher significance and dj indicates, when priority has been resolved, in whose favour. The final bit dm constitutes the selection signal D1 . z becomes a a for the next priority logic unit.
One set of equations defining the structure for in the case of minimum priority resolution is as follows:
cj = q, + (aj (13 bj) (1) dj = c.1.d1.1 + aj. c.1 (2)
Zj = a1.b1 + q .(bj.d; 1 + aj. dj ) (3)
Figure 3tabulates all possible combinations ofthe input quantities ai, bj, cj-1 and dj 1 and the resultant output quantities cj, dj and zj.The heavy boxes indicate the cases in which priority resolution takes place (c#.1 = 0 butch = 1).The bracketed values for dj arethevaluesarisingfrom equation (2) although they are actually "don'tcare" values. An alternative to equation (2) is dj = c1.1. di +bjcj-1 (2a) The convention assumed is that =O means"not resolved" while cj-1 = 1 means "resolved". If c; 1 =0 the value of dj 1 is without significance. If q, = 1, then ds, = 1 means the device has won the priority contest whereas dj 1 = 0 means the bus has won the priority contest.
The provision ofthe initial values co and d0 will now be considered. c0 maybe input from the corresponding processor, as indicated in Figure 1 while do may be tied to logical 0. This allows the processor to allow itselfto enterthe priority contest (by setting c0 = 0) orto shut itself out of the contest by setting c0 = 1, which forces all c, to cm to 1 and forces all dl to do to 0. If this facility is not required, c0 can be tied to logical 0. On the other hand the processor could be given control over both c0 and doto allow itto effectforced selection, overriding the priority contest.
In one particular embodiment d0 is tied to0 and c0 is provided as an ACTIVE signal which is logical 1 only during that part of each scan line traversing an object processed by the processor in question. Thus each processor is prevented from attempting to contribute to the signals on the video bus except in areas which contain image data so far as that processor is concerned.
A set of equations for the case of maximum priority resolution is now given. Figure4 isthecorresponding table of input and output quantities.
The bracketed "don't care" values in Figure 4for dj arethosewhich arise if equation (5) is used. The gate arrays required to implement equations (1) to (3) or equations (4) to (6) are not illustrated as they involve only trivial, everyday design.
So far it has been assumed that each priority logic unit produces its output virtually instantaneously (subject only to the gate delays in rippling through the bit logic units). This may be a practical implementation forsome applications but an important development of the invention allows pipelined operation. Every bit logic unit is provided with latches (not shown) for all its output quantities zi, cj and dj. These latches are clocked by a bit-rate clockCK (Figure 2) so that, if resolution ofthe most significant bits aO, bo is effected in one clock cycle, a1 and b1 will be resolved in the next clock cycle and so on.During the said next clock cycle the bits a, and bo of the next contest are treated and each priority logic unit Lj actually effects bit resolutions simultaneously in each clock cycle from m different contests for which m bus priority numbers A11 to Aim are pipelined through the unit, as illustrated in Figure 5fora greatly simplified case of m = 3. Ail means a first bus priority number handled bya unit Li,Aj2 means the next bus priority number handled by Li and A13 means athird bus priority number handled by Li.
In orderto avoid hiccups in operation,when a device priority numbers is changed it should either be changed during an inactive phase of the system (e.g. during the field blanking interval in a computergraphics application) or be changed bit by bit overm clock cycles, starting with the most significant bit.
In the examples above it has been assumed that positive logic is used throughout. It will be appreciated that the logical conventions employed are immaterial to the principle ofthe invention and may be chosen as may best suit circuit design. It is not essential to preserve the same convention throughout the whole system, although this is desirable if configurations are to be altered. In a fixed configuration system,the most efficient implementation may involve using inverted logic in alternate priority logic units. Inverted logic may also be used in alternate bit logic units within each priority logic unit.
In contrast to the prior art, the maximum clock speed ofthe system does not depend upon the numberof devices P1 to P0. Each priority logic unit Lj merely has to drive lines long enough to carry the bus priority numberto the next unit. Moreoverthere is no limitation on the number of devices imposed by bus loading since the loading on each priority logic unit arises solely from the nextunit.
The invention may be used in many applications, including priority resolution in computer generated image systems, including object-based systems. Other applications are to priority resolution between contending processes in computer systems and to data transfer between processors in multiprocessor systems. The circuitry may also be used to resolve number comparisons for numbers otherthan priority numbers, i.e. as a pipelined hardware comparator.
The pipelined nature ofthe system means that it does not select just one device with highest priority.
Selection is a progressive process along the pipeline and a device is selected if it has higher prioritythanthe bus priority at that point along the pipeline. This form of priority resolution is particularly suited to image overlay processes. It is not applicable when solely the highest priority device is to be selected.
The assigned priority numbers may be such that equal priority situations are never encountered. If they can arise, the logic must be designed to give the required resolution. Reverting to Figure 2, the final signal cmwill befalseifthere is no resolution in any priority logic unit L1 (i.e. A1 = B1). Simple additional logic can be used to force Dj to whichever state is desired when cm is false.
Claims (11)
1. A priority resolution system for a plurality of devices to which priority numbers are assigned, comprising a bit-parallel priority bus relayed through priority logic units individual to the devices, each priority logic unit receiving as bit-parallel inputs the number on the upstream portion of the priority bus and the corresponding device number and providing as a bit-parallel output the number on the downstream portion of the priority bus, and each priority logic unit being constructed to effect bit-wise comparisons between the two input numbers from the most to the least significant bit, to provide a selection signal to the corresponding device in dependence upon the first two compared bits which disagree and to provide as the output number whichever of the two input numbers represents the higher priority.
2. Asystem according to claim 1,wherein each priority logic unit comprises a sequence of bit logic units in order of decreasing significance, each of which receives corresponding bits of the two input numbers and outputs the corresponding output number bit and passes to the next less significant such unit a resolution signal indicating whether or not priority has been resolved and a selection signal indicating whether the resolution is in favour of the bus number of the device number, a resolution signal indicating that priority has been resolved forcing less significant bit logic units to relay both that signal and the associated selection signal to provide the selection signal of the priority logic unit at the output of the least significant bit logic unit.
3. A system according to claim 2, wherein each bit logic unit latches its output number bit, its resolution signal and its selection signal and the bit logic units are clocked at bit rate so that resolutions are pipelined through the priority logic units.
4. A system according to claim 3, wherein device priority numbers, when changed, are changed bit by bit over successive clock cycles, starting with the most significant bit.
5. Apparatus for generating a video signal for a raster-scan display, comprising an ordered plurality of devices operable independently and synchronously with respect to synchronizing signals forthe display to generate video signals, means for assigning priority numbers to the devices, a video line on to which the generated video signals may be placed, and a priority bus for passing a bus priority numberfrom device to device, each device including a priority logic unit for comparing the priority number assigned thereto with the bus priority number received from the preceding device and passing on as the bus priority number to the succeeding device whichever number corresponds to the higher priority, and video insertion means responsive to the priority logic unit and operative, when that unit indicates that the assigned device priority number corresponds to a higher priority than the bus priority number, to introduce the video signal generated bythatdevice on to the video line.
6. Apparatus according to claim 5, wherein each priority logic unit is constructed to effect bit-wise comparisons between the two input numbers from the most to the least significant bit, and to provide a selection signal to the corresponding video insertion means in dependence upon the first two compared bits which disagree.
7. Apparatus according to claim 6, wherein each priority logic unit comprises a sequence of bit logic units in order of decreasing significance, each of which receives corresponding bits of the two input numbers and outputs the corresponding output number bit and passes to the next less significant such unit a resolution signal indicating whether or not priority has been resolved and a selection signal indicating whetherthe resolution is in favour of the bus number of the device number, a resolution signal indicating that priority has been resolved forcing less significant bit logic units to relay both that signal and the associated selection signal to provide the selection signal of the priority logic unit at the output of the least significant bit logic unit.
8. Apparatus according to claim 7, wherein each bit logic unit latches its output number bit, its resolution signal and its selection signal and the bit logic units are clocked at bit rate so that resolutions are pipelined through the priority logic units.
9. Apparatus for effecting sequential comparisons between a plurality of input numbers, comprising a
bit-parallel bus relayed through comparison units individual to the input numbers, each comparison unit receiving as bit-parallel inputs the number on the upstream portion ofthe bus and the corresponding input number and providing as a bit-parallel output the number on the downstream portion of the bus, and each comparison unit being constructed to effect bit-wise comparisons between the two input numbers from the most to the least significant bit, to provide an output signal indicating the sense of disagreement ofthefirsttwo compared bits which disagree, and to provide as the output number whichever ofthe two input numbers satisfies a predetermined comparison test.
10. Apparatus according to claim 9, wherein each comparison unit comprises a sequence of bit logic units
in order of decreasing significance, each of which receives corresponding bits of the two input numbers and outputs the corresponding output number bit and passes to the next less significant such unit a resolution signal indicating whether or not the comparison has been resolved and a selection signal indicating whether the resolution is in favour of the bus number of the input number, a resolution signal indicating thatthe comparison has been resolved forcing less significant bit logic units to relay both that signal and the
associated selection signal to provide the output signal ofthe comparison unit at the output of the least
significant bit logic unit.
11. Apparatus according to claim 10, wherein each bit logic unit latches its output number bit, its resolution signal and its selection signal and the bit logic units are clocked at bit rate so that resolutions are pipelined through the comparison units.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8518130A GB2180125B (en) | 1985-07-18 | 1985-07-18 | Priority resolution system and video display apparatus |
| PCT/GB1986/000422 WO1987000658A1 (en) | 1985-07-18 | 1986-07-18 | Priority resolution system and video display apparatus |
| EP19860904306 EP0231240A1 (en) | 1985-07-18 | 1986-07-18 | Priority resolution system and video display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8518130A GB2180125B (en) | 1985-07-18 | 1985-07-18 | Priority resolution system and video display apparatus |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8518130D0 GB8518130D0 (en) | 1985-08-21 |
| GB2180125A true GB2180125A (en) | 1987-03-18 |
| GB2180125B GB2180125B (en) | 1989-09-20 |
Family
ID=10582458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8518130A Expired GB2180125B (en) | 1985-07-18 | 1985-07-18 | Priority resolution system and video display apparatus |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0231240A1 (en) |
| GB (1) | GB2180125B (en) |
| WO (1) | WO1987000658A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2213340A (en) * | 1987-12-04 | 1989-08-09 | Hamamatsu Photonics Kk | Neighbouring picture element comparison unit |
| GB2299734A (en) * | 1995-04-03 | 1996-10-09 | Motorola As | Method of switching in signal selecting system |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5230041A (en) * | 1990-12-11 | 1993-07-20 | International Business Machines Corporation | Bus interface circuit for a multimedia system |
| US5689657A (en) * | 1991-03-30 | 1997-11-18 | Deutsche Itt Industries Gmbh | Apparatus and methods for bus arbitration in a multimaster system |
| EP0506988B1 (en) * | 1991-03-30 | 1999-06-09 | Micronas Intermetall GmbH | Method of bus arbitration in a multi-master system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1168476A (en) * | 1966-05-17 | 1969-10-29 | British Telecomm Res Ltd | Improvements in or relating to data transmission systems |
| GB2043972A (en) * | 1979-01-26 | 1980-10-08 | Thomas A L | Improvements in or relating to display processors |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2143349B (en) * | 1983-06-16 | 1987-12-02 | Secr Defence | 'priority resolution in bus orientated computer system' |
| GB8419071D0 (en) * | 1984-07-26 | 1984-08-30 | Secr Defence | Language recognition |
-
1985
- 1985-07-18 GB GB8518130A patent/GB2180125B/en not_active Expired
-
1986
- 1986-07-18 EP EP19860904306 patent/EP0231240A1/en active Pending
- 1986-07-18 WO PCT/GB1986/000422 patent/WO1987000658A1/en unknown
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1168476A (en) * | 1966-05-17 | 1969-10-29 | British Telecomm Res Ltd | Improvements in or relating to data transmission systems |
| GB2043972A (en) * | 1979-01-26 | 1980-10-08 | Thomas A L | Improvements in or relating to display processors |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2213340A (en) * | 1987-12-04 | 1989-08-09 | Hamamatsu Photonics Kk | Neighbouring picture element comparison unit |
| US4943934A (en) * | 1987-12-04 | 1990-07-24 | Hamamatsu Photonics Kabushiki Kaisha | Picture operation unit for performing operations on intensity data of neighboring picture elements |
| GB2213340B (en) * | 1987-12-04 | 1992-03-25 | Hamamatsu Photonics Kk | Neighbouring picture operation unit |
| GB2299734A (en) * | 1995-04-03 | 1996-10-09 | Motorola As | Method of switching in signal selecting system |
| US5799253A (en) * | 1995-04-03 | 1998-08-25 | Motorola, Inc. | Method of switching in a signal selecting system |
| GB2299734B (en) * | 1995-04-03 | 1999-10-27 | Motorola As | Method of switching in signal selecting system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1987000658A1 (en) | 1987-01-29 |
| GB8518130D0 (en) | 1985-08-21 |
| EP0231240A1 (en) | 1987-08-12 |
| GB2180125B (en) | 1989-09-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19920718 |