EP0231240A1

EP0231240A1 - Priority resolution system and video display apparatus

Info

Publication number: EP0231240A1
Application number: EP19860904306
Authority: EP
Inventors: Richard Westmore
Original assignee: Anamartic Ltd
Current assignee: Anamartic Ltd
Priority date: 1985-07-18
Filing date: 1986-07-18
Publication date: 1987-08-12
Also published as: GB8518130D0; WO1987000658A1; GB2180125A; GB2180125B

Abstract

Des dispositifs (processeurs) P1 à Pn transmettent des nombres de priorité de dispositif B1 à Bn à des blocs de logique prioritaires L, à Ln, à travers lesquels un nombre de priorité de bus est relayé sur un bus de priorité de m-bits A, à An. Chaque bloc de logique prioritaire (p. ex. L1) effectue une comparaison de bits entre ses nombres d'entrée A1 et B1 (par ordre de signification décroissante) et donne, comme nombre de bus A2, celui parmi A1 et B1 qui indique une priorité plus élevée. De plus, un signal de sélection D1 est donné pour signaler lorsque B1 possède une priorité supérieure à celle de A1. Les signaux de sélection D1 à Dn valident sélectivement les sorties V1 à Vn provenant des processeurs vers un bus vidéo X, à Xn+1 dans l'application décrite.Devices (processors) P1 to Pn transmit device priority numbers B1 to Bn to priority logic blocks L, to Ln, through which a bus priority number is relayed on a priority bus of m-bits A , to An. Each priority logic block (eg L1) performs a bit comparison between its input numbers A1 and B1 (in decreasing order of meaning) and gives, as the number of buses A2, that of A1 and B1 which indicates a higher priority. In addition, a selection signal D1 is given to signal when B1 has a priority higher than that of A1. The selection signals D1 to Dn selectively validate the outputs V1 to Vn from the processors to a video bus X, at Xn + 1 in the application described.

Description

PRIORITY RESOLUTION SYSTEM

AND VIDEO DISPLAY APPARATUS

The present invention relates to a priority resolution system for a plurality of devices to which priority numbers are assigned for determination of priorities in accordance with the rule higher number = higher priority (maximum priority resolution) or the rule lower number = higher priority (minimum priority resolution). The devices may be processors or peripheral devices. The invention also relates to video display apparatus, more specifically apparatus for generating a video signal for a raster-scan display.

Priority resolution systems of the above kind are known and examples are described in "Introduction to a Simple but Unconventional Multiprocessor System and Outline of an Application", Rolf Linder, Technische Hochschule Darmstadt, Presented at the NATO Advanced Study Institute on Computer Architectures for Spatially Distributed Data, Cetraro, Italy, June 83. and in published application GB 2 143 349. GB 2 143 349 explains how the priority numbers may be assigned dynamically so as to achieve desired allocation of a shared resource or determination as to which of a plurality of processors provides image data in a situation where images can overlay each other.

The systems described in the references above use multibit priority buses. Each device has priority logic with wired - AND (open collector) connections to the bus lines to pull down bus lines. The logic is such that the device providing the most significant "1" bit in its priority number wins and is granted access to a data bus (maximum priority resolution). The system described in GB 2 143 349 is moreover pipelined so that bit-wise comparisons ripple through the logic. The performance of these systems is dependant on the number of devices which are connected. The maximum clock speed decreases as the physical size of priority and data buses increases because a longer settling time is required. The total number of contending processors (or devices) is limited by the electrical loading on the wired -OR lines of the priority bus. Thus large numbers of contending devices will degrade system performance and ultimately cease to make this a workable solution. The loading problem is recognised in GB 2 143 349 and buffering of lines is accordingly proposed. The maximum clock rate is still reduced (one buffer propagation delay is added for each device) and the circuit complexity is increased.

An object of the present invention is to provide a system which does not suffer from these problems and which can be used at very high clock rates, e.g. a pixel clock rate of 160 MHz or greater. It is a further object to provide a system which places no limit on the number of devices which may be incorporated and in which the maximum usable clock rate is not affected by the number of devices (although latency is increased as devices are added). The priority resolution system according to the invention is defined in claim 1 below and advantageous developments are defined in the claims dependent on claim 1.

As already noted, one application of priority resolution is in relation to computer generated image systems, in which case priority values correspond to z-values, i.e. values of the depth coordinate. In synthesizing a picture, higher priority images are required to overlay lower priority images. Various approaches are known but all are relatively complex. It is necessary to be able to make the resolution on a pixel by pixel basis. Many systems use a frame buffer and sort the image data into the frame buffer. Sorting is notoriously difficult to implement quickly. The z-buffer algorithm is simpler but requires a large z-buffer to store a z-value for every pixel. Systems as described in GB 2 143 349 and also in GB 1 532 275 which rely on real-time selection of the highest priority device suffer from the kind of problems discussed above in relation to the priority resolution process.

It is a further object of this invention to provide an improved apparatus for generating a video signal for a raster-scan display, which does not suffer from the aforementioned disadvantages.

The invention will be described In more detail, by way of example, with reference to the accompanying drawings, in which:

Fig. 1 is a block diagram of a system embodying the invention;

Fig. 2 is a block diagram of the priority logic associated with one device;

Figs. 3 and 4 are tables illustrating the operation of Fig. 2; and

Fig. 5 is a diagram illustrating pipelined operation.

The system illustrated in Fig. 1 comprises an ordered plurality of devices such as microprocessors P₁, p₂ etc. up to P_n. n must be at least 2 and may well be substantially larger than 2. The processors operate synchronously with respect to video sync signals for a raster scan display; these signals are passed from processor to processor on a line S. Each processor outputs video signals on a corresponding port V₁ to V_n shown as comprising three lines to cater for R, G and B signals, although the number of lines is not important to the present invention; only one is needed for a monochrome display. The video lines do not necessarily carry signals which determine colour directly. It is well known to translate the video signals on a plurality of lines by use of a colour look-up table.

The nature of the devices P₁ to P_n is not important. They may generate their video signals from bit-plane buffers or by real-time scan conversion, for example.

The video signals are fed to respective pixel insertion circuits M₁ to M_n, which are essentially two-input, three channel multiplexers through which a video bus X₁ to X_n is chained. Each multiplexer outputs whatever it receives on the bus X₁ to X_n when a corresponding selection signal D₁ to D_n has a first logic state and outputs what it receives on the corresponding port V₁ to V_n when its selection signal has the other logic state. The complete image is thus built up from the signals provided from the processors p₁ to P_n and the signals from higher order processors may overlay the signals from lower order processors.

The invention is concerned in part with the way in which the selection signals D₁ to D_n are provided by priority logic units L₁ to L_n associated with the processors P₁ to P_n. These units are chained by an m-bit priority bus A₁, A₂ ... A_n where m is large enough to select between the number of processors involved, i.e. the minimum value of m is given by the relation n≤2m<2n.

In practice it may be more convenient to choose a larger value for m. Each of the priority logic units also receives a corresponding m-bit input B₁ to B_n which is the corresponding device's priority number. These numbers may emanate from the devices P₁ to P_n themselves or may be assigned by a common priority allocation unit, as in GB 2 143 349.

The indexes 1 to n pertain to the processors P₁ to P_n and associated entities. If the index i is used for the general case, the properties of each priority logic unit L₁ to L_n may be described as follows. A unit L_i compares A_i and B_i in bit-wise fashion, working from the most significant to the least significant bit. The first mis-match indicates whether the bus number A_i or the device number B_i indicates the higher priority. D_i is set accordingly and A_i+1 becomes whichever of A_i and B_i indicates the higher priority.

Before describing an embodiment of a priority logic unit, certain special cases will be considered. The first priority logic unit L₁ is shown receiving A₁ and B₁. A₁ may be set to a minimum priority value to provide a threshold below which a processor cannot be selected. More likely, A₁ will be set to all zeroes (maximum priority resolution) or to all ones (minimum priority resolution) so that A₂ always equals B₁ and D₁ always effects selection. The same result can be achieved by omitting the unit L₁, connecting B₁ directly to A₂ and wiring D₁ to effect selection. Going further it is also possible to omit the pixel insertion multiplexer M₁ and connect V₁ to X₂ . On the other hand M₁ may be provided to cater for a case in which there is already video information on X₁ , provided by a separate system.

Turning now to the structure of a representative priority logic unit L_i, the bits of the numbers A_i, B_i and A_i+1 will be denoted as follows:

A_i = a₁ ... a_j ... a_m

Bi = b₁ ... b_j ... b_m

A_i+1= z₁ ... z_j ... z_m

where the subscripts 1 and m denote the most and least significant bits respectively and j denotes a general bit.

Each priority logic unit (Fig. 2) comprises m bit logic units T₁ to T_m. Considering the general unit T_j, it receives the bits a_j and b_j and outputs z _j . The unit T_j also receives inputs c_{j- 1} and d_j-1 from the next more significant unit T_j-1 and outputs c_j and d_j to the next less significant unit. The signal c_j indicates whether or not priority has been resolved at the unit T_j or at a unit of higher significance and d_j indicates, when priority has been resolved, in whose favour. The final bit d_m constitutes the selection signal D_i . z_j becomes a _j for the next priority logic unit.

One set of equations defining the structure for T_j in the case of minimum priority resolution is as follows:

c_j = c_j-1 + (a_j b_j) (1) d_j = c_j-1.d_j-1 + a_j. (2) z_j = a_j.b_j + c_j-1.(b_j.d_j-1 + a_j. (3)

Fig. 3 tabulates all possible combinations of the input quantities a_j, b_j, C_j-1 and d_{j- 1} and the resultant output quantities c_j, d_j and z _j . The heavy boxes indicate the cases in which priority resolution takes place (c_j-1 = 0 but c_j = 1). The bracketed values for d_j are the values arising from equation (2) although they are actually "don't care" values. An alternative to equation (2) is d_j = c_j-1. d_j-1 + c_j-1 (2a)

The convention assumed is that c_j-1 = 0 means "not resolved" while c_j-1 = 1 means "resolved". If c_j-1 = 0 the value of d_j-1 is without significance. If c_j-1 = 1, then d_{j -1} = 1 means the device has won the priority contest whereas d_{j -1} = 0 means the bus has won the priority contest.

The provision of the initial values c_o and d_o will now be considered. c_o may be input from the corresponding processor, as indicated in Fig. 1 while d₀ may be tied to logical 0. This allows the processor to allow itself to enter the priority contest (by setting c_o = 0) or to shut itself out of the contest by setting c_o =

1, which forces all c_o to c_m to 1 and forces all d₁ to d_m to 0. If this facility is not required, c_o can be tied to logical 0. On the other hand the processor could be given control over both c_o and d_o to allow it to effect forced selection, overriding the priority contest. In one particular embodiment d_o is tied to 0 and c_o is provided as an ACTIVE signal which is logical 1 only during that part of each scanline traversing an object processed by the processor in question.

Thus each processor is prevented from attempting to contribute to the signals on the video bus except in areas which contain image data so far as that processor is concerned.

A set of equations for the case of maximum priority resolution is now given. Fig. 4 is the corresponding table of input and output quantities.

C_j = c_j-1 + (a_j b_j) (4 ) d_j = c_j-1. d_j-1 + b_j. (5)

OR d_j = C_j-1 . d_j-1 + a_j . c_j-1 (5a)

Z_j = a_j. - + b_j. + d_j-1) (6)

The bracketed "don't care" values in Fig 4 for d_j are those which arise if equation (5) is used. The gate arrays required to implement equations (1) to (3) or equations (4) to (6) are not illustrated as they involve only trivial, everyday design.

So far it has been assumed that each priority logic unit produces its output virtually instantaneously (subject only to the gate delays in rippling through the bit logic units). This may be a practical implementation for some applications but an important development of the invention allows pipelined operation. Every bit logic unit is provided with latches (not shown) for all its output quantities z_j, c_j and d_j. These latches are clocked by a bit-rate clock CK (Fig. 2) so that, if resolution of the most significant bits a_o, b_o is effected in one clock cycle, a₁ and b₁ will be resolved in the next clock cycle and so on. During the said next clock cycle the bits a_o and b_o of the next contest are treated and each priority logic unit L_i actually effects bit resolutions simultaneously in each clock cycle from m different contests for which m bus priority numbers A_i1 to A_im are pipelined through the unit, as illustrated in Fig. 5 for a greatly simplified case of m = 3. k_i1 means a first bus priority number handled by a unit L_i, A_i2 means the next bus priority number handled by L_i and A_i3 means a third bus priority number handled by L_i. In order to avoid hiccups in operation, when a device priority number B_i is changed it should either be changed during an inactive phase of the system (e.g. during the field blanking interval in a computer graphics application) or be changed bit by bit over m clock cycles, starting with the most significant bit.

In the examples above it has been assumed that positive logic is used throughout. It will be appreciated that the logical conventions employed are immaterial to the principle of the invention and may be chosen as may best suit circuit design. It is not essential to preserve the same convention throughout the whole system, although this is desirable if configurations are to be altered. In a fixed configuration system, the most efficient implementation may involve using inverted logic in alternate priority logic units. Inverted logic may also be used in alternate bit logic units within each priority logic unit.

In contrast to the prior art, the maximum clock speed of the system does not depend upon the number of devices P₁ to P_n. Each priority logic unit L_i merely has to drive lines long enough to carry the bus priority number to the next unit. Moreover there is no limitation on the number of devices imposed by bus loading since the loading on each priority logic unit arises solely from the next unit.

The invention may be used in many applications, including priority resolution in computer generated image systems, including object-based systems. Other applications are to priority resolution between contending processes in computer systems and to data transfer between processors in multiprocessor systems. The circuitry may also be used to resolve number comparisons for numbers other than priority numbers, i.e. as a pipelined hardware comparator.

The pipelined nature of the system means that it does not select just one device with highest priority. Selection is a progressive process along the pipeline and a device is selected if it has higher priority than the bus priority at that point along the pipeline. This form of priority resolution is particularly suited to image overlay processes. It is not applicable when solely the highest priority device is to be selected. The assigned priority numbers may be such that equal priority situations are never encountered. If they can arise, the logic must be designed to give the required resolution. Reverting to

Fig. 2, the final signal c_m will be false if there is no resolution in any priority logic unit L_i (i.e. A_i = B_i). Simple additional logic can be used to force D_i to whichever state is desired when c_m is false.

Claims

1. A priority resolution system for a plurality of devices to which priority numbers are assigned, comprising a bit-parallel priority bus relayed through priority logic units individual to the devices, each priority logic unit receiving as bit-parallel inputs the number on the upstream portion of the priority bus and the corresponding device number and providing as a bit-parallel output the number on the downstream portion of the priority bus, and each priority logic unit being constructed to effect bit-wise comparisons between the two input numbers from the most to the least significant bit, to provide a selection signal to the corresponding device in dependence upon the first two compared bits which disagree and to provide as the output number whichever of the two input numbers represents the higher priority.

2. A system according to claim 1, wherein each priority logic unit comprises a sequence of bit logic units in order of decreasing significance, each of which receives corresponding bits of the two input numbers and outputs the corresponding output number bit and passes to the next less significant such unit a resolution signal indicating whether or not priority has been resolved and a selection signal indicating whether the resolution is in favour of the bus number of the device number, a resolution signal indicating that priority has been resolved forcing less significant bit logic units to relay both that signal and the associated selection signal to provide the selection signal of the priority logic unit at the output of the least significant bit logic unit.

3. A system according to claim 2, wherein each bit logic unit latches its output number bit, its resolution signal and its selection signal and the bit logic units are clocked at bit rate so that resolutions are pipelined through the priority logic units.

4. A system according to claim 3, wherein device priority numbers, when changed, are changed bit by bit over successive clock cycles, starting with the most significant bit.

5. Apparatus for generating a video signal for a raster-scan display, comprising an ordered plurality of devices operable independently and synchronously with respect to synchronizing signals for the display to generate video signals, means for assigning priority numbers to the devices, a video line on to which the generated video signals may be placed, and a priority bus for passing a bus priority number from device to device, each device including a priority logic unit for comparing the priority number assigned thereto with the bus priority number received from the preceding device and passing on as the bus priority number to the succeeding device whichever number corresponds to the higher priority, and video insertion means responsive to the priority logic unit and operative, when that unit indicates that the assigned device priority number corresponds to a higher priority than the bus priority number, to introduce the video signal generated by that device on to the video line.

6. Apparatus according to claim 5, wherein each priority logic unit is constructed to effect bit-wise comparisons between the two input numbers from the most to the least significant bit, and to provide a selection signal to the corresponding video insertion means in dependence upon the first two compared bits which disagree.

7. Apparatus according to claim 6, wherein each priority logic unit comprises a sequence of bit logic units in order of decreasing significance, each of which receives corresponding bits of the two input numbers and outputs the corresponding output number bit and passes to the next less significant such unit a resolution signal indicating whether or not priority has been resolved and a selection signal indicating whether the resolution is in favour of the bus number of the device number, a resolution signal indicating that priority has been resolved forcing less significant bit logic units to relay both that signal and the associated selection signal to provide the selection signal of the priority logic unit at the output of the least significant bit logic unit.

8. Apparatus according to claim 7, wherein each bit logic unit latches its output number bit, its resolution signal and its selection signal and the bit logic units are clocked at bit rate so that resolutions are pipelined through the priority logic units.

9. Apparatus for effecting sequential comparisons between a plurality of input numbers, comprising a bit-parallel bus relayed through comparison units individual to the input numbers, each comparison unit receiving as bit-parallel inputs the number on the upstream portion of the bus and the corresponding input number and providing as a bit-parallel output the number on the downstream portion of the bus, and each comparison unit being constructed to effect bit-wise comparisons between the two input numbers from the most to the least significant bit, to provide an output signal indicating the sense of disagreement of the first two compared bits which disagree, and to provide as the output number whichever of the two input numbers satisfies a predetermined comparison test.

10. Apparatus according to claim 9, wherein each comparison unit comprises a sequence of bit logic units in order of decreasing significance, each of which receives corresponding bits of the two input numbers and outputs the corresponding output number bit and passes to the next less significant such unit a resolution signal indicating whether or not the comparison has been resolved and a selection signal indicating whether the resolution is in favour of the bus number of the input number, a resolution signal indicating that the comparison has been resolved forcing less significant bit logic units to relay both that signal and the associated selection signal to provide the output signal of the comparison unit at the output of the least significant bit logic unit.

11. Apparatus according to claim 10, wherein each bit logic unit latches its output number bit, its resolution signal and its selection signal and the bit logic units are clocked at bit rate so that resolutions are pipelined through the comparison units.