EP0216886A1 - Appareil d'affichage video. - Google Patents

Appareil d'affichage video.

Info

Publication number
EP0216886A1
EP0216886A1 EP19860902442 EP86902442A EP0216886A1 EP 0216886 A1 EP0216886 A1 EP 0216886A1 EP 19860902442 EP19860902442 EP 19860902442 EP 86902442 A EP86902442 A EP 86902442A EP 0216886 A1 EP0216886 A1 EP 0216886A1
Authority
EP
European Patent Office
Prior art keywords
window
store
address
display
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19860902442
Other languages
German (de)
English (en)
Other versions
EP0216886B1 (fr
Inventor
Graham P Pump House Hudson
James R C Reid
Dennis Johin Tricker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Telecommunications PLC
Original Assignee
British Telecommunications PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Telecommunications PLC filed Critical British Telecommunications PLC
Priority to AT86902442T priority Critical patent/ATE61141T1/de
Publication of EP0216886A1 publication Critical patent/EP0216886A1/fr
Application granted granted Critical
Publication of EP0216886B1 publication Critical patent/EP0216886B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports

Definitions

  • the present invention is concerned with video display apparatus.
  • a video display apparatus comprising timing means for generating address signals representing successive points within a raster-scan display field; a store for containing video data; a plurality of comparators each arranged in operation to compare the address signals with window limit addresses representing the limits of a respective window area within the display field; and to produce an enabling signal when the relevant point is within that window; store addressing means responsive to the enabling signals to produce or store addresses corresponding to the relevant point(s) and output means for output of video data read from the store.
  • the invention provides a video display apparatus comprising timing means for generating address signals representing successive points within a raster-scan display field; a store for containing high-resolution video data capable of representing a plurality of grey-scale levels; means for storing data relating positions within the display field to store addresses; and store addressing means to produce store addresses corre.sponding to the point of the image to be displayed and output means for output of video data read from the store.
  • FIG. 2 is a block diagram of a video display apparatus according to one embodiment of the invention.
  • Figure 3 is a more detailed block diagram of the di.splay controller used in Figure 2.
  • Figure 1 illustrates the window addressable memory concept employed.
  • the main advantage of such an indirect addressing scheme is that since the memory array is not bit mapped to the screen, it becomes possible to move pictures by simply changing the virtual address of the picture, rather than physically moving the picture data within the memory array.
  • WAMs window addressable memories
  • Figure 1 presents the concept behind this approach to indirect addressing in schematic form.
  • the picture data is stored as a continuous block in a memory array 1, with the start address of the data being stored in a start address latch 2.
  • a window addressable memory 3 (shown for simplicity with only a single location) acts to determine whether the current screen write position x,y is within the rectangular picture boundary (illustrated at 4) or not.
  • Each location consists of four comparators and four latches, with the latter storing the coordinates (x in, y min, x max, y max) of the picture bounding rectangle.
  • each new screen address is generated, (by an x and a y counter which are driven by the di.splay timing signals), it is compared with the values held in the latches, and the output (a single wire) of the window addressable memory indicates whether the screen address is within the picture window.
  • this output increments a "current address" counter 5, whose output is used as the read address of the picture data within the memory array.
  • the current address counter is reset to the value stored in the start address latch 2 at the begining of every frame.
  • the output is used to select a background colour, which could be stored at a single address within the memory array.
  • This basic architecture allows a high functional performance to be achieved, in that a picture can be moved or .scrolled across the screen simply by changing the window information stored in the latches.
  • frame stores for the display of either small or low resolution pictures need be equipped with only as much memory as is necessary to store the picture information.
  • high performance frame stores could be constructed with sufficient memory capacity to store several frames of data, and the indirect addressing scheme would then allow rapid switching between previously downloaded frames through manipulation of the window information.
  • Figure 2 comprising a controller 10, memory array circuitry 30, and interface circuitry including latches/buffers -40, output digital to analogue converters 50 and first in first out (FIFO) stores 60,61 and buffers 62,63 for interfacing to a host computer whose data bus is shown at 70.
  • FIFO first in first out
  • the memory array 30 is assumed to provide sufficient memory for a 540x480 pixel array, with 16 bits per pixel (8 bits luminance, plus 8 bits each for the u and v colour difference signals, shared by two pixels - ie the horizontal chrominance resolution is half that of the luminance). This implies a total capacity of 4.15 Hbits and a video output rate of 13.5MHz (ie 16 bits need to be read out every 74.1ns).
  • the memory array might typically be organised as 64K x 64 bits - eg 16 off 64Kx4bit dynamic RAM chips - the data for four pixels being addressed simultaneously, latched, and multiplexed in latches/multiplexers 40 thereby rec icing the memory access time requirement.
  • FIFO first-in first-out store 60,61
  • the FIFO could be implemented by using a fast static RAM, with a minimum cycle time of 75 nS or less.
  • the FIFO would operate by using two cyclic counters acting as address generators.
  • the write counter During data transmission from the CPU to the frame store, the write counter would increment until it was point to the location one below the read counter. A comparator would then inhibit the write coulter and a signal would be sent to the CPU to indicate that the buffer was full. This state would continue until the read counter was incremented by the frame store controller reading data out of the FIFO. A signal would then be sent to the CPU to indicate more space was available and transmission could recommence.
  • FIG. 3 A block diagram of the controller 10 is shown in figure 3.
  • the key component in the device is the address translator unit 11, which operates to calculate the physical address of picture data from a virtual screen address of the picture. Pictures are represented and manipulated as "windows" of information, specified by a window nur ⁇ ber and its bounding rectangle on the screen.
  • Other circuitry includes a pair of counters 12 whose outputs represent the row and column of the current screen write position, a freespace ounter 13 which is maintained during CRJ write operations to indicate the position of unused memory within the memory array, read and write counters 14,15 which are used during CPU read and write operations, a refresh counter 16 which is maintained to provide systematic refresh of the dynamic memory array 30, a FIFO control unit 17 which supervises data transfer between the memory array and the CFU, a scroll control unit 18 and an overall control unit 19, which generates all required control signals and decodes commands from the CPU. Finally, a programmable timing chain 20 is included which is used to generate the display synchronisation and blanking signals and to control the position of a cursor on the screen.
  • the address translator unit 11 is constructed from a window addressable memory 110, a priority decode unit 111 and an array of address counters 112, each with an associated latch 113 which stores the physical start address of its window within the memory array. Each start address latch is loaded with the contents of the freespace counter when its window is created and written to the memory array by the host CRJ. All address counters 112 are preset to the address stored in the latches 113 at the start of each field (but see below for interlace operation)frame.
  • Each location within the window addressable memory 110 correlates to a window number, and stores two pairs of x-y coordinates which represent the window's bounding rectangle on the screen, with a separate location being provided for each stored window.
  • the outputs of the row and column counters are input to the memory 110 which evaluates whether the screen write position is within any of the stored windows. Three outcomes are possible,
  • the output from the selected address is used to select the output of the appropriate address counter 112 as the physical address to be supplied to the memory array 30, then the selected address counter 112 is incremented to maintain the position within the physical store.
  • the priority decode unit 111 is used to select one of the counter outputs as the physical address, and the address counters of all selected windows are incremented.
  • the priority of window addressable memory sections 110a, 110b etc could be fixed, each with a 1-bit yes/no -output to the priority decoder, or could output the contents of priority word latches 114a, 114b etc.
  • the priority decode unit would then operate on an array of words each representing the priority of its window. The priority of a window would be set as it was written into the frame store, and could subsequently be altered by the host processor. In this way, pictures can be overlaid and moved across one another.
  • the window addressable memory may also include flag bits V,B,A in the latches 114a, 114b.
  • a useful feature which can be provided is a 'viewport' facility, which defines the overall active area on the screen. This can be achieved by designating one or more window addressable memory location(s) - by setting flag bits V - as storing the bounding coordinates of rectangular viewport(s). If the current screen position was outside all of the defined viewports, the address of a border colour, stored and accessed in the same manner as the background colour, described above, would be output onto the controller's address bus. If the current screen position was within any of the defined viewports, the output address would be calculated on the basis of the information stored on the remaining (non-viewport) locations within the window addressable memory.
  • the row and column dimensions of the window addressable memory would be 10 and 8 bits respectively, and each address counter and associated address latch would be 18 bits long.
  • the length of the priority words P depends on the number of windows that can be implemented. Estimates of circuit areas indicate that it should be feasible to implement around 8 windows, implying that an appropriate priority word length,would be 3 bits. It would be useful to store one additional bit A in the priority word which would indicate whether a particular window was active, ie visible, or not.
  • the priority unit iself can be implemented as maximum search CAM (content addressable memory), which subjects the priority words to a parallel maximum search and outputs the address of the maximum as its result.
  • maximum search CAM content addressable memory
  • In order to set up or alter the priority information it would be necessary to write the complet set (for 8 windows four 8 bit words), to the controller. Two further refinements of the basic architecture are required to cope with high resolution and variable display format windows.
  • the first concerns the display of high resolution windows in which one frame of data is produced by two successive interlaced fields.
  • the data from one field of information eg the odd numbered lines
  • the data from the second field that even numbered lines
  • the second refinement is to allow the display of variable display format windows, such as fixed colours from a colour pallette or monochrome.
  • the window addressable memory and priority parts of the address translation unit would operate in the normal fashion, however since the windows would be stored in the same memory array as the normal 4.2.2 format windows, ie one in which 64 bits of information are accessed in each memory address cycle, some allowance must be made for the number of pixels that are displayed from each memory address. For example, in the 4.2.2 case each address increment corresponds to four pixels of information, whereas in the monochrome case each increment would corre-spond to 64 pixels worth of information.
  • This variation in pixel rate can be accommodated by providing a programmable prescaling counter at the input of each current address counter in the address translation unit. In the two examples given above the prescaler would be set to divide by 1 (ie be bypassed) and 16 respectively.
  • a further consequence of the requirement to simultaneously display variable format windows is that it would be necessary to provide additional external circuitry of suitable format at the memory array output, and also to provide the necessary control circuitry for the external devices on the controller chip itself.
  • the minimum operational cycle time of all parts of the address translator is 4 times the dot clock period, ie approx 300 nsec for a 13.5MHz dot clock.
  • the row and column counters 12 would be implemented as 10 bit counters to allow for a maximum display size of 1024 by 1024 pixels. Only the most significant 8 bits of the column counter would be supplied by the window addressable memory to allow for the fact.that 4 pixels are stored at each memory address in the array.
  • the basic display resolution will be determined by the signals supplied from the timing chain. These will determine how many dot clocks per line and how many line clocks per field are passed to the column and row counters, respectively.
  • Half resolution mode may be supported by having a selectable divide by two function on both clocks.
  • the freespace counter would be implemented as an 18 bit counter and incremented as data is written to the array to maintain a pointer to the next free memory location. Some additional circuitry would be necessary to give notice to the CFU when all available space is used.
  • the read and write counters would also be implemented as 18 bit counters.
  • the read cointer When a complete window of data is to be read from the memory array to t-he CPU, the read cointer would be loaded with the window start address, as held in the appropriate start address latch. If only part of a window is to be accessed, the CPU would -first haver to read the window start address from the controller chip, add an appropriate offset to it, then write this information to the controller read counter. In both cases the read counter would then be incremented as data is read from the array to the FIFO, with its output supplying the read address to the memory array during valid CPU access periods.
  • the write counter When a complete window is to be written to the array from the CFU, the write counter would be loaded from the freespace counter and then incremented as data is written to the array, with the counter output supplying the write address to the memory array during v.alid CPU access periods. When part of an existing window is to be modified, the write counter would have to be loaded with an appropriate start address, calculated in the same way as described above for the read operation.
  • the memory array In the indirect addressing scheme the memory array is not accessed in a sequential manner, and only those portions of the array which hold active picture data will be accessed in each frame. It is therefore necessary to provide circuitry which will systematically instigate refresh read cycles during part of the display blanking periods. This function is performed by the refresh counter 16, which will be cycled through the RAM column addresses.
  • the FIFO control unit 17 has to supply the necessary control and address signals which will allow a static RPM to perform as a FIFO buffer between the CPU and the memory array. This can be achieved using a pair of counters, one which holds the current FIFO read address, the other the current write address. For a IK FIFO the counters would be 10 bits long.
  • the scroll control unit 18 is implemented as a simple ALU which would operate on the window bounding box coordinates xmm, Xmax, Ymin, Ymax to effectively scroll a given window on the screen, the amount and direction of the ascroll being sent as part of commands from the CPU, as would the amount of scroll per frame (scroll rate).
  • the main control unit 19 operates to decode and execute commands from the CPU, and to generate all control and timing signals that are required, both internal and external to the controller chip. It could be designed as a synchronous finite state machine and would be implemented using PLA's and random logic as appropriate.
  • the timing chain and cursor control unit produces the necessary display blanking and synchronisation signals, and could also produce strobe sginals which enable a cross hair cursor to be displayed.
  • the timing chain parameters are preferably programmable to allow a variety of video standards to be supported. As far as timing is concerned, the controller chip might be capable of two basic modes of operation, master or slave.
  • Selection between the two timing modes could be achieved by setting a logic level on a mode select pin. It is envisaged that the actual timing signals would either be output or input via bidirectional drivers, to reduce pin count.
  • the timing chain may be implemented as a set of programmable counters and comparators, with the degree of programmability being chosen to allow a sufficient variety of video standards to be supports, and programmed by a set of commands sent to the controller by the host CPU in the normal fashion.
  • the cursor controller may be implasmented as a pair of programmable equality comparators, which operate on the outputs of horizontal and vertical counters in the timing chain. These comparators would be loaded with the cursor position by the CPU, and the logical 'or', of their outputs would be taken to the chip boundary where they would be used to switch in a cursor colour at the memory array output.
  • the basic CPU to memory array write operation is a create window command, which would be used to create a new window of information on the screen.
  • Three basic types of window can be created, a viewport, a block filled window, or a photographic window.
  • a window n-umber which indicates which window addressable memory location/address counter is to be used, would be embedded within the command word.
  • the create viewport operation would be achieved by the CRJ sending a command word, followed by a string of data words, which represent the viewport bounding box coordinates, to the controller. These coordinates woudl be written into the selected window addressable memory location, and the single bit viewport latch V associated with that location would be set to indicate the window type.
  • the create photographic and create block filled window commands would both commence with the transmission of the appropriate command word to the controller.
  • the controller On receipt of this command the controller would first of all store the contents of the freespace counter in the selected start address latch and in the write counter, then reset the FIFO control unit. The controller would then indicate that it was ready to receive picture data from the CPU, which in turn would start to write data to the FIFO input.
  • di.splay blanking data would be transferred from the FIFO to the memory array, with the freespace and write counters being incremented in unison, the latter being used to supply write addresses to the memory array.
  • the CRJ would indicate completion of the write operation (after the transfer of a single pixel of information in the block filled case) by sending further commands to the controller, which would include the window coordinates and priority of the data that has been transferred. These items would be stored in appropriate locations within the address translator.
  • a further write window command that may be supported is the modify window command, which would be used to change the contents of part of an existing window.
  • the CRJ would first of all read the start address of the window from the controller chip. It would then calculate an offset based on the window size which takes it to the desired point within the window. The CRJ would then send the modify window command to the controller followed by an address, formed as the sum of the start address and the offset, which the controller would store in the write counter. The controller would reset the FIFO control unit, and the CRJ would then proceed to write data to the FIFO input. The controller chip would then transfer the data from the FIFO to the memory array. It would be the responsibility of the CPU to perform memory management calculations to ensure that the amount of data transferred did not exceed the capacity of the window. (c) Read Window
  • the first type of read operation would be instigated by the CRJ sending a read window command to the controller chip.
  • a window number which indicates irf ⁇ ch window addressable memory location/address counter is to be used, would be embedded within the comand word.
  • the controller On receipt of this command the controller would first of all reset the read counter to the contents of the selected window's start address latch and reset the FIFO control unit. During display blanking periods data would be transferred from the memory array to the FIFO, with the read counter being used to supply read addresses to the memory array.
  • the controller would indicate that it was ready to send daa to the CRJ.
  • the CRJ would access this data by supplying a simple read clock to the FIFO control unit.
  • the CPU would terminate the read operation once .sufficient data has been accessed, by sending a stop command to the controller.
  • the second type of read operation which would be performed when it was required to read part of a window at some offset from the window start, would be performed in a similar manner to the one described above, except that in this case the read counter would be loaded with the appropriate address by the CPU at the start of the operation. This address would be calculated by the CRJ in the same way as described above for the modify window command.
  • the first type would be implemented using the scroll control unit.
  • the CPU would send a move window command to the controller, (with the window number embedded in- the command as before), followed by dx and dy data words which specify the magnitude of the move.
  • the ALU within the scroll control unit would add the dx and dy data into appropriate components of the selected window coordinates, and then return the results to the window addressable memory.
  • the absolute move window operation would be performed by the CRJ transmitting new window coordinates to the controller, which would overwrite the old coorodinates to the selected window with these values.
  • the simplest way to implement the scroll window function is for the CRJ to send a dx and a dy increment to the controller, followed by two data words which specify how many times each has to be applied.
  • the scroll control unit would then operate to add the increments into the selected window coordinates once per frame, until the speicified number of increments have been made, (f) Grab Mode
  • Grab mode is required to fill the memory array with real time data from a video camera.
  • normal controller operation apart from mmory refresh, would be suspended.
  • the freespace counter would be reset, then incremented as data was written into the array, the counter's output being used to supply write addresses to the array.
  • the input FIFO would be bypassed in this mode of operation.
  • the host CRJ At the end of the operation it would be necessary for the host CRJ to write the window coordinates of the grabbed frame to the controller chip.
  • An additional feature that might be provided is to permit "transparent" areas within a window thereby allowing part of a lower priority window to become visible. This could be achieved by providing an additional bit in the memory, or (preferably) reserving a special code - eg the luminance range could be limited to 0000 to FFFE (hex), FFFF indicating transparency - so that a window selected by the address translator can be temporarily deselected.
  • a special code eg the luminance range could be limited to 0000 to FFFE (hex), FFFF indicating transparency - so that a window selected by the address translator can be temporarily deselected.
  • One problem with this approach is that of memory access times, since, the memory having been read and a transparent pixel found, a further memory access is required to obtain the data for the next lower priority window. If more than one overlapping tran.sparent area is permited to occur, the problem becomes much worse, and the number of .such layers needs to be limited.
  • windows with transparent pixels be marked with a transparent attribute.
  • the controller alternately addresses a memory slice (64bits) from the- upper window followed by a slice from the underlying window.
  • the data selector will require a second 64 bit latch and multiplexer to enable the pixel colours from either slice to be selected for display.
  • a pixel from the multiplexer of the upper window is detected to be transparent the pixel from the second window multiplexer is selected. Transparency can only operate if neither window required the full memory bandwidth (13.5MHz/16 bit).

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Abstract

Des signaux d'adresse sont produits en correspondance avec les points successifs d'un champ d'affichage (4) à balayage récurrent. Des comparateurs (3) comparent les adresses avec les adreses limites des zones de fenêtres de l'affichage et lorsqu'une adresse se trouve dans une zone de fenêtre, des adresses de mémoire sont produites de manière à permettre l'accès aux données vidéo mémorisées (1).
EP19860902442 1985-04-03 1986-04-02 Appareil d'affichage video Expired - Lifetime EP0216886B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT86902442T ATE61141T1 (de) 1985-04-03 1986-04-02 Videoanzeigevorrichtung.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB858508668A GB8508668D0 (en) 1985-04-03 1985-04-03 Video display apparatus
GB8508668 1985-04-03

Publications (2)

Publication Number Publication Date
EP0216886A1 true EP0216886A1 (fr) 1987-04-08
EP0216886B1 EP0216886B1 (fr) 1991-02-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP19860902442 Expired - Lifetime EP0216886B1 (fr) 1985-04-03 1986-04-02 Appareil d'affichage video

Country Status (4)

Country Link
EP (1) EP0216886B1 (fr)
JP (1) JPS62502429A (fr)
GB (1) GB8508668D0 (fr)
WO (1) WO1986005910A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1196844B (it) * 1986-12-16 1988-11-25 Olivetti & Co Spa Governo video per apparecchiature di informatica
FR2610160B1 (fr) * 1987-01-27 1989-03-24 Radiotechnique Compelec Dispositif synthetiseur d'images
JPH0291721A (ja) * 1988-09-29 1990-03-30 Toshiba Corp ウィンド表示制御装置
US4953027A (en) * 1989-04-24 1990-08-28 Motorola Inc. OSD in a TV receiver including a window, smoothing and edge enhancing
US5307180A (en) * 1991-12-18 1994-04-26 Xerox Corporation Method and apparatus for controlling the processing of digital image signals
US5477242A (en) * 1994-01-03 1995-12-19 International Business Machines Corporation Display adapter for virtual VGA support in XGA native mode
KR19980042031A (ko) * 1996-11-01 1998-08-17 윌리엄 비. 켐플러 가변 해상도 스크린 디스플레이 시스템
US6369855B1 (en) 1996-11-01 2002-04-09 Texas Instruments Incorporated Audio and video decoder circuit and system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2559927B1 (fr) * 1984-02-20 1986-05-16 Comp Generale Electricite Circuit cable de gestion de fenetres sur ecran

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8605910A1 *

Also Published As

Publication number Publication date
WO1986005910A1 (fr) 1986-10-09
EP0216886B1 (fr) 1991-02-27
JPS62502429A (ja) 1987-09-17
GB8508668D0 (en) 1985-05-09

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