EP0216183A2 - Egalisateur à décision récursive utilisant un détecteur de motif - Google Patents

Egalisateur à décision récursive utilisant un détecteur de motif Download PDF

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Publication number
EP0216183A2
EP0216183A2 EP86111878A EP86111878A EP0216183A2 EP 0216183 A2 EP0216183 A2 EP 0216183A2 EP 86111878 A EP86111878 A EP 86111878A EP 86111878 A EP86111878 A EP 86111878A EP 0216183 A2 EP0216183 A2 EP 0216183A2
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EP
European Patent Office
Prior art keywords
signal
residual
isi
estimated
data sequence
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86111878A
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German (de)
English (en)
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EP0216183B1 (fr
EP0216183A3 (en
Inventor
Akira Kanemasa
Akihiko Sugiyama
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NEC Corp
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NEC Corp
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Publication date
Priority claimed from JP19072685A external-priority patent/JPS6248816A/ja
Priority claimed from JP19072785A external-priority patent/JPS6249732A/ja
Priority claimed from JP19432985A external-priority patent/JPS6253029A/ja
Priority claimed from JP9074586A external-priority patent/JPS62247630A/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0216183A2 publication Critical patent/EP0216183A2/fr
Publication of EP0216183A3 publication Critical patent/EP0216183A3/en
Application granted granted Critical
Publication of EP0216183B1 publication Critical patent/EP0216183B1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure

Definitions

  • the present invention relates to a decision feedback equalizer (DFE) for removing intersymbol interference (ISI) which is particular to pulse transmission.
  • DFE decision feedback equalizer
  • a DPI is one of implementations heretofore proposed for the removal of ISI which occurs during pulse transmission.
  • a DFE an adaptive filter having taps corresponding to a length over which ISI has influence is installed to generate estimated ISI, so that ISI occurring during transmission of pulses over a channel may be suppressed.
  • the ta p coefficients of the filter are sequentially corrected by determining a correlationship between residual ISI and a result of decision of a received signal.
  • a problem with a DFE is that the adaptive operation is unachievable unless residual ISI contained in a residual signal which is produced by subtracting estimated ISI from a received signal having ISI, is detected with accuracy in the event of correction of the coefficients.
  • a DFE in accordance with the present invention comprises first adaptive filter means responsive to a demodulated data sequence and a residual ISI signal for estimating ISI which occurs during pulse transmission of a period of T second and producing an estimated ISI signal, first subtractor means for subtracting the estimated ISI signal from a received signal having an -ISI signal to produce a residual signal, means for extracting the residual ISI signal from the residual signal and a delayed residual signal which is produced by delaying the residual signal, first demodulating means for producing the demodulated data sequence from the residual signal and applying the demodulated data sequence to the first adaptive filter means, pattern detector means for detecting a particular consecutive pattern out of the demodulated data sequence, and means for applying the residual ISI signal to the filter means in response to an output of the pattern detector means.
  • Fig. 1 shows a biphase code and Fig. 2 a minimum shift keying (MSK) code.
  • the biphase code assigns pulse shapes of opposite polarities to data ONE and ZERO.
  • the two pulse shapes individually have the polarities inverting at the center of one bit width, i.e., T second and are balanced within one bit in terms of positive and negative polarities.
  • the MSK code is implemented with four different kinds of pulse shapes, as shown in Fig. 2.
  • the MSK code assigns two different kinds of pulse shapes of opposite polarities, i.e., a ONE mode and a ZERO mode to each of data ZERO and ONE, the transitions of the four pulse shapes being represented by arrows in Fig. 2.
  • the MSK code is characterized in that the polarity is necessarily inverted at the point of interconnection of transmitted pulse shapes.
  • the MSK code is balanced for a data ONE within one pulse shape but not for a data ZERO, each in terms of positive- negative levels. Nevertheless, it will be seen from the directions of the arrows of Fig. 2 that if an even number of data ZEROs exist in a data sequence, the positive- negative balance is set up so that the DC component is almost negligible.
  • a DFE in accordance with the present invention includes an input terminal 1.
  • a received signal which involves ISI is applied to the input terminal 1 and then to a subtractor 2.
  • the subtractor 2 subtracts from the received signal an estimated ISI signal which is generated by an adaptive filter 5, thereby producing a residual signal which involves residual ISI.
  • the residual signal is applied to an arithmetic circuit 9 after being delayed by a delay element 8 by i sampling times.
  • the arithmetic circuit 9 cancels the data involved in the residual signal by the delayed signal to extract a residual ISI signal.
  • the cancellation by the circuit 9 is effected by subtraction of the two input signals.
  • the residual signal from the subtractor 2 is also fed to a decision circuit 3 which compares the residual signal with a reference value to determine an original two-level data sequence. This data sequence is routed to an output terminal 4, a pattern detector 11, and the adaptive filter 5.
  • the dicision circuit 3 may be conveniently implemented with a construction which is described in a paper "A Study on the Subscriber Loop Transmission System for ISDN Based on the Echo Cancellation Technique" presented at IEEE International Conference on Communications which was held in Chicago, U.S.A on July 23 to 26, 1985.
  • the pattern detector 11 detects out of the output of the decision circuit 3 a particular pattern from which the residual ISI signal can Le detected as will be described later, the detected pattern being applied to a selector 10.
  • the selector 10 selects either one of the residual ISI signal or a zero volt and delivers it to the filter 5. Based on the output of the selector 10 and the data sequence of the decision circuit 3, the filter 5 corrects tap coefficients or filter coefficients and generates an estimated ISI signal. It is to be noted that the correction of filter coefficients does not occur when the selector 10 has selected a zero volt.
  • the reason why the residual ISI signal is obtainable by cancelling the data involved in the residual signal is that the ISI signal of the residual signal and that of the delayed-signal are not correlated. Because the value of the current ISI signal and that of the delayed ISI signal are not correlated, the value of the delayed ISI signal may be regarded as random noise.
  • the delayed ISI signal has a symmetrical amplitude distribution with respect to the positive and negative polarities, and the probability that its amplitude d becomes
  • the pattern detector 11 is constructed to detect the code sequences "000" (Fig. 4A) and "111" (Fig. 4B) as mentioned above.
  • Fig. 5 shows a specific construction of the pattern detector 11.
  • the input signal 51 corresponds to the data sequence outputted by the decision circuit 3 as shown in Fig. 3, and the input signal 52 to the mode signal.
  • the signal path between the decision circuit 3 and the pattern detector 11 and that between the circuit 3 and the filter 5 are each represented by a single path, in the case of MSK code they are representative of two signal paths each, one for the data signal and the other for the mode signal.
  • Delay elements 53 and 54 each adapted to provide a delay of T second and an Exclusive-NOR (EXNOR) gate 55 cooperate to determine whether the current data and the data appeared 2T seconds before are coincident with each other.
  • EXNOR Exclusive-NOR
  • delay elements 56 and 57 each adapted to provide a delay of T second and an EXNOR gate 58 cooperate to see if the current mode signal and the mode signal delayed by 2 T second are coincident with each other.
  • An AND gate 59 provides AND of the outputs of the EXNOR gates 55 and 58 to produce a pattern detection signal 60.
  • the pattern detector 11 will be described in relation to the biphase code as shown in Fig. 1 which is another possible transmission line code.
  • Fig. 7 shows a specific construction of the pattern detector 11 constructed to detect such five-bit patterns.
  • the pattern detector includes EXNORs 71, 72 and 73 which function to see coincidence of the first and third bits of a five-bit code, that of the second and fourth bits, and that of the third and fifth bits, respectively.
  • the detector also includes an AND gate 74 adapted to detect coincidence of outputs of the EXNORs 71 to 73.
  • the adaptive filter 5 of Fig. 3 is shown in a detailed block diagram.
  • the input signals 106' and 106 respectively correspond to data (ZERO or ONE) and mode (positive or negative) which are outputted by the decision circuit 3 of Fig. 3.
  • the input output signals 107 and 108 respectively correspond to output signals of the selector 10 and adaptive filter 5 of Fig. 3.
  • the mode signal 106 is fed to a delay element 100 1 , a multiplier 101 0 , and a coefficient generator 102 0 .
  • the data signal 106' is applied to a delay element 100' 1 and the coefficient generator 102 0 . It should be born in mind that N in Fig.
  • the coefficient generators 102 0 to 102 N are adapted to supply their associated multipliers 101 0 to 101 N with coefficients corresponding to the respective modes in response to the mode signal 106'.
  • the multipliers multiply outputs of their associated delay elements and the coefficients applied thereto, delivering the products to an adder 103. Summing up the products, the adder 103 delivers an estimated ISI signal as the output signal 108.
  • Each of the coefficient generators 102 0 to 102 N corrects its coefficient in response to a residual ISI signal which is fed as the input signal 107 and an output signal from its associated delay element.
  • the input signal 200 corresponds to the input signal 106 or one of the output signals of the delay element 100 1 , 100 2 , ..., 100 N of Fig. 8.
  • the input signal 200' corresponds to the signal 106' or one of the outputs 100' 1 , 100' 2 , ..., 100' N of Fig. 8, and the input signal 201 to the signal 107 of Fig. 8.
  • the output signal 209 of Fig. 9 corresponds to the output of the coefficient generator 102 1 of Fig. 8.
  • the data signal 200' which is representative of a ZERO or a ONE is fed as a control signal to selectors 204, 205 and 208.
  • the mode signal 200 assuming a value of +1 or -1 which is representative of a + mode or a - mode and associated with the data signal 200' is applied to one input of a multiplier 202.
  • a residual ISI signal 201 which comprises an ISI component only.
  • the multiplier 202 multiplies the mode signal 200 and the residual ISI signal 201 and delivers the product to one input of an adder 203.
  • Delay elements 206 and 207 serve as coefficient memories which are respectively associated with a ZERO and a ONE of the data signal 200', the elements 206 and 207 being coupled to a selector 208.
  • the data signal 200' is also fed to the selector 208 as a control signal.
  • the selector 208 selects a coefficient which is associated with a ZERO which is the output of the delay element 206 and, when the data signal 200' is a ONE, it selects a coefficient associated with a ONE which is the output of the delay .element 207.
  • the coefficient 209 selected by the selector 208 is delivered as indicated as in Fig. 9.
  • This coefficient 209 is routed also to the adder 203 to be added to an output of the multiplier 202.
  • the output of the adder 203 is fed to the selectors 204 and 205.
  • the outputs of the delay elements 206 and 207 are applied also to the selectors 204 and 205, respectively.
  • the outputs of the selectors 204 and 205 are applied to the delay elements 206 and 207, respectively.
  • the selectors 204, 205 and 208 operate as follows. Assume that the data signal 200' is a ZERO. Then, the selector 208 selects the output of the delay element 206 which corresponds to the data ZERO, the selected delay output being delivered as a coefficient 209.
  • the coefficient is fed to the adder 203 and then fed back to the delay element 206 via the selector 204, thereby updating the coefficient which is associated with the data ZERO.
  • the selector 205 selects the output of the delay element 207 and feeds it back to the delay element 207 with the result that the coefficient associated with the data ONE is not updated.
  • the selector 208 selects the output of the delay element 207 which is associated with the data ONE.
  • the resultant coefficient 209 is applied to the adder 203 and then fed back to the delay element 207 via the selector 205, whereby the coefficient associated with the data ONE is updated.
  • the selector 204 selects the output of the delay element 206 and returns it to the element 206 with the result that the coefficient associated with the data ZERO is not updated.
  • a particular coefficient which is associated with the value of the data signal i.e., a ZERO or a ONE is selected for the arithmetic operation of the filter and, at the same time, the coefficient used is updated while the coefficient not used is not updated. In this manner, the coefficients of the filter are set up adaptively.
  • a second embodiment of the present invention is shown.
  • the zero-crossing point of a received signal changes as the transmission distance increases. Should the received signal be decided based on a clock signal which is derived from such a signal, the decision point would be deviated from a point where the data reaches the highest level.
  • the embodiment of Fig. 10 is constructed to eliminate such an occurrence.
  • the DFE includes a selector 13 adapted to select either the output of the selector 10 or the residual signal in response to an output of the decision circuit 3, and a switch 14.
  • the switch 14 has a fourth terminal 144 for receiving the residual signal, a first and a third terminals 141 and 143 for receiving an output of the selector 10, and a second terminal 142 for receiving an output of the selector 13.
  • the switch 14 sequentially selects the terminals 141 to 144 in response to the control signal.
  • the signal selected by the switch 14 is fed to an adaptive filter 50.
  • the filter 50 adjusts coefficients thereof such that the residual ISI at each time converges to zero.
  • the delay elements 100 1 to 100 N and 100' 1 to 100' N are shared by the data sequences at 2/4 ⁇ T to 4/4 ⁇ T.
  • a third embodiment of the present invention is shown. While the first and second embodiments each contemplates to remove ISI with which the past pulse shape effects the current pulse shape, the third embodiment further contemplates to remove intrasymbol interference (ITSI) with which the current pulse shape itself effects the current levels at times 2/4 . T and 4/4 ⁇ T.
  • a selector 17 delivers to the filter 18 the signal appearing at 2/4 ⁇ T or a zero volt when the output of the decision circuit 3 is a ONE or a ZERO, respectively.
  • the filter 18 In response to the signal at T/4 from the switch 16 and the ITSI signal at 2/4 T from the selector 17, the filter 18 generates an estimated ITSI signal for removing the ITSI signal at 2/4 . T. Likewise, the filter 20 responds to the data outputted by the detection circuit 19 and the ITSI signal at T by generating an estimated ITSI signal which removes the ITSI signal at T.
  • An adder 21 sums outputs of the filters 50 and 18 to apply the sum to an adder 22 while the adder 22 sums an output of the filter 20 and that of the adder 21 to generate an estimated ITSI signal.
  • Fig. 13 shows a specific construction of the adaptive filter 18 of Fig. 12.
  • the input signals 300 and 301 respectively correspond to an output signal of a first terminal of the switch 16 of Fig. 12, i.e., polarity of the residual signal at the sampling time t 1 , and an output of the selector 17, i.e. polarity of an IT S I signal at the sampling time t 2 or an error signal which is a zero volt.
  • the output signal 306 as shown in Fig. 13 corresponds to the output signal, or estimated ITSI, of the adaptive filter 18 of Fig. 12.
  • the polarity 300 of the residual signal is routed to multipliers 302 and 305.
  • a delay element 304 adapted for a delay of T second serves as coefficient memory and applies an output thereof to the multiplier 305 which then generates estimated ISI 306. Also, the output of the delay element 304 is fed back thereto via an adder 303 so that a coefficient associated with the output of the multiplier 302 is selectively updated.
  • the error signal 301 is zero
  • the output of the multiplier 302 is also zero and, therefore, the coefficient is not updated. In this manner, the coefficient is selectively updated.
  • the estimated ITSI signal at the zero-crossing point which occurs at the center within a symbol appears and is added by the adder 21 to the estimated ITSI signal which is generated by the adaptive filter 50.
  • the output of the adder 21 is fed to the subtractor 2 via the adder 22.
  • Fig. 14 a specific construction of the adaptive filter 20 of Fig. 12 is shown in a detailed q N block diagram.
  • the filter 20 corresponds to only one phase and one tap of the filter 50.
  • the principle of operation of the filter 20 for updating the coefficients is the same as that of Fig. 9 and, therefore, detailed description thereof will be omitted to avoid redundancy.
  • Fig. 14 the same function blocks and signals as those of Fig. 9 are designated by like reference numerals.
  • the data signal 200 and the mode signal 200' correspond to the outputs of the decision circuit 3 of Fig. 10, and the error signal 201 to the output of the fourth terminal of the switch 16 as shown in Fig. 12.
  • the filter of Fig. 14 differs from that of Fig. 9 in that the mode signal 200' is multiplied by a coefficient 209 by a multiplier 210 to produce estimated ITSI 211.
  • Another difference is that while the error signal 201 in Fig. 9 selectively assumes three values, i.e., ⁇ 1 and 0, it in Fig. 14 assumes either one of two values, i.e. il.
  • the estimated ITSI which is outputted by the adaptive filter 20 is applied to the adder 22 to be added to an output of the adder 21, the sum being fed the subtractor 2.
  • the arithmetic unit 9 performs subtraction on an input signal and a delayed signal in order to cancel a data involved in a residual signal.
  • the subtraction may be replaced with addition in which case a consecutive symbol pattern is selected such that, as shown in Figs. 4C and 4D, the wave shape of one of the current input signal and the delayed signal becomes identical with pulse shape of the other when inverted.
  • the EXNOR 58 responsive to coincidence of mode signals may be replaced with an Exclusive-OR gate which is responsive to non-coincidence of mode signals.
  • the adaptive operation of an adaptive filter is ensured because the filter is controlled such that the coefficients are selectively updated by detecting the pattern of a received signal waveform appearing when either a sum or a difference between the current value of a residual signal and a value of the same appeared iT second before is equal to the ITSI signal.
  • This realizes decision feedback type removal of ISI which eliminates the need for complicated control and can be implemented with a simple and small-scale hardware configuration.
  • the present invention allows not only ISI due to a past sequence of symbols but only ISI within a sequence of data to be removed.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)
EP86111878A 1985-08-28 1986-08-27 Egalisateur à décision récursive utilisant un détecteur de motif Expired - Lifetime EP0216183B1 (fr)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP19072685A JPS6248816A (ja) 1985-08-28 1985-08-28 判定帰還型等化方式
JP190727/85 1985-08-28
JP190726/85 1985-08-28
JP19072785A JPS6249732A (ja) 1985-08-28 1985-08-28 判定帰還型等化方式
JP194329/85 1985-09-02
JP19432985A JPS6253029A (ja) 1985-09-02 1985-09-02 判定帰還による符号間干渉除去方法
JP90745/86 1986-04-18
JP9074586A JPS62247630A (ja) 1986-04-18 1986-04-18 判定帰還による符号間干渉除去方法及び装置

Publications (3)

Publication Number Publication Date
EP0216183A2 true EP0216183A2 (fr) 1987-04-01
EP0216183A3 EP0216183A3 (en) 1989-01-25
EP0216183B1 EP0216183B1 (fr) 1992-06-03

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EP86111878A Expired - Lifetime EP0216183B1 (fr) 1985-08-28 1986-08-27 Egalisateur à décision récursive utilisant un détecteur de motif

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US (1) US4730343A (fr)
EP (1) EP0216183B1 (fr)
CA (1) CA1258296A (fr)
DE (1) DE3685536T2 (fr)

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CN106707762A (zh) * 2017-02-20 2017-05-24 海南大学 一种两输入两输出网络控制系统不确定时延混杂控制方法

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US5157690A (en) * 1990-10-30 1992-10-20 Level One Communications, Inc. Adaptive convergent decision feedback equalizer
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US6680971B1 (en) * 1998-05-18 2004-01-20 Sarnoff Corporation Passband equalizer for a vestigial sideband signal receiver
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106707762A (zh) * 2017-02-20 2017-05-24 海南大学 一种两输入两输出网络控制系统不确定时延混杂控制方法
CN106707762B (zh) * 2017-02-20 2020-08-21 海南大学 一种两输入两输出网络控制系统不确定时延混杂控制方法

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EP0216183B1 (fr) 1992-06-03
US4730343A (en) 1988-03-08
DE3685536T2 (de) 1993-01-21
EP0216183A3 (en) 1989-01-25
CA1258296A (fr) 1989-08-08
DE3685536D1 (de) 1992-07-09

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