Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Definitions

• the present invention relates to a method of making an integrated ferroelectric device - and a device produced thereby.
• a method of making an integrated ferroelectric device comprising the steps of:
• An integrated ferroelectric device comprising:
• the invention also provides a method of fabricating a combined integrated circuit/ferroelectric memory device, including the steps of removing predetermined portions of a surface of an integrated circuit for providing contacts with the input/output logic of the integrated circuit, and thereafter depositing a first conductive layer.
• the method proceeds with removing undesired portions of the first conductive layer, depositing a ferroelectric layer, and th ⁇ n depositing a second conductive layer.
• the method proceeds with then removing undesired portions of the ferroelectric layer and of the second conductive layer, depositing a passivation layer, and then removing undesired portions of the passivation layer.
• the method then proceeds with depositing a third conductive layer for electrically connecting the second conductive layer to the input/output logic of the integrated circuit, and thereafter removing undesired portions of the third conductive layer.
• a primary object of the present invention is to provide a method for building an integrated ferroelectric device whereby the top electrode (interconnect) encapsulates the ferroelectric cell.
• a further object of the invention is to provide a method for constructing an integrated ferroelectric device where the top electrode (interconnect) encapsulates a Phase III K 0 3 cell.
• An object of the present invention is to provide a device and a method as described and/or claimed herein 4 wherein the ferroelectric layer which is deposited comprises and/or includes Phase III potassium nitrate.
• Another object of the present invention is to provide a device and a method as described and/or claimed herein wherein the ferroelectric layer and the second conductive layer are both deposited during a single pumpdown, i.e., under the same vacuum condition.
• a further object of the present invention is to provide a device and a method as described and/or claimed herein wherein undesired portions of the ferroelectric layer and the second conductive layer are removed by means of ion milling.
• Yet another object of the present invention is to provide a method and a device as described and/or claimed herein wherein the ferroelectric layer has a thickness of less than 110 microns, and preferably falling within the range of from 100 Angstrom units to 5,000 Angstrom units.
• a further object of the present invention is to provide a device and a method as described and/or claimed herein wherein after the step of depositing the ferroelectric layer, and prior to. depositing the second conductive layer, there is included the step of filling any grain boundaries, cracks and/or imperfections in the ferroelectric layer with insulative material.
• Another object of the present invention is to provide a a device and a method as described and/or claimed herein wherein prior to the step of depositing the first conductive layer, there is included the steps of forming first layer interconnects on the surface of the semiconductor integrated circuit, and thereafter depositing a non-semiconductor dielectric and forming interconnect and bonding pad vias therein.
• a further object of the present invention is to provide a device and a method as described and/or claimed herein wherein the step of depositing the second conductive layer includes the deposition of a conductive layer forming a top electrode, wherein this conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides.
• An additional object of the present invention is to provide a device and a method as described and/or claimed herein wherein the first layer interconnects are composed of doped polysilicon.
• a further object of the present invention is to provide a method and a device as described and/or claimed herein wherein the non-semiconductor dielectric and/or passivation layer is selected from the group consisting of low temperature glass, silicon dioxide, silicon nitride, oxides, and sputtered and/or evaporated dielectrics.
• Another object of the present invention is to provide a device and a method as described and/or claimed herein wherein the Phase III potassium nitrate layer has a thickness within a range of from 100 Angstrom units to
• a further object of the invention is to provide a device and a method as described and/or claimed herein wherein the Phase III potassium nitrate layer has a thickness of less than 2 microns and is stable at room temperature.
• Another object of the present invention is to provide a device and a method as described and/or claimed herein wherein after deposition of the first conductive layer, and prior to the deposition of the ferroelectric layer, there is included the step of depositing a second non-semiconductor dielectric and forming vias therein.
• a further object of the present invention is to provide combined integrated circuit/ferroelectric memory devices produced in accordance with any of the methods described and/or claimed herein.
• Fig. 1 shows a top plan view of an integrated circuit chip depicting connections to the integrated circuit driving logic through first cuts in a surface of the integrated circuit.
• Fig. 2 illustrates a sectional view taken along the line 2-2 shown in Fig. 1.
• Fig. 3 illustrates a cross-section of a further stage in the method showing the first conductive layer on which has been deposited a ferroelectric layer, and upon which in turn has been deposited a second conductive layer, and upon which in turn has been deposited photoresist.
• Fig. 4 illustrates a cross-section of a further stage in the method in which undesired portions of the first conductive layer, ferroelectric layer and second conductive layer have been removed by ion milling, and also indicating the remaining resist ashed off in vacuum.
• Fig. 5 illustrates a top plan view of a further stage in the method showing the openings to the second conductive layer at each cell, and the openings for the contacts to the substrate pads for the top electrodes.
• Fig. 6 illustrates a sectional view taken along the line 6-6 shown in Fig. 5.
• Fig. 7 illustrates a top plan view of the integrated circuit chip showing a further stage in the method wherein the third conductive layer has been applied to define a top metal electrode with its connection to the substrate pads.
• Fig. 8 illustrates a sectional view taken along the line 8-a shown in Fig. 7.
• Fig. 9 shows a fragmentary elevational view of a partially planarized integrated circuit surface in connection with another aspect of the invention.
• Fig. 10 is a top plan view of an integrated circuit wherein the decoding IC surface is exceptionally planar.
• Fig. 11 shows a top plan view of another embodiment of the invention wherein the decoding IC surface is not exceptionally planar.
• Fig. 12 shows a fragmentary edge view of an early stage in the inventive process showing the contact cuts through a non-conductive layer on top of the IC chip.
• Fig. 13 illustrates a partial top plan view of the device in the stage as shown in Fig. 12.
• Fig. 14 is a partial cross-sectional view in elevation taken along the line 14-14 shown in Fig. 15.
• Fig. 15 illustrates a partial top plan view of a further stage in the fabrication technique showing the trench photoresist.
• Fig. 16 is a partial cross section in elevation taken along the line 16-16 shown in Fig. 17.
• Fig. 17 illustrates a partial top plan view of a further stage in the fabrication technique showing the .trench etch.
• Fig. 18 is a fragmentary cross-sectional view in elevation taken along the line 18-18 shown in Fig. 19.
• Fig. 19 is a partial top plan view of a further stage in the fabrication technique showing the bottom electrode or trench metal deposition.
• Fig. 20 is a partial cross-sectional elevational view taken along the line 20-20 shown in Fig. 19, but at a further stage than the Fig. 19 stage, showing the results of the photoresist lift-off process.
• Fig. 21 is a view similar to Fig. 20 but at a further stage of the fabrication technique showing the spin-on glass application.
• Fig. 22 is a view similar to Fig. 21 but showing a further stage in the fabrication technique illustrating the trench assemblage following the plasma etching operation.
• Fig. 23 is a view similar to Fig. 22 but showing a further stage in the fabrication technique illustrating the silicon dioxide or silicon nitride deposition following the trench metal deposition and planarization. f
• Fig. 24 is a fragmentary cross-sectional elevational view taken along the line 24-24 shown in Fig. 25.
• Fig. 25 is a partial top plan view showing a further stage in the fabrication technique illustrating the cell definition cut.
• Fig. 26 is a partial cross-sectional elevational view taken along the line 26-26 shown in Fig. 27.
• Fig. 27 is a partial top plan view of a further stage in the fabrication technique after the KNO,, cap metal and silicon nitride deposition.
• Fig. 28 is a partial cross-sectional elevational view taken along the line 28-28 shown in Fig. 29.
• Fig. 29 is a partial top plan view of a further stage in the fabrication technique after the KNO_ cell top electrode definition.
• Fig. 30 is a partial cross-sectional elevational view taken along the line 30-30 shown in Fig. 31.
• Fig. 31 is a partial top plan view of a further stage in the fabrication technique showing the top metal stripe and circuit interconnections.
• Fig. 32 is a fragmentary enlarged cross-sectional elevational view of the KNO, cross section taken along the • line 32-32 shown in Fig. 31.
• FIGs. 1 and 2 there is shown an integrated circuit chip 1 with its input/output driving logic 2 covered by a protective layer 3, such as, for example formed of silicon dioxide.
• the first step in the novel process is to remove predetermined portions of the layer 3 of the integrated circuit 1 for providing contacts with the input output logic 2 of the integrated circuit 1. This is done by forming holes 4, 5, 6, 7, 8, 9 and 10 by well known photoresist and etching techniques.
• the next step is to deposit a first conductive layer which is then defined and cut by standard photoresist and etching techniques to form the first conductive layer portions 11-17 as shown in Fig.
• a ferroelectric layer 18 and the second conductive layer 19 are deposited during a single pumpdown, i.e., under vacuum conditions.
• the chips or wafers are then removed from the vacuum system.
• various photoresist steps are performed, such as to define the memory cells, to develop and to hard bake.
• the purpose of the hard baking is to harden up the resist material so that such material is very resistant and hard.
• the aforementioned machine may constitute a sputtering machine, in accordance with a preferred embodiment of the present invention the machine employed is an ion mill machine which will bombard the entire wafer or chip with ions to "etch" out all of the metal 19 and ferroelectric material 18 where desired.
• the ion milling procedure is carried out under vacuum conditioned or under a pumpdown. During this same pumpdown or vacuum condition, it is preferable to oxidize or ash off the remaining photoresist 20 (as shown in Fig. 3) which is indicated by the phantom line portion 25 in Fig. 4. In the preferred embodiment, this ashing off or oxidation step is performed in the ion milling machine under vacuum. A predetermined quantity of oxygen is bled into the machine, and the raw oxygen then attacks the photoresist 20.
• the photoresist 20 is similar to a plastic. The oxygen decomposes the plastic or resist 20, and the decomposition products are pumped out.
• a passivation layer such as glass 26 (see Fig. 6) is deposited over the chip 1.
• glass is evaporated over the entire wafer or chip. This also is done during the same single pumpdown or vacuum condition which prevails for the ion milling and ashing off process step mentioned hereinabove.
• the chips or wafers in the form partially illustrated in Fig. 4, are removed from the ion milling system or machine.
• the next step is to remove undesired portions of- the passivation layer 26. This is done by standard photoresist/etch techniques to open the top contacts to the cells, and to open the contacts to the • substrate pads for the top electrodes. As shown in Figs. 5 and 6, this photoresist/etching step produces the cut vias 27-45.
• a third conductive layer 47 over the entire chip to electrically connect the second conductive layer 19 to desired portions of the input/output circuit 2 of the integrated circuit chip 1. This is followed by photoresist/etching steps to define the top metal electrode to connect the top electrode to the substrate pads. This is best illustrated in connection with Fig. 7 and 8.
• Fig. 7 and 8 there are shown the bottom electrodes 12, 13 and 14 and the orthogonally arranged top electrodes 48, 49 and 50, such top electrodes being formed from the aforementioned deposited third conductive layer 47.
• the invention contemplates the optional step of passivation for the entire chip 1, and especially for the top electrodes in order to provide scratch protection. This may be done, if desired, by depositing another layer of a passivation material, such as glass and then to cut out those areas where bonding pads would be exposed. In other words, this may be done by placing a photoresist over the entire chip after the top passivation, and then cutting holes down to the bonding pads which would go out therefrom.
• a passivation material such as glass
• ferroelectric layer means any and all ferroelectric materials. However, such terms as used herein preferably refer to, but are not limited to,
• non-conductive material examples include, but are not limited to, silicon dioxide, silicon nitride, spin-on glass, sputtered and/or evaporated dielectrics, and other forms of glass.
• At least some ferroelectric memory arrays are sensitive to moisture contamination. Any topological flaws, passivation pinholes, etc., which allow moisture to come into contact with the ferroelectric material, such as the Phase III KN0-. film, can ultimately destroy the memory. It is therefore desirable to fabricate the ferroelectric array on top of a very planar surface.
• ferroelectric memory array in accordance with the present invention may be structured on top of the decode circuitry of the IC.
• Fig. 9 illustrates a partially planarized IC surface showing an IC chip 60 with conductors 61-64 on the decode circuitry of such IC chip 60.
• the conductors 61-64 may take the form of conductive polysilicon lines. 1 2
• Fig. 9 also illustrates a non-conductive material 65, which preferably, but not necessarily, may take the form of reflow glass.
• the reflow glass 65 is depicted with a somewhat undulating pattern to indicate a partially planarized IC surface.
• Fig. 10 illustrates a preferred embodiment of the present invention wherein the decoding IC surface is exceptionally planar. Bonding pads 66, 67 are disposed around the periphery of the decode circuitry 68 upon which the ferroelectric memory array would subsequently be constructed.
• the memory array may be structured over a substantially flat portion of the device in such a way that the decoding circuitry surrounds the ferroelectric memory array.
• Fig. 11 illustrates an alternate embodiment of the present invention wherein the decoding IC surface is not exceptionally planar.
• a ferroelectric memory array 69 would be disposed to be .surrounded by the decode circuitry 70.
• Bonding pads 71, 72 would be disposed around the periphery of the decode circuitry 70.
• the reflow glass 65 may preferably, but not necessarily, be CVD silicon dioxide which is heavily doped with phosphorous. Such a reflow glass 65 tends to flow or planarize at some temperature less than approximately 1000°C, depending upon the phosphorous content of the glass. The etch rate of the reflow glass 65 is also dependent on the phosphorous content of such glass. Subsequent glass (silicon dioxide or silicon nitride) depositions on top of the reflowed glass 65 can create a composite structure which etches non-uniformly because of the non-uniform doping profile throughout the composite layer.
• a layer of glass which is sufficiently thick to both planarize the surface 13 and provide sufficient dielectric isolation between the conductors 61-64 on the decode circuitry 68 and the bottom electrodes of the ferroelectric memory array to be constructed.
• Such thickness should preferably, but not necessarily, be 8 to 12KA. This thickness dimension . is shown in Fig. 12 as the thickness dimension of the composite non-conductive layer 73.
• a composite non-conductive layer 73 which may preferably, but not necessarily, consist of the reflow glass 65 and the above-mentioned subsequent glass (silicon dioxide or silicon nitride) depositions on top of the reflow glass 65.
• This composite layer 73 provides both the planarized surface and sufficient dielectric isolation between the conductors 61-64 and the bottom electrodes of the ferroelectric memory array to be constructed.
• a plurality of contact cuts or channels 74-80 are formed within and through the layer 73.
• contact cut 74 and 75 may be proyided for the bonding pads 66 and 67 of Fig. 10, or alternately for the bonding pads 71 and 72 of Fig. 11.
• Contact cuts 76 and 77 may be provided for the bottom electrodes of the ferroelectric memory array which are oriented substantially horizontally in Figs. 24, 26, 27, 28, 30 and 31.
• contact cuts 78, 79 and 80 are for connecting to the decode circuitry the top electrodes of the ferroelectric memory array which are oriented substantially vertically in Figure 31.
• the photoresist layer 81 has formed therein bottom electrode elongated openings 82 and 83; top electrode contact openings 84, 85 and 86; and bonding pad openings 87 and 88.
• etching operation is performed to provide the trenches as shown in the configuration illustrated in Figs. 16 and 17.
• the trench-forming operation results in trenches 89-95 all of which have substantially sloping side walls 97 which undercut the photoresist as shown, for example, at 96.
• a first conductive material such as metal 98
• metal 98 is deposited over the entire wafer and completely fills contact cuts 74-80, and partially fills trenches 89-95.
• the trenches 89-95 are filled at least to the height thereof, but empty spaces or voids are left between the metal 98 in such trenches and the sloping side walls 97 thereof.
• Fig. 19 is a partial top plan view which has been slightly modified to show the outline of the upper surface of the metal 98 which is for ed - in the trenches 89-95. An unmodified top plan
• the metal 98 is merely indicative of one or more conductive materials or metals which may be employed, depending upon the desired application.
• the material designated as metal 98 may consist of several layers -of various metals, such as, for example, a lowermost layer of aluminum, an intermediate layer of nickel, and an uppermost layer of gold. Various other combinations of metals may also be suitably employed.
• the configuration as shown in Figs. 18 and 19 is then subjected to a process for removing the patterned photoresist material 81 together with any metal 98 which has been deposited on such patterned photoresist material 81.
• This removal or photoresist or lift-off process leaves metal 98 only in the contact cuts 74-80 and trenches 89-95.
• An exemplary way of performing this removal step is by immersion of the wafer in a suitable solution, such as acetone, to lift-off the photoresist and the excess metal deposited thereon. The results of the photoresist lift-off process is best illustrated in Fig. 20.
• a second non-conductive material 99 such as spin-on glass
• the spin-on glass 99 may not only fill the voids in the trenches, but also provides a layer of non-conductive material over the entire assemblage.
• the surface of the wafer is planarized, for example, by plasma etching, back to the original surface 100 of layer 73.
• this layer 102 is then formed over the entire surface of the wafer.
• this layer 102 may take the form of silicon dioxide or silicon nitride.
• trenches 103-113 there are then formed in the non-conductive layer 102 a series of apertures in the form of trenches 103-113.
• trenches 103-113 have sloping side walls 115 which meet the upper surface of the metal 98 inwardly of the outer extremities of such upper surface as indicated at 114.
• the trenches 103-108 serve as the cell areas for the ferroelectric memory cells.
• the trenches 109-111 serve to open up the contact pads for the top electrodes.
• the trenches 112 and 113 serve to open up the bonding pads.
• a ferroelectric layer 116 which is preferably, but not necessarily, a thin film of Phase III KN0-; a cap metal 117; and an upper non-conductive layer 118, which is 16 preferably, but not necessarily, formed from either silicon dioxide or silicon nitride.
• the layers 116-118 are deposited preferably, but not necessarily, in vacuum in such a manner that the photoresist operation which is to follow will not convert or in any manner adversely affect the
• Fig. 27 is a top plan view which has been slightly modified to show the relative positions of some of the
• FIG. 27 An unmodified top plan view in Fig. 27 would merely show the ' upper surface of the non-conductive layer 118.
• the cap electrode photostep involves definition and etching of the silicon nitride layer 118 in such a way that, after photoresist removal, the pattern is transferred to the nitride layer 118.
• the wafer is then ion milled in vacuum so that the silicon nitride pattern is transferred to the underlying layers 117 and 116.
• the ion milling step removes the top nitride 118 completely, and etches the cap metal 117 and the KNO- layer 116 from all areas except those defined by the photopattern.
• This series of operations clears the bonding pads, the top electrode contacts, and overetches the lower silicon nitride layer 102 as shown at 119 in Fig. 28.
• the trenches 109-111 of the top electrode contacts, as well as the trenches 112 and 113 for the bonding pads, are cleared down to the top surface of the metal 98 as indicated, for example, by the surface 100 shown in Fig. 28.
• the cap electrode layer 117 is removed except for the metal caps 121.
• substantially vertical walls 122 are formed comprising the substantially vertical portions of the metal caps 121, the exposed edge 120 of the KNO-., and a vertical portion in layer 102 in the overetched area 119, all of which is most clearly represented in Fig. 32. 1 7
• a layer of metal may be deposited over the whole ' wafer while still under vacuum.
• the wafer may now be removed from vacuum and transferred to the next operation.
• This next operation may, for example, be a silicon nitride deposition or a photoresist operation. If silicon nitride or silicon dioxide is required to accomplish the subsequent photoresist and etch operations, then either of these materials may also be deposited under the same pumpdown or vacuum.
• the metal deposited in the previous operation may now be patterned using photoresist techniques. The resulting IC structure is shown in Figs. 30 and 31. In essence, this operation forms the top electrode metal stripes 123-125, and the circuit and bonding pad interconnects as shown at 126 and 127.
• Fig. 32 shows a cross section of the resulting KNO- cell. It is important to note that the overetch has removed the silicon nitride surface 102 down and away from the KNO.. edge as at area 119 so that the stripe metal 123 contacts the exposed edge 120 of the KNO- above the corner of the step. This avoids step coverage problems which otherwise would be likely to occur at this corner. In this manner, the K O, is removed from the problem area.
• scratch protect (passivation) glass and bonding pad (photoresist) cuts may follow, as required, to complete the IC structure.
• top electrodes 123-125 encapsulate their associated KNO- cells, and at the same time form the interconnects to the underlying decode circuitry.

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• 1986
  • 1986-01-24 EP EP19860901195 patent/EP0211888A4/fr not_active Withdrawn
  • 1986-01-24 AU AU53940/86A patent/AU588856B2/en not_active Ceased
  • 1986-01-24 WO PCT/US1986/000159 patent/WO1986004447A1/fr not_active Application Discontinuation

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