Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
  • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
  • H10D84/619—Combinations of lateral BJTs and one or more of diodes, resistors or capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P36/00—Gettering within semiconductor bodies
  • H10P36/03—Gettering within semiconductor bodies within silicon bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/62—Capacitors having potential barriers
  • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants

Definitions

• This invention relates in general to structures and fabrication methods for providing an intern 3 .l shield to protect depletion regions of semiconductor devices from discharge by ionizing radiation or particles, or other spurious carriers and, more particularly, to improved means and methods for shielding the depletion region of dynamic charge storage devices to prevent undesirable discharge thereof by ionizing radiation or particles absorbed within the device substrate or by carriers injected or pumped from nearby regions.
• Charge storage is a frequently used technique in semiconductor devices and integrated circuits. Examples of devices whose operation depends critically on charge storage are dynamic random access memories, bucket brigade shift registers, and charge coupled imaging devices. Many other kinds of semiconductor devices and integrated circuits also use charge storage. Depletion region charge storage may be accomplished using a physical P-N junction formed by abutting doped P and N regions. However, depletion regions may also be induced, as for example, by means of an MOS capacitor or the like. If a sufficiently large voltage is applied across an MOS capacitor or equivalent, a depletion region akin to that found in a P-N junction is created between the semiconductor surface and the bulk. Such induced depletion regions can equally well be used for charge storage devices.
• reference to storage of charge on junctions is intended to include charge stored in depletion regions whether formed by a permanently doped P-N junction or field induced or by formed by any other means.
• a significant problem that arises in connection with the use of charge storage is that the stored charge is subject to being discharged by minority carriers or electron-hole carrier pairs which reach the depletion region. These free carriers may arise from a number of sources, such as, generation within the junction region, injection from another nearby junction, or diffusion from outside the junction region, i.e., from within the bulk of the underlying semiconductor substrate.
• the result of the discharge is that the information represented by the stored charge decays. If discharge is severe, the information stored in the form of charge may be lost entirely. As a consequence, the charge representing the stored information must usually be periodically refreshed. The greater the number of free carriers created within or reaching the charge storage depletion region per unit time, the more frequently this stored information must be refreshed, that is, the lost charge replaced.
• Thermal carrier generation within the depletion region can dissipate the stored charge.
• Thermal carrier generation and carrier lifetime are related. In order to minimize thermal carrier generation in the depletion region, the carrier lifetime must be made as long as possible. Thus, great effort is expended to obtain long lifetime material in which to form the depletion regions used for charge storage. However, the longer the lifetime, the greater the probability that carriers from elsewhere in the device, e.g., carriers generated in the underlying substrate or injected from nearby junctions, will diffuse into the depletion region and discharge the stored information. Thus, conflicting requirements are encountered when trying to reduce all sources of carriers which might contribute to dissipating the stored charge and thereby requiring more frequent refresh. Ionizing radiation and particles absorbed within a semiconductor material produce free carriers by ionization.
• the depletion region of a charge storage device is relatively thin so that few ionizing events occur directly therein. Further, the depletion region is often located near a device surface, so that only comparatively low energy radiation or particles are likely to be absorbed there. These low energy particles can be easily filtered out by surface protection layers and so are readily avoided. However, the more energetic particles or radiation will pass through the surface layers and be absorbed in the bulk of the substrate. The carrier pairs freed by ionizing events occurring in the substrate can readily diffuse to the depletion region if the semiconductor "substrate has a high lifetime. It has been found that these bulk generated carriers are a significant cause of low storage times in many types of charge storage devices.
• One method for reducing the discharging effect of in-diffusing carriers is to reduce the bulk lifetime so that more of the bulk generated carriers recombine before reaching the depletion region of the storage device.
• Two methods of carrier lifetime control which are commonly used in silicon devices, for example, are electron bombardment and gold doping. Electron bombardment is believed to reduce lifetime by introducing defects in the crystal lattice. A disadvantage of using bombardment induced lattice defects for lifetime control is that such defects anneal out during subsequent high temperature processing steps.
• Gold doping is another means of controlling lifetime. However, gold doping is incapable of the necessary spatial resolution. For example, gold diffuses so rapidly in silicon at ordinary process temperatures that it travels throughout the entire wafer thickness in a very brief time. Further, the amount of lifetime reduction that can be obtained by these methods is often insufficient to prompt recombination of all in-diffusing carriers.
• Another method which has been suggested for providing lifetime control structures is to start with a low lifetime substrate and attempt to grow thereon a high lifetime surface layer in which the charge storage devices would be fabricated.
• this has not proved practical because of the tendency of the substrate to contaminate or create defects in the epi- layer, thereby reducing its lifetime.
• argon has been investigated as a means of obtaining localized reduction in lifetime.
• the lifetime reductions from ion implanted argon appear to be primarily related to physical damage to the crystal lattice.
• the effect is significantly annealed by post implant heating. This is a substantial disadvantage since practical device fabricated methods generally require that the treated wafer be heated to high temperatures during subsequent fabrication steps.
• a means for forming radiation shielded charge storage devices comprising, a semiconductor substrate having first and second major surfaces, a high lifetime region adjacent the first major surface and adapted for containing one or more charge storage devices, a low lifetime region in the semiconductor substrate underlying the high lifetime region, wherein the low lifetime region contains reactive ions which form carrier recombination centers. It is essential that the lifetime killing impurities be implanted to dose levels which exceed the solid solubility limit of the impurities in the substrate material. It is desirable that the low lifetime region comprise a planar region of predetermined thickness which is small compared to the separation of the first and second major surfaces, and which is located substantially parallel to the first major surface.
• the low lifetime region is preferably formed by implantation of lifetime killing impurity ions not from the third or fifth columns of the periodic table.
• Oxygen ions implanted to a concentration exceeding about 30 parts per million atomic and a dose exceeding 1x10 per square centimeter are useful for forming the low lifetime region.
• a process for forming radiation shielded charge storage devices comprising, providing a semiconductor substrate having a major surface and a first region adjacent to that surface which is adapted for containing charge storage device regions, implanting a second region beneath the first region with lifetime killing reactive impurity ions to a dose exceeding the solid solubility limit of the reactive impurity ions in the substrate at the melting temperature of the substrate, and heating the implanted substrate to a first predetermined temperature to chemically react the impurity ions with the substrate material to form a stable zone of reduced carrier lifetime in the second region.
• Charge storage devices may be formed in the first region before the implanting step, after the heating step, or between the implanting and heating step. It is desirable that the implanting step include implanting the lifetime killing reactive impurity ions to a dose exceeding the solid solubility of the lifetime killing impurity ions at the melting temperature of the substrate by at least one order of magnitude.
• the surface of the substrate may conveniently be covered by an epitaxial layer suitable for construction of charge storage devices before or after implantation of the lifetime killing reactive impurity ions.
• Oxygen is a suitable material for use as a reactive lifetime killing impurity ion.
• Carbon may be provided in the substrate to act as a nucleation center for controlling the reaction of the implanted oxygen ions.
• oxygen is used in silicon, it is desirable that the oxygen ions be implanted to a dose exceeding 1x10 per square centimeter and/or to a
• FIG. 1 shows a simplified schematic cross-sectional view of a po'rtion of a semiconductor substrate containing charge storage device regions, according to the prior art
• FIG. 2 shows a simplified schematic cross-sectional view of a portion of a semiconductor substrate containing charge storage device regions, according to the present invention
• FIG. 3 shows a simplified schematic cross-sectional view of a portion of a semiconductor substrate containing charge storage device regions and a bipolar device region, according to a further embodiment of the present invention
• FIG. 4 shows a simplified schematic cross-sectional view of a portion of a semiconductor substrate containing charge storage device regions according to a further embodiment of the present invention
• FIGS. 5A-I show simplified schematic cross- sectional views of a portion of a semiconductor substrate having charge storage device regions, during various stages of manufacture and using alternative manufacturing sequences, according to the present invention
• FIG. 6 shows calculated values for the expected oxygen concentration in silicon as a function of depth from the surface of the substrate for various implant energies and doses
• FIGS. 7A-B show plots of the normalized effective lifetime as a function of depth from the surface of the substrate for different implant doses of oxygen; and FIG. 8 shows plots of leakage current (I) versus depletion depth (w), and rate of charge of leakage current with depletion depth (dl/dw) versus depletion depth (w), for an N P diode in an epitaxially coated oxygen implanted silicon substrate.
• FIG. 1 shows portion 10 of semiconductor substrate 11 which has therein charge storage device regions 12 and 14.
• Charge storage device region 12 is doped to a conductivity type opposite that of substrate 11 so that a P-N junction exists between device region 12 and substrate 11.
• MOS structure 14 consists of metallic electrode 14a covering dielectric 14b which rests on substrate 11. When appropriately biased, MOS structure 14 depletes the portion of surface llu of substrate 11 underneath electrode 14a to form depletion region 14d having width 14e.
• Depletion region I4d results from charge applied to electrode 14a or charge trapped within dielectric region 14b. Depletion region 14d is induced by this applied or trapped charge. When the applied or trapped charge is removed, depletion region 14d disappears.
• Doped region 13 having a conductivity type opposite substrate 11 is also provided to illustrate the interaction of nearby junctions with charge storage devices 12 and 14.
• the lifetime of the free carrier pairs created by the ionization events is large enough, they can diffuse across distance 16 and reach depletion regions 12a or 14d, where they will contribute to discharging any charge which has been stored on device regions 12 or 14. It is well-known in the art that free carriers generated within substrate 11 by absorption of energetic particles or ionizing radiation, are a significant cause of stored information loss in semiconductor charge storage devices. The greater the carrier lifetime in substrate 11, the larger is carrier diffusion length 16, and the greater the probability that an ionization event creating free carriers will occur within a diffusion length of the depletion layers.
• Argon diffuses less rapidly than gold in silicon, but is also not a practical lifetime killer for forming an effective free carrier recombination region since the decrease in lifetime obtained with argon, while initially a factor of about 10 , is reduced after heating of the implanted wafers to about 10 . This is insufficient to provide adequate shielding. Further, neither gold or argon react chemically with most semiconductor materials so the lifetime killing complexes formed by these materials are inherently unstable.
• nearby junction 13 A further mechanism which adversely affects the behavior of charge storage devices is illustrated by nearby junction 13.
• nearby junction 13 When nearby junction 13 is forward biased, minority carriers will be injected into substrate 11, as indicated by arrows 13a. Since, the material surrounding the charge storage devices must be high lifetime material, an appreciable fraction of injected carriers 13a may reach depletion regions 12a and 14d of charge storage devices 12 and 14 and cause discharge, just as do the carriers produced in the bulk by ionizing particles or radiation 15a-b. Similar effects may be produced by conductors running across the surface of substrate 11 and by other device regions through a phenomena called charge-pumping. When the voltage on these conductors or devices is varied, as for example during memory write or read operations, minority carriers may be injected into the near surface regions containing the charge storage devices.
• Dynamic random access memories are particularly susceptible to such phenomena which frequently manifest themselves as row or column disturb effects. Hence, shielding charge storage devices from such phenomena and effects is particularly important.
• FIG. 2 shows portion 30 of semiconductor substrate 31 in which have been constructed charge storage device regions 12 and 14. Ray 15 indicates either ionizing particles 15a or radiation 15b.
• Junction 13 has the same function as described in connection with Fig. 1.
• Charge storage devices 12 and 14, and junction 13 are constructed in zone 31a of substrate 31 adjacent surface 31u.
• Substrate 31 is chosen to be a high lifetime material so that zone 31a also has this property. This insures that the recombination-generation currents present in devices 12 and 14 will be extremely low and that devices 12 and 14 will inherently have good charge storage properties.
• very low lifetime zone or region 31c is placed immediately beneath device zone 31a. It is desirable that thickness 32a of device zone 31a be as small as possible consistent with the requirement that depletion regions 12a and 14d associated with devices 12 and 14 do not expand to contact low lifetime region 31c.
• very low lifetime zone 31c By placing very low lifetime zone 31c close to doped region 13, very low lifetime zone 31c also serves as a sink to absorb a large fraction of carriers 13a injected from doped region 13 into substrate 31. This reduces the sensitivity of charge storage devices 12 and 14 to minority carriers injected from nearby junction 13 or from adjacent charge pump regions which behave in a similar way with respect to injecting minority carriers into the surface regions of the device structure.
• zone or region 31c In order for zone or region 31c to be effective in shielding charge storage devices 12 and 14 from the effects of carriers generated by ray 15 or injected from region 13 or injected by charge pumping, it is essential that the lifetime in region 31c be extremely short.
• the density of recombination centers in region 31c must be so high that virtually all free carriers entering region or zone 31c recombine before reaching the charge storage devices.
• a very high density of permanent lifetime killing impurities can be created in a narrow zone within substrate 31, such as in width 32c of region or zone 31c, by implanting reactive lifetime killing impurities to a concentration which significantly exceeds the normal solid solubility limit of the impurity in the substrate material.
• oxygen atoms can be implanted into a silicon wafer in a band 1-2 microns thick located a micron or more belo the surface and with a super-saturated peak concentration substantially exceeding the solid solubility limit of oxygen in silicon at the melting temperature of silicon.
• such a super-saturated oxygen zone can be produced at a controlled depth within the substrate without destroying the single crystal nature of the substrate surface, or causing such a high density of surface defects as to preclude the construction of high quality charge storage devices in the overlying material.
• the super-saturated oxygen zone is stable during subsequent heat treatments so that post- implant high temperature processing steps do not cause significant annealing, that is, the very low free carrier lifetime in the super-saturated oxygen zone does not decrease or go away on post-implant heating.
• the stability of the super-saturated oxygen zone is believed to be due to the ability of the oxygen to react chemically with the semiconductor material to form a stable SiO ⁇ phase.
• This stable SiO ⁇ phase is highly localized and extremely finely divided and, because of the super-saturated oxygen concentration, cannot re- dissolve in the semiconductor crystal during subsequent heating steps.
• the free carrier lifetime in zone 31c can be reduced significantly below that which would otherwise be obtained by other means, as for example, by the reaction or activation of impurities already in solution within the crystal, or by use of impurities introduced by diffusion.
• the concentration of impurities ordinarily in solution is limited by the solid solubility of that impurity in the substrate at the melting point of the substrate. Any further amounts dissolved in the melt segregate out on solidification.
• zone 31c is buried within substrate 31 beneath high lifetime zone 31a in which charge storage devices can be constructed.
• Very low values of effective lifetime e.g. 15 to 200 picoseconds
• these highly concentrated complexes formed from the semiconductor and the implanted ions act to shield charge storage devices 12 and 14 from the electron-hole carrier pairs generated by ray 15 absorbed within bulk portion 31b of substrate 31, or from minority carriers injected from region 13 or introduced by charge pumping.
• FIG. 3 shows a simplified cross-sectional diagram in schematic form of portion 50 of substrate 51 having upper surface 51u containing charge storage devices 12 and 14, and conventional bipolar device 53.
• Conventional bipolar device 53 comprises isolation walls 53a, buried layer region 53b, collector region 53c, base region 53d, and emitter region 53e.
• Ion implanted low lifetime carrier shield zone 51d of thickness 52d extends laterally only to point 51e, and does not extend into the region occupied by bipolar device 53. This lateral localization of carrier shield 51d is readily accomplished by masking off the portion of substrate 51 intended to contain bipolar device 53 during implantation of carrier shield 51d.
• FIG. 4 shows, in simplified schematic cross-sectional form, portion 60 of semiconductor substrate 61 having upper surface 61u.
• Low lifetime shield region 61d produced by ion implantation is located in substrate 61, and serves to protect charge storage devices 12 and 14 from free carriers generated by ionizing events occurring within bulk portion 61b of thickness 62b of substrate 61.
• _ . -. epitaxial layer 63 is grown on surface 61u of substrate 61, and devices 12 and 14 constructed in surface 63u of layer 63.
• layer 63 have thickness 63a sufficient to contain the depletion regions of devices 12 and 14, since layer 63 can potentially be formed with great perfection. This improves the characteristics of devices 12 and 14. In order that layer 63 have great perfection, it is desirable that epitaxial layer 63 be separated from carrier shield zone 61d by region 61a of thickness 62a.
• thickness 62a must be of sufficient size so as to preclude the generation of implantation defects in surface 61u which might propagate into epi-layer 63. A distance of 0.5 to 1 micron has been found to be adequate for thickness 62a.
• FIGS. 5A-I show simplified schematic cross- sectional views of portion 70 of semiconductor substrate 71 containing devices 12-14 fabricated according to the methods of the present invention, at various stages of completion, and according to various alternative methods of fabrication.
• charge storage device regions 12 and 14 are formed in surface 71u of substrate 71 (FIGS. 5A-B) by means well-known in the art.
• ions 74 are implanted through device regions 12 and 14 to produce buried layer regions 71c of width 72b at depth 72a below surface 71u, to act as a free carrier shield (FIG. 5C).
• Oxygen has been found to be a suitable material for forming free carrier shield region 71c in silicon.
• the depth of shield region 71c below surface 71u can be varied by varying the implant energy (see FIG. 6).
• the implant energy see FIG. 6
• the center of the implanted oxygen distribution is located about one micron below surface 71u.
• the center of the implant distribution is approximately two microns below surface 71u, and at 3,500 keV the center is about four microns below surface 71u.
• the width of the implanted distribution at a particular concentration level depends upon the energy and total dose. Profiles of concentration versus depth from the surface for various implantation energies and doses are shown in FIG. 6. The profiles of FIG.
• FIGS. 5D-E illustrate an alternative sequence for the construction of the means of the present invention.
• lifetime killing impurity ions 74 are implanted in substrate 71 (FIG. 5D) to form low lifetime shield region 71c of width 72b lying beneath high lifetime region 71a of thickness 72a in substrate 71.
• charge storage device regions 12 and 14 are formed in surface 71u of substrate 71 (FIG. 5E) using conventional techniques. This is a preferred procedure.
• FIG. 51 The finished structure is illustrated in FIG. 51 wherein substrate 71 has thereon epitaxial layer 73 of thickness 73a in which are fabricated charge storage device regions 12 and 14.
• Low lifetime carrier shield region 71c of width 72b is located in substrate 71 below undisturbed region 71a of width thickness 72a.
• Means for obtaining the structure of FIG. 51 are illustrated in FIGS. 5F-H.
• bare substrate 71 FIG. 5A
• Epitaxial layer 73 is then applied to surface 71u of substrate 71, as illustrated in FIG. 5F.
• bare substrate 71 (FIG. 5A) is coated with epitaxial layer 73 prior to formation of buried low lifetime shield layer
• the epitaxially coated substrate is then implanted with ions 74 to produce buried low lifetime shield layer 71c, as illustrated in FIG. 5H.
• the differences in implant energy are necessary to take into account the differences in the thickness of material which ions 74 must penetrate so as to be deposited in region 71c at depth 72a below surface 71u of substrate 71 or depth 72a + 73a below surface 73u of layer 73, depending upon whether the implantation is performed before or after formation of layer 73.
• low lifetime shield region 71c may be implanted within substrate 71 with the center of the implant region located approximately from about 0.5 to 5 or more microns below surface 71u. Tests sho that this can be accomplished without substantial degradation of the properties of overlying region 71a. This is important, since if region 71a is adversely affected by the implantation of region 71c, charge storage devices 12 and 14 fabricated in layer 71a will be adversely affected and their properties degraded. Similarly, if region 71a is adversely affected by the implantation of region 71c, overgrown epi-layer 73 will also be degraded.
• Polished dislocation free silicon wafers were utilized for the measurements.
• Oxygen implantation at 400 keV was carried out in an Extrion Type 400-10 implanter using 0 + ions derived from an O2 source. The total beam current was about 100 micro-amps of 0 + of which about 60% stuck the wafer.
• the Extrion implanter is manufactured by the Extrion Division of Varian, Inc., Glouster, Mass. Implants at 3,500 keV were carried out in a General Ionex Tandetron implanter using a
• Duoplasmatron Source supplied with O2 gas. Beam currents were about 2 micro-amps of 0 , substantially all of which struck the wafer. Implantation on the General Ionex implanter was obtained through Universal Energy Systems of Dayton, Ohio. Typical implant doses and energies are shown in Table I. The implants were 1 generally made into bare silicon wafers. However, samples SW5-A and B were covered with a 0.02 micron oxide layer prior to implantation. This oxide layer is too thin to have any appreciable affect on the ion 5 penetration depth. No attempt was made to control the wafer temperature during implantation. After implantation the wafers were heated as shown in Table I in order to react the oxygen with the silicon substrate material to activate the recombination centers and form
• the oxygen implants were carried out before the test diodes and MOS capacitors were formed. Where epitaxial layers were utilized, the oxygen implants were generally made prior to forming the epitaxial layer. The epitaxial layers,
• diodes, and MOS capacitors were formed using conven ⁇ tional techniques well known in the art.
• Diodes and MOS capacitors analogous to device regions 12-14 of FIG. 3 were formed according to the general procedure outlines in connection with FIGS. 5A-
• oxygen implanted P-type silicon wafers were oxidized at about 1000 °C in oxygen to form a surface oxide layer for masking purposes.
• a photoresist layer was applied to define openings in the surface oxide
• N + P diodes were formed by conventional diffusion at about 950 °C using a phosphorous dopant.
• the wafers were reoxidized at 900 °C and 1050 °C to form a gate oxide for the MOS capacitors.
• a metal layer was
• SW5-B 400 1X10 16 2xl0 20 4 5 30 @ 1050 ]
• the entries in the column labeled "EPI THICK” are the thickness of any epi-layer overlying the implanted wafer.
• the "PEAK DEPTH” shown in Table I is the estimated depth below the surface, of the peak of the implant concentration profile, including any overlying epi-layer. Where an epi-layer was used the test devices were built in the epi-layer. For the samples of Table I, the implant depth and the epi-layer thickness were varied in tandem so that the implant profiles were located about 4 to 5 microns below the surface in which the test devices were fabricated. This procedure allowed reasonably direct comparison of non-epi and epi- layer results.
• the implant penetration depths and the concentration profiles were calculated using methods well known in the art for estimating the stopping distances of implanted ions and the resulting profiles. The results of these calculations are shown in detail in FIG. 6. It should be noted that the peak oxygen concentrations obtained by the method of the present invention and shown in Table I are substantially above the solid solubility limit of oxygen in silicon, which
• 1 Q is about l-2xl0 xo per cm .
• Table I the wafers of Table I were subjected to further post-implant heating during the formation of the test diodes and MOS capacitors. These further heating cycles were: 90-165 min. at 1000 °C for initial oxidation; 25 min. at 950 °C during phosphorous diffusion; 75-115 min. at 900 °C during reoxidation; and 135 min. at 1050 °C for gate oxidation.
• the wafers coated with epitaxial layers were subjected to an additional heating cycle of
• FIGS. 7A-B show the effective lifetime calculated from the I-V characteristics of the N + P diodes, normalized to the lifetime at the surface, plotted as a function of depth into the structure, for the samples of Table I.
• the effective generation lifetimes calculated from the I-V characteristics were checked against values determined from relaxation time measurements on adjacent MOS capacitors. Agreement was generally good.
• the peak of the oxygen implant distribution is estimated as lying four to five microns beneath the surface of the structures.
• the effective lifetime at the surface was determined separately to be approximately 150 microseconds.
• FIGS. 7A-B are labelled to indicate their correspondence to the values in Table I. All of the curves of FIGS. 7A-B trend toward the surface lifetime value of 150 microseconds at zero bias depletion depth. Note that the depletion region depth is given on the scale at the bottom of the FIGS. 7A-B and the depth from the surface is give on the upper scale of the FIGS. 7A-B . Both depths are measured in microns.
• FIGS. 7A-B show that at a dose of about 3x10 ions- per square centimeter, the effective lifetime drops-off from a surface value of approximately 150 microseconds to a value of less than 150 nanoseconds. This is a lifetime reduction ratio in the range of 10 ⁇ J to 10 " .
• the higher the dose the more the lifetime is reduced in the implanted zone.
• the effective lifetime drops-off from the surface value of about 150 microseconds to a range about 5 to 200 picoseconds. This is an apparent reduction ratio of as much as 10 " .
• the method of the present invention provides an extremely low lifetime region buried beneath an undisturbed surface layer.
• the data presented in FIG. 7A corresponds to samples without epi-layers implanted using 3,500 keV oxygen ions.
• the peak of the implant distribution is expected to lie about 4 microns below the surface, and the half-width at a concentration of about 10 18 per cm J is estimated to be about 1 micron for a dose of lxlO x -' per cm , and about 1.5 microns for a dose of 1x10 per cm .
• significant reduction in the lifetime should be observed at about 3 microns depth from the surface for doses above about lxlO 1 - 5 per ci and at about 2.5 microns for doses approaching 1x10 per cm 2 .
• the drop off in lifetime plotted in FIG. 7A corresponds reasonably well with these predictions, with the curves for higher doses showing a more rapid drop at smaller depths, as would be expected.
• the data of FIG. 7B corresponds to samples implanted at 400 keV and overcoated with an epi-layer about four microns thick.
• the calculations of FIG. 6 show that the widths of the oxygen implants made at 400 keV are substantially smaller than those made at 3,500 keV.
• the drop-off in lifetime in FIG 7B should take place at a greater depth from the surface and be more gradual, as compared to FIG. 7A. This is what is observed. This indicates that the depth of the implanted distribution below the surface can be controlled by varying the implant energy or the epi- layer thickness or both.
• the very low values of lifetime for the implanted region and the very large lifetime reduction ratios observed in these samples are measured after the wafers have been extensively heated, both to activate the implanted oxygen, as will be discussed in more detail later, and also in connection with the fabrication of the epitaxial layers and the test devices after the implants were performed.
• the means and method of the present invention, of implanting a super-saturated layer of reactive ions is not subject to any significant tendency for the lifetime reduction centers to anneal out during post implant heating. This indicates that the very low lifetimes obtained by the present invention are extremely stable. This is a highly desirable property.
• the implanted oxygen zone may be observed directly by measuring the leakage current of the N P diodes at different values of bias.
• FIG. 8 for sample Number SW1-A which was implanted at
• the solid curve in FIG. 8 is a plot of leakage current (I) versus depletion depth (w).
• the depletion region width is varied by varying the bias voltage.
• a log-linear scale is used in FIG. 8. Near zero volts bias, the depletion region is so thin that it does not extend into the implanted oxygen zone underlying the diode.
• the leakage current is very low under these conditions, e.g., about 10 ⁇ i ⁇ amps.
• the fact that the leakage current is so low is further evidence that the surface layers above the implanted region have not been damaged by the implant process, or at least that any damage which may have been created did not propagate into the epi-layer in which the test devices were formed.
• the bias on the diode is increased, the depletion region expands and the leakage current increases. So long as the depletion region does not touch the low lifetime (high thermal generation rate) implanted zone, the leakage current increases relatively slowly.
• the dashed curve in FIG. 8 shows the slope (dl/dw) of the I-w plot as a function of depletion depth. A large peak is observed corresponding to the point where the depletion region passes through the buried low lifetime implant region. This peak, indicated by the star on the dashed curve, was calculated to be 4 microns below the junction and about 5 microns below the surface.
• the curves of FIG. 8 provide direct observational evidence that the low lifetime shield region or zone, formed according to the teaching of the present invention, does not perturb or damage the surface of the implanted substrate or epi-layer, that it is very narrow, and that it provides a very large density of deep recombination-generation centers.
• a feature of the present invention is that the low lifetime shield region may be localized both in area and depth. Area localization is accomplished by masking the surface of the wafer during implantation, for example, by using a heavy layer of resist or other implant resistant material. In this way, the lifetime killer ions forming the free carrier shield zone can be implanted in one area of the wafer and not in another.
• the depth of the implanted zone can be varied by adjusting the implant energy and/or the epi-layer thickness.
• the minimum depth is set by the requirement that the device depletion layer not penetrate into the shield region.
• the maximum depth can be varied over a range of many microns by using higher energy implants and/or thicker epi-layers.
• maximum shielding effect is obtained when the shield zone is kept as close as possible to the depletion layer without touching.
• charge storage device structures which employ a shallow low lifetime shield region in a substrate, which is then -coated by an overlying epi-layer, are expected to give better performance, and are preferred.
• the lifetime killing action of the implanted impurities is stable if the substrate is heated during or after implantation to react the implanted impurities with the substrate material and form chemically bonded complexes which provide a rich abundance of deep recombination centers. This process is generally referred to herein as activation.
• Implanted oxygen in silicon is believed to form SiO ⁇ complexes. These complexes have been observed using transmission electron microscopy and appear to be very finely divided, e.g., about 100 Angstroms (10 ⁇ ° m) in size. The complexes are surrounded by larger dislocations.
• the concentration of the implanted impurities must be above the solid solubility limit of the ion in the semiconductor material.
• the activation heating may be performed in any type of heating means.
• activation heating was carried out in an ordinary tube furnace of the type commonly used for diffusion or oxidation of semiconductors such as silicon, generally in a nitrogen atmosphere. The times and temperatures are indicated in Table I.
• a model IA-2000 Rapid Isothermal Annealing (RIA) apparatus manufactured by Varian-Extrion of Glouster, Massachusetts is suitable.
• the implanted wafer or substrate is placed in a vacuum chamber in the RIA apparatus where it is thermally isolated and separated by a shutter from a hot heater block held at a high temperature, for example, 900-1300 °C.
• a shutter is rapidly moved aside so that the wafer is suddenly exposed to the high temperature radiation from the heater. Since the thermal mass of the wafer is small its temperature rises very rapidly.
• An optical pyrometer located behind the wafer is used to measure its temperature.
• the RIA apparatus permits a wafer to be heated from room temperature to 900-1300 °C and cooled back to the vicinity of room temperature in a matter of a few seconds or tens of seconds. For example, heating to over 1100 °C in 5-30 seconds and dropping back below about 800 °C in another 5-30 seconds can be achieved.
• This treatment is particularly desirable for activation of implanted lifetime killing impurity ions, since it provides activation without allowing time for substantial thermal diffusion which can cause the implanted impurity distribution to spread out.
• an impurity must provide deep recombination centers, i.e. recombination levels located in the vicinity of the middle of the forbidden energy gap of the semiconductor material being used. The action of deep centers or levels in promoting carrier recombination is described by A. S.
• Oxygen for example is a weak N-type impurity but is still suitable. Nitrogen is also expected to be a useful element as a lifetime killer even though located in column 5a, since it is not believed to be a strong dopant atom in silicon but is expected to provide deep recombination levels.
• impurities which diffuse very rapidly and at relatively low temperatures are not useful, since during subsequent heating steps they can spread into the surface portions occupied by the depletion regions of the charge storage devices. This will increase the leakage currents in the charge storage devices and degrade their charge storage properties.
• Gold is an example of a material which provides deep recombination centers, but has too high a diffusivity.
• lifetime killer impurities which have values of diffusivity D corresponding to (D) ' > 50 microns per square root hour, in the temperature range of interest for device fabrication, that is, 900-1300 °C, are not expected to be useful.
• impurities or particles which provide deep recombination centers mostly by virtue of the lattice damage they create during implantation or by formation of unreacted precipitates (e.g., gas bubbles), are less desirable because of the tendency of the lifetime killing effect to anneal away during subsequent heating.
• Noble gases are examples of this type of impurity.
• Argon in particular is known to provide thermally annealable recombination centers. Such materials generally do not form stable chemically bound complexes with the substrate material.
• impurity ions suitable for use in forming a free carrier shield region according to the present invention must be chosen from among the elements which provide deep recombination centers or levels, which react chemically with the substrate material so as to form bound complexes which do not substantially re- absorb or anneal out during subsequent heating, and which do not have a diffusivity so high as to preclude maintaining the implanted ions in a predetermined zone within the semiconductor substrate under the temperatures required in subsequent device manufacturing and use. Further it is desirable to chose elements from among those which do not provide a high density of shallow donor or acceptor levels. For silicon, materials having a diffusivity satisfying the relation (D) 1 x/ / i 2 i > 50 microns per square root hour in the range
• carbon in silicon affects the propensity of oxygen to precipitate from solution and form deep recombination levels. The exact mechanism by which this occurs is not clearly understood. Nevertheless, carbon provides a useful means of controlling the nucleation and reaction of lifetime killing impurities such as oxygen.
• carbon is implanted in the semiconductor substrate to stimulate the localized nucleation and reaction of dissolved or implanted oxygen or other reactive lifetime killing impurity. When carbon is present, the oxygen preferentially reacts on or near the carbon, rather than nucleating and reacting at random. Hence, the carbon allows greater control of the distribution of the lifetime killing complexes within the substrate.
• carbon may be first implanted and then oxygen or another lifetime killing impurity implanted subsequently, using the carbon implanted region for purposes of promoting the nucleation and activation of the later implanted oxygen or other lifetime killer.
• Carbon may also function as a recombination center itself.
• the invention provides an improved means and method for shielding charge storage devices in semiconductor substrates from the deleterious effects of incident radiation or particles, or from carriers which may be injected from nearby junctions or by charge pumping. It is further apparent that the invented means and method provides a very low lifetime free carrier shield zone or region immediately beneath a high lifetime surface layer suitable for construction of charge storage devices. Additionally, the concentration of lifetime killing impurities which can be provided in the carrier shield zone is very large, being at least an order of magnitude greater than the normal solid solubility. As a consequence, the lifetime reduction ratios obtained by the present invention in the carrier shield region are also very large, e.g. as much as 10 or more.
• the lifetime killing properties of the shield layer are stable with time and temperature. Additionally, the present means and method permits the carrier shield region to be localized both laterally, so as to encompass only those device regions where it is desired, and in depth so as to permit optimum adjustment of the shielding effect. Further, the low lifetime carrier shield region can be buried in the device substrate without deleterious effect upon the lifetime in the overlying surface regions or- epitaxial layers which may be grown on the surface of the implanted substrate.

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• 1985
  • 1985-08-12 KR KR1019860700312A patent/KR860700314A/ko not_active Withdrawn
  • 1985-08-12 EP EP19850903970 patent/EP0197948A4/de not_active Withdrawn
  • 1985-08-12 JP JP60503547A patent/JPS62500340A/ja active Pending
  • 1985-08-12 WO PCT/US1985/001523 patent/WO1986002202A1/en not_active Ceased

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