EP0177560A1 - Composants additionnels de circuit integre - Google Patents

Composants additionnels de circuit integre

Info

Publication number
EP0177560A1
EP0177560A1 EP85901777A EP85901777A EP0177560A1 EP 0177560 A1 EP0177560 A1 EP 0177560A1 EP 85901777 A EP85901777 A EP 85901777A EP 85901777 A EP85901777 A EP 85901777A EP 0177560 A1 EP0177560 A1 EP 0177560A1
Authority
EP
European Patent Office
Prior art keywords
network
integrated circuit
electrical
dielectric
device includes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85901777A
Other languages
German (de)
English (en)
Inventor
Wayne A. Mulholland
Daniel J. Quinn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of EP0177560A1 publication Critical patent/EP0177560A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the field of the invention is that of a combination of an integrated circuit with another integrated circuit and/or with one or more components.
  • the invention relates to a combination of an integrated circuit, having a contact surface that includes a number of contacts set in a relatively thick protective top layer, with one or more additional devices.
  • the additional devices may be discrete passive devices, such as resistors, capacitors, inductors, or connectors; simple active devices, such as power transistors or different technology transistors; or complex devices, such as a second integrated circuit or an optical device.
  • a feature of the invention is the combination of a MOS or CMOS first circuit with a bipolar second circuit, for use in applications, such as telecommunications, that require different voltage levels or higher power devices.
  • Another feature of the invention is the combination of a first standard integrated circuit with a second custom or semi-custom integrated circuit that has been developed for a particular customer or for a specialized application.
  • Another feature of the invention is the combination of an integrated circuit of one material, such as silicon, with a second device, such as a GaAs solid state laser, that uses a different semiconductor material from that of the first circuit.
  • a second device such as a GaAs solid state laser
  • Figure 1 illustrates the process flow in a system using the subject invention.
  • FIG 2 illustrates the steps in Figure 1 in more detail.
  • FIGS 3A and 3B illustrate integrated circuit chips used in the system of Figure 1.
  • Figures 4A and 4B illustrate alternative embodiments of the invention.
  • Figure 5 illustrates a portion of a leadframe.
  • Figure 6 illustrates a cross section of an integrated circuit suited to the application of the invention.
  • Figure 7 illustrates a method of attaching leads to an integrated circuit suited to the application of the invention.
  • FIG. 1 An overall flow chart of the steps used in the back-end assembly is illustrated in Figure 1, in which a number of steps are illustrated schematically and are performed by a variety of different machines in communication with and sometimes controlled by a computer for storing test and other data.
  • a process that may be part of the "front-end” or the "back-end” accepts as input a wafer that has been completed with all the conventional steps (including passivation - etc.) and applies a further layer of dielectric having a thickness sufficient to protect the chip circuits and to insulate them electrically from signals being carried on the top surface of the dielectric.
  • a pattern of metal leads is formed that extends from the contact pads on the previous chip to a standard array of contact pads on the top of the dielectric.
  • the standard array is the same for all chips having the same number of pins, regardless of the size of the chip die.
  • the wafer is then probe tested, in major step II with the results of the probe test being stored electrically, such as in a computer.
  • the conventional ink-dot marking system for bad chips is not used.
  • the wafer is then adhesively mounted on an adhesive film in a frame holder that is shaped to allow for automatic insertion and orientation in various fixtures further along in the process and cut apart in an automatic sawing process (Step III) that cuts through the entire thickness of the wafer.
  • the good dice are then removed from the wafer in an automatic sequence (Step IV) that presses from above against the tape to selectively pick a die downinto a dedicated carrier where it rests circuit side down. This is not a problem since the active circuitry is protected by the standard pad dielectric and standard pads.
  • the wafer and punch-out device are moved under computer control to put the dice into the correct positions in the carrier.
  • the dice are transferred to a mating carrier simultaneously in an inversion operation that rotates the two-carrier "sandwich" by 180 degrees, so that the dice resting in the second carrier have contacts on the top side.
  • a set of dice are transferred to a bonding fixture that holds a convenient number, illustratively 14 dice. Once loading is complete, a leadframe matching the spacing of the dice in the fixture is positioned above the dice in the soldering fixture and an upper bonding fixture is added to maintain lead to pad contact during the bonding process.
  • the bonding fixture is heated to reflow the solder and form the interconnection (Step V).
  • the leadframe with dice attached is placed in a transfer or injection molding machine that encapsulates the die together with the interconnections to the leadframe (Step VI).
  • the molded strip of devices is then trimmed and formed conventionally (Step VII).
  • Figure 2 sets out the steps in Figure 1 in more detail and also illustrates the material and data flow.
  • a convention used in this figure is that a broken line indicates a material transport step of the sort of loading the material into a container and moving the container to another location and a double arrow indicates data flow into or out of a computer or other storage device.
  • the three material inputs to the process are the wafers, leadframes and plastic for encapsulation.
  • Two recirculation loops involve, respectively, a frame used to support the wafers during the sawing and die selection steps and a positioning fixture used to maintain a set of dice in alignment with a leadframe segment during the bonding operation.
  • the illustrative dielectric layer is a polyimide such as Dupont 2525 applied with the thickness of 6 microns and cured at a temperature of greater than 260 C.
  • a nitride or other layer below the polyimide to improve adhesion to the reflow glass or other top layer.
  • the electrical contact pads that have been previously formed in the integrated circuit chip by conventional processing techniques are exposed by applying a photoresist, either liquid or in the form of a tape, on top of the dielectric and etching down through it a passageway to the metal contact pad in the circuit in a conventional manner.
  • a "via" will be formed by filling the contact holes with a metal or other conductor until the surface of the dielectric is reached.
  • the photoresist is stripped off and a layer of metal is applied by any technique, such as sputtering, over the surface of the polyimide.
  • a layer of metal is applied by any technique, such as sputtering, over the surface of the polyimide.
  • the polyimide was back sputtered to prepare the surface, after which 600 Angstroms of 10% titanium +90% tungsten followed by 3 microns of copper were sputtered on.
  • a second layer of photoresist is applied and patterned to define a set of metal leads in the metal layer.
  • the leads reach from the vias penetrating the dielectric to an area in the center of the chip which has a standard pad array of pad contacts that may advantageously be the same for two or more chips that have the same number of leads.
  • a 16 pin chip will have the same standard pad array, of size about .016" by .016" in a standard configuration having dimensions of .126" by .126", whether it is a memory or any other logic device.
  • the standard pad array will be sized so that it fits on the smallest chip that is to be used with that leadframe.
  • the exposed areas of the metal are plated with a solder composed of a standard mixture of lead and tin in a conventional electrolytic plating process that employs a mixture of 95% tin and 5% lead.
  • the photoresist is stripped and the plated areas of the metal layer are used as an etching mask in the next step in which the remaining unwanted area of the metal layer is etched away in a bath of hydrogen peroxide plus ammonium hydroxide followed by hydrogen peroxide, which does not attack the solder.
  • chip 300 of the form illustrated in Figure 3A in which die 310 has on it a thick layer of polyimide 320 and a network of metal lines 326 leading from the contact areas 330 on the outside of the chip to the standard pad array 340.
  • the metal lines 326 have lower inductance, greater thermal conductivity and greater strength compared to the wires that were previously used.
  • Lines 326 are the second set of conductors in the die, the first set being the metallization and/or polysilicon conductors below the dielectric layer.
  • the first contacts and the vias through the polyimide layer are all formed on the perimeter of the chip.
  • This figure illustrates a chip in which the layout design was made for the old wire-bonding method in which the contact areas had to be on the perimeter of the chip.
  • a via 305 is shown in Figure 3A in a cut-away portion of the figure as extending from a lower contact area 304 to an upper contact 306 at an end of one of leads 326.
  • the lower contact pads in current practice are typically 4 mils by 4 mils.
  • the alignment tolerance for the formation and location of the vias and the placement of leads 326 are typically + 2 mils to 3 mils, which is much greater than a typical tolerance of + 1/2 mil to 1 mil for connecting leads in the precision processes that are used with conventional wirebonding.
  • the steps of forming vias and putting down leads may be performed in the front-end using the standard machines for photolithography, if that is convenient.
  • thick-film technology such as screen printing
  • the thick-film technique will be 1/4 to 1/2 the cost of the precision techniques.
  • FIG. 6 A cross section of a portion of a die is shown in Figure 6, in which substrate 6-100 is the silicon substrate and aperture 6-200 is the "street" that separates adjacent dice.
  • the width of a street is typically 100 microns, to allow room for the saw kerf in the separation step that is performed with a diamond saw having a width of .001 inch.
  • a contact pad, 6-05 is shown with a series of apertures defined above it.
  • Pad 6-05 which is typically aluminum and is connected by metallization strips, not shown, to the rest of the circuit, is surrounded by oxide 6-10, which has a conventional composition of SiO 2 plus phosphorous and other additives and a thickness of 1 micron.
  • Oxide 6-10 has a top surface 6-15 on which polyimide layer 6-50 was, at first, applied directly. Early tests showed significant difficulty, in that polyimide layer 6-50 (layer 320 in Figure 3) often disbonded, causing the leadframe to pull the polyimide away from the underlying layer.
  • Oxide 6-10 functions as the top dielectric layer in the circuit.
  • Nitride layer 6-20 is deposited by plasma-assisted CVD at a temperature of 250 C, in a conventional manner, to a thickness of .3 micron after street 6-200 has been etched through oxide 6-10 to the substrate.
  • a layer of 2525 polyimide from Dupont is applied and spun to produce a relatively flat top surface.
  • Apertures 6-45 above contact 6-05 and 6-55 above street 6-200 are opened through the uncured polyimide by wet etching with a conventional basic solution such as Shipley 312 developer. Typical dimensions for the top of aperture 6-55 and 6-45 are 100 and 87 microns, respectively.
  • aperture 6-40 is opened through nitride layer 6-20 in CF4.
  • a typical dimension of aperture 6-40 is 75 microns, so that aperture 6-40 is surrounded by nitride 6-20 and does not expose any of oxide 6-10.
  • the next major step II is a test with the individual circuit dice still remaining in the wafer.
  • a conventional wafer electrical test step could be performed in which small probes are attached to the contacts that will be used for the input/output and the individual chips are tested.
  • An advantage of this invention is that the metal leads on top of the polyimide cover a much larger area than the old-style contact pads do, so that it is easier to make electrical contact at reduced pressure of the electrical contact probe or electrode with these large metal pads than it is with the small contact pads used in conventional techniques. It is also possible to make electrical contact to the leads before you reach the contact area, thus providing additional flexibility in the probe step.
  • An important economic benefit from the invention is that only a single set of probe tips will be needed to match the standard pad array for the whole family of circuits that have the same number of pins. In the prior art, a different set of probe tips was typically needed for each chip design.
  • the chip has optional electric contact pads outside the standard pad array, as shown by contact 350 in Figure 3B (which is a via formed to provide access to a point in a circuit that is to be tested, yet does not connect to one of the regular contacts), then a different set of probe pins will be needed in that case, of course.
  • wafer mapping In conventional wafer tests, defective chips are marked by a small dot of ink so that, in manual assembly, they can be identified and discarded. In this process, the chips are identified electrically i.e. the wafer is oriented in a particular way and the chips are identified by their locations in an X-Y matrix.
  • the test data for individual chips are stored in the central computer memory or in a floppy disk or other storage medium and defective chips are identified in the computer. This step is referred to in Figure 2 as wafer mapping. If the chip has the feature of redundant or optional circuits that are connected or disconnected by blowing fuses by a laser (as is done in large scale memory arrays), then this step will have been done before the polyimide layer is put down, as is currently being done.
  • the wafers have not been given an identifying label before, it is now necessary to put a label on them in order to maintain the connection between the test data stored in the computer and the wafer the data came from. There are many ways of doing this correlation, of course, and no particular method is required.
  • One preferred method is to put the identification on an identifying label, such as an optical bar code, that identifies the wafer.
  • Another method is to form a programmable memory in the wafer in which the identities of defective chips may be stored. In that case, the wafer carries with it the necessary information so that there is no problem of getting the wafer separted from the test results.
  • Step V in Figure 1 and Leadframe Fixture Assemble, Bond, Disassemble in Figure 2 is shown in an exploded view in Figure 7, in which holder 7-110, represented schematically, holds 14 chips with the correct spacing, only two of the receptacles 7-225 being shown. Above receptacle 7-225, there is positioned chip 7-230 and, above the chip, a set of finger contacts 5-122 in leadframe 5-100, part of leadframe strip 5-125. The details of the leadframe will be described below. Cover 7-120 presses down on edge 5-110 of leadframe strip 5-125, which edges rest on shelves 7-112 to position the outer parts of the strip so that the contact tips will be deflected slightly.
  • This deflection is done to compensate for inevitable fluctuations in the position of the tips during the manufacturing process, so that reliable contact is ensured during the bonding operation.
  • the deflection is effected by making the depth of receptacle 7-225 such that the top of chip 7-230 projects above the plane of shelves 7-112 by a set amount.
  • the amount of deflection, (.005 inch to .007 inch) is illustratively several standard deviations of the nominal fluctuation of the tip position to ensure reliable joint formation.
  • the edges 5-110 of leadframe strip 5-125 will be forced on to shelves 7-112 by cover 7-120 and tips 5-122 will thus be pressed against the pads by the spring constant of the leads.
  • a typical leadframe used in the invention is illustrated in Figure 5, in which half of an individual frame is shown.
  • the individual leadframes are stamped out of a ribbon of metal that may be an inexpensive copper alloy, in contrast to the expensive alloy having the correct thermal properties that is used in the standard prior art process.
  • Strips 5-110 on either side of the ribbon serve to carry the actual leads 5-120 along.
  • Leads 5-120 have an exterior end 5-123, shaped either for insertion in a socket or for surface-mounting, and an interior portion 5-121 for attachment to a die. The two portions are joined by segments 5-124 that will be severed after the bonding step.
  • Holes 5-112 are provided to give a reference in positioning the leadframe.
  • each lead segment 5-121 there is a region, 5-122, in which the lead is bent in a quarter circle (or bent twice to form a parallel contact section) to form a standard dimension flat contact area.
  • Each of the different lead segments 5-121 has been shaped to provide substantially the same spring constant so that the contact areas 5-122 will be uniformly pressed against the mating pads on the die to give correct alignment for the soldering operation.
  • the leads 5-120 have been tinned with solder in a previous step in the fabrication of the lead frame ribbon. It is an advantageous feature of the system, but not an essential one, that a family of chips that have the same number of pins have the same standard pad array on top of the dielectric.
  • the soldering assembly of holders 7-110 and 7-120, with chips plus leadframe maintained in alignment, is inserted into a container or oven that is filled with the vapor at the boiling-point temperature and held there until the solder has melted and flowed to form a bond.
  • a typical length of time for the heating cycle is 5 to 15 seconds.
  • This boiling point temperature is typically above 225 degrees C but below 300 degrees C.
  • the present wire bonding and die attach steps are performed at temperatures of up to 460 degrees C and performed individually.
  • the bonding fixture should have low mass and many apertures to permit the vapor to flow freely about the solder joints.
  • Holders 7-110 and 7-120 have been shown schematically in order to reduce the complexity of the drawing.
  • An important economic benefit of this invention is that all the leads are soldered at the same time. This is in contrast to the wire-bonding technique, in which the leads must be bonded one by one. The soldering step takes no longer for a 28 pin chip than it does for a 16 pin chip.
  • Step VII in Figure 1 leadframe 5-100, with 14 chips attached, is placed into a transfer or injection molding machine to mold plastic about it, thus encapsulating and protecting the chip in a dielectric shell.
  • the molding process will be done using conventional techniques and equipment. Any other method of protecting the chips may be used, such as ceramic holders. It is an advantageous feature of this invention that the wide contact area between the leadframe and the contact pads is extremely rugged compared to the wire bonding technique that is in standard use so that a far smaller fraction of chips will be damaged during handling and the chips can be moved about at a greater rate and with less delicacy required. It is a further advantage that the leads conduct heat away from the chip during operation.
  • the optional labelling step of Figure 2 is performed.
  • the dice identity first appeared during probe test. when data were measured that applied to an individual die. That identity was preserved by the labels on the wafer, tape frame and leadframe, the computer being updated as required to log the die identity on the leadframe.
  • Each chip may be marked by a laser branding process or any other convenient technique with an identifying label, test results, etc.
  • step VIII of Figure 1 the chip plus leadframe combination is separated from the ribbon and the spacing segments 5-124 that served to maintain the leads in correct alignment are severed. If the ribbon is formed from a sheet of copper or copper alloy, it is necessary to sever the connections 5-124 or else all the leads will be shorted together. If another version of the ribbon is used, in which a plastic backing is used for the portion 5-110 and to support leads 5-120, on top of which a plated copper lead has been formed, then it will be easy to maintain the sections 5-124 in plastic and it is not necessary to separate the leads.
  • Figure 4A shows a die having the same substrate 310 and polyimide 320 as before, but in which the pad array comprises two rows 350 illustratively of eight pads each, set toward the outside of the chip.
  • bus 353 which distributes the power supply voltage to various points in the circuit, one of which is a via indicated by the numeral 352 and positioned at one of the array positions to make contact with a lead.
  • bus 353 offers considerably less resistance and inductance.
  • bus 354 makes contact with pad 351 and distributes the ground terminal about the die.
  • a further advantage of the sturdy polyimide layer 320 is that discrete electrical devices, active or passive, may be placed on top of layer 320 and connected to the circuit, either by vias or to the standard pads.
  • device 368 is shown as being connected to vias 370 and 369.
  • the device may be a thick-film resistor having a large magnitude (that is difficult to achieve with conventional integrated circuit techniques).
  • Thick-film resistors, capacitors and inductors are conventionally formed by silk-screen techniques on printed circuit boards.
  • the capacitors require a three-layer "sandwich" of two conductors and an insulator.
  • the vehicle for carrying the conductor may be a conductive ink, epoxy or polymerizable material, or any other conventional technique.
  • top electrical device will mean any thing from a conductor to an integrated circuit that is placed on top of layer 320.
  • a capacitor is shown as unit 355, a charge reserve capacitor connected between the power supply and ground using a conductive adhesive at point 367 and to strap 366.
  • Such capacitors are conventionally attached to integrated-circuit sockets to maintain a stable supply voltage when circuits switch. The economic advantages of including the capacitor with the chip are evident.
  • a device such as unit 355 may be connected to any point in the circuit, of course.
  • device 355 that is an optical or other element that is difficult to fabricate on the same substrate .
  • device 355 could be a solid-state laser using a gallium arsenide substrate and die 310 could be a conventional silicon integrated circuit. In that case, a fiber-optic pigtail would be included for communication to other optical devices.
  • Other devices that may be readily implemented are an R-C timing network, either fixed or having an adjustable element for which an access hole is formed in the encapsulating plastic; or a power transistor using the area of device 355 to spread the heat load.
  • Heat sinks may also be attached directly to layer 320 or to vias that provide a low impedance thermal conduction path from high-power sections of substrate 310.
  • These other devices may be attached in any convenient manner. They may be adhesively attached before or after the soldering of the leadframe (or they may be soldered and the leadframe adhesively attached). Alternatively, soldering or gluing of leadframe and discrete devices may be done simultaneously, with the leadframe maintained in position prior to bonding by an adhesive.
  • Figure 4B illustrates another variation of the invention that offers considerable reduction in inventory.
  • a two-chip assembly comprising a first chip 300' having substrate 310, polyimide 320 and surface pads as before, and a second chip 380 comprising substrate 310', polyimide 320' and array of contacts 382' that mate with an array of contacts 382 on layer 320.
  • An alternate U-shaped contact array 350' is shown, which has the advantage of freeing up half of layer 320 for chip 380. In order to bring all the leads over to one half of chip 300', it may be necessary to permit some variation in the spring constant of the leads.
  • Chip 380 may connect directly to the leads for input/output, of course. In the case illustrated, chip 380 is a ROM that needs only power supply and ground and communicates only with the larger chip through vias in array 382 or through surface leads, such as lead 373.
  • a multi-purpose chip such as a single-chip microcomputer that is customized by adding a ROM. If the ROM is a mask option, then there must be a reserve supply of customized microcomputers to allow for fluctuations in the yield, or rush orders and the manufacturer must maintain an inventory of chips that are good only for one customer. With the embodiment of Figure 3D, however, the inventory for each customer need only be his ROMs, which are much cheaper than microcomputers.
  • the manufacturer will maintain a reserve of microcomputer chips sufficient to meet the needs of all his customers, of course. It is evident that the total value of inventory will be less with a central reserve, simply because of the laws of statistics.
  • a variation of the two-chip system is that in which the main chip 302 is a generalized system, such as an input controller and the second chip 380 is one of a number of alternatives, each customized for a particular application.
  • the main chip might be a 5-volt logic chip and chip 380 might be designed to withstand the high voltages of the telephone network in a telephone interface such as a modem or coder.
  • One convenient method of attaching chip 380 is to form pads 382' with a sufficient amount of high temperature solder to make reliable contact and to reflow that bond before bonding the leads at a lower temperature.
  • Another method is to adhesively attach chip 380 in alignment and to solder both sets of contacts simultaneously.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Un dispositif à circuit intégré comporte un circuit intégré conventionnel (310) modifié par l'addition d'une couche diélectrique (320) au-dessus de laquelle se trouve un réseau de conducteurs (353, 354), ainsi qu'un ou plusieurs composants ou dispositifs électriques actifs ou passifs (368) connectés entre les conducteurs supérieurs.
EP85901777A 1984-03-22 1985-03-19 Composants additionnels de circuit integre Withdrawn EP0177560A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59216984A 1984-03-22 1984-03-22
US592169 1984-03-22

Publications (1)

Publication Number Publication Date
EP0177560A1 true EP0177560A1 (fr) 1986-04-16

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ID=24369595

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85901777A Withdrawn EP0177560A1 (fr) 1984-03-22 1985-03-19 Composants additionnels de circuit integre

Country Status (4)

Country Link
EP (1) EP0177560A1 (fr)
JP (1) JPS61501533A (fr)
KR (1) KR860700077A (fr)
WO (1) WO1985004521A1 (fr)

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Publication number Priority date Publication date Assignee Title
FR2720190B1 (fr) * 1994-05-20 1996-08-02 Matra Marconi Space France Procédé de raccordement des plages de sortie d'une puce à circuit intégré, et module multipuces ainsi obtenu.
JP2003504746A (ja) 1999-07-13 2003-02-04 エムブイ・リサーチ・リミテッド 回路製造方法
GB2407394A (en) * 2003-10-23 2005-04-27 Dow Corning Ltd Optical waveguide with two differently dimensioned waveguiding layers on substrate

Family Cites Families (5)

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Publication number Priority date Publication date Assignee Title
US3386008A (en) * 1964-08-31 1968-05-28 Cts Corp Integrated circuit
US3614554A (en) * 1968-10-24 1971-10-19 Texas Instruments Inc Miniaturized thin film inductors for use in integrated circuits
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
US3947840A (en) * 1974-08-16 1976-03-30 Monsanto Company Integrated semiconductor light-emitting display array
US4371912A (en) * 1980-10-01 1983-02-01 Motorola, Inc. Method of mounting interrelated components

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8504521A1 *

Also Published As

Publication number Publication date
WO1985004521A1 (fr) 1985-10-10
JPS61501533A (ja) 1986-07-24
KR860700077A (ko) 1986-01-31

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