GB2219435A - "Plastics encapsulated multichip hybrid circuit" - Google Patents

"Plastics encapsulated multichip hybrid circuit" Download PDF

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Publication number
GB2219435A
GB2219435A GB8911054A GB8911054A GB2219435A GB 2219435 A GB2219435 A GB 2219435A GB 8911054 A GB8911054 A GB 8911054A GB 8911054 A GB8911054 A GB 8911054A GB 2219435 A GB2219435 A GB 2219435A
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United Kingdom
Prior art keywords
integrated circuit
lead frame
flag
bonding
chip
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Granted
Application number
GB8911054A
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GB8911054D0 (en
GB2219435B (en
Inventor
Larry D Hobson
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Texas Instruments Tucson Corp
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Burr Brown Corp
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Publication of GB2219435B publication Critical patent/GB2219435B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

PLASTIC ENCAPgULATED MULTICHIP HYBRID INTEGRATED CIRCUIT 2219435
BACKGROUND OF THE INVENTION
The invention relates'to plastic encapsulated multichip hybrid integratea circuit structures, particularly those suitable for a combination of high power chips and low power chips.
Hybrid integrated circuits have been widely manufactured for many years to provide, in a single package, electronic devices that are too complex to be economically integrated, on a single monolithic semiconductor chip. In hybrid integrated circuits, 0 various monolithic integrated circuit chips, capacitors, film resistors, and other components are die bonded, deposited, or otherwise attached to a ceramic substrate. The ceramic substrate has thereon a suitable metal interconnection pattern including "flag" areas (onto which integrated circuit chips and other 5. components are bonded) and also including metal interconnect strips ("interconnects") to which bonding pads of the various components are electrically connected by wire bonding techniques. Multiple integrated circuit chips have been provided by bonding them to a metalization pattern on a thin insulating layer formed !0 as part of a flexible ribbon substrate attached to a conventional lead frame. Bonding pads of the various integrated circuit chips and other components have been wire bonded to metal strips or _.,interconnects on the insulating layer and to f ingers of the lead --.-frame. The. assembly has -been encapsulated in plastic by a plastic transfer molding process. This technique is disclosed in Japanese Patent Public Disclosure No. 60-41249, dated March 4,
1985, assigned to NIPPON DENKI K.. K. The technology disclosed in that reference is subject to the limitation that the integrated -circuit chips therein must dissipate only relatively low amounts of power. This is necessary because flexible ribbon-type materials that are good electrical insulators are relatively poor 0 thermal conductors. Since the etched copper technology requires gold electroplated interconnects, widespread use of vias and connections of the vias to inner, isolated interconhects is necessary to provide connection of isolated interconnects to a "Plating bus". These vias and connections thereto add expense, and also degrade electrical performance_ An example of a hybrid integrated circuit that would be very difficult to provide in a plastic package using the prior technology disclosed in Japanese Patent Public Disclosure No. 60-41249 is a digital to analog converter including a relatively :0 low power CMOS integrated circuit chip containing digital logic circuitry and switching circuitry and a relatively high power bipolar integrated circuit chip containing an analog amplifier -"and bit current switch circuits. Up to now, such a hybrid integrated circuit digital to analog converter encapsulated in !5 plastic could be provided only by die bonding both the CMOS chip 2 -Y and the bipolar chip onto a multilayer polymer film substrate attached to.a lead frame.
z , -. 1 J, 3 )SUMMARY OF THE iNVENTION
Accordingly, it is an object of the invention to provide a low cost plastic encapsulated hybrid integrated circuit containing high power semiconductpr chips.
It is another object of the invention to provide a low cost plastic encapsulated hybrid integrated circuit containing both high power and low power.,monolithic integrated-circuit chips.
It is another object of the invention to provide a technique for manufacturing a low cost plastic encapsulated liybrid 0 integrated circuit containing multiple chips with different back voltages.
Briefly described, and in accordance with one embodiment thereof, the invention provides a hybrid integrated circuit including an insulative film bonded to a first area of a lead frame flag, a second area of the lead frame flag being exposed.
A plurality of individual metalized strips or interconnects are formed on the insulative film. A first chip is bonded directly to the second area of the lead frame flag. Bonding wires are bonded to electrically connect the first chip to various 0 7metalized strips. Other- bonding -wires- are bonded-to connect the metalized strips to various fingers of the lead frame. The first chip, the bonding wires, the lead frame flag, the lead frame 4 z tjfingers, and the #sulative film all are encapsulated in plastic formed by transfer molding. In a described embodiment of the invention, an isolated flag area is included in the metalized pattern formed on the insulative film. A second chip is bonded to the isolated flag area,,and bopding pads of the second integrated circuit chip are connected by bonding wires to various metalized strips, which are connected by other wire bonds to the fingers of the lead frame or to various bonding pads of the first chip. A plating bus is formed on the insulative film and is .0 connected to the individual metalized strips and the isolated flag. Initially, a metal layer pattern including the individual bonding strips and the isolated flag are composed 6f copper foil backing adherent to the insulative film. Gold is electroplated onto the copper while applying an electroplating voltage to the plating bus. The piece of the film to -be bonded to the first area of the lead frame flag is punched out of a larger piece of film so that none of the plating bus is on the punched out film, but the metalized strips or interconnects and the first flag area are on the punched out piece.
_RIEF DESCRIPTION OF THE-DRAWINGS
Fig. 1 is a partial plan view of the hybrid integrated circuit of the present invention prior to plastic encapsulation.
Fig. 2 is a plan view of a lead frame utilized in manufacture of the hybrid integrated circuit shown in Fig. 1.
Fig. 3 is a partial plan view-of a flexibl-e insulative ribbon tape from which a plurality of the insulative film substrates, with separate gold plated metal areas formed thereon, are subsequently punched.
0 Fig. 4 is a section view of the device in Fig. 1 after plastic encapsulation._ Fig. 5 is a partial perspective exploded view of the hybrid integrated circuit of Fig. 1.
6 P, (DETAILED DESCRIPTION OF. THE PREFERRED EMBODIMENTS
Referring now to Figs. 1, 2, 4, and 5, immediately prior to plastic encapsulation (by well known transfer molding operations), hybrid integrated circuit I includes a lead frame generally designated to by reference numeral 2 having a plurality -of coplanar fingers such as 2-1, 2-2, 2-3, 2-4, 2-5, and 2-7.
Each of the fingers is connected to a respective lead 2A. In the final structure, the temporary lead-to-lead shorting bars 10 (referred to as "dam bars"), are severed as the individual lead 0 frames are punched out of the lead frame ribbon structure (Fig. 2), in accordance with conventional practice.
Two coplanar tie bars 2-5 and 2-6 support a thermally conductive lead frame flag 3, as best seen in Fig. 5. Lead frame flag 3 is spaced from the inner ends of all of the lead frame fingers 2-1, 2-1, etc. A direct connection such as 2-8 from a lead frame finger to lead frame flag 3 may be provided to apply a back voltage, as shown in Figs. 1 and 5.
As best seen in Fig. 5, a thin 5.5 mil thick layer of glass epoxy film material formed as an L-shaped insulative substrate 5 0 is directly bonded to the upper surface of lead frame flag 3 by means of a pre-attached epoxy preform.15-3. The glass epoxy f ilm can be FR4 material, available with separate gold plated copper foil strips on the upper surface according to the user's 7 k-- Yspecifications, manufactured by IBIDEN Co., Ltd., 300 AOYANAGICHO, OGAKIi GIFU 503j JAPAN,, and available from IBIDEN USA CORP.,' of 2727 Walch Avenue, #203, Santa Clara, California. IBIDEN also will supply such glass epoxy film with a "B" staged epoxy material attached thereto,_po a preattached preform is already on the substrate 5 when it is punched out of the glass epoxy film.
The gold plated pattern of metal strips on insulative -substrate 5 includes a p).urality of spaced individual metal interconnects such as 6-1,6-2, 6-3, etc. A relatively large area gold plated conductive "isolated flag" 7 thereon is connected to a wire bonding strip 7-1, to apply a back voltage to an integrated circuit chip thereon.
An integrated circuit chip 8 is die bonded to the upper surface of isolated flag 7. Integrated circuit chip 8 needs to have sufficiently low power dissipation that its heat can be adequately conducted away from chip 8 through the glass epoxy substrate 5 to the lead frame flag 3. Various bonding pads on integrated circuit chip 8 are wire bonded by means of gold bonding wires to various individual interconnects on glass epoxy substrate 5 or directly to the f ingers of lead frame 2. For example, bonding pad 9-1 is connected by gold bonding- wire 16-5 to gold plated interconnect 6-1. which in turn is bonded by gold wire 16-1 to lead frame finger 2-1. Similarly, bonding pad 9-2 is bonded by a gold bonding wire to interconnect 6-2.
8 xnterconnect 6-2 i.s connected by gold bonding wire 16-2 to lead finger 2- 2.
In accordance with the present invention, glass epoxy - _substrate 5 has one or more.rectapgular "cutouts" which expose a -silver plated upper surface of lead'frame flag 3. In Fig. 1, the - rectangular cutout bounded by edges 15-1 and 15-2 of glass epoxy substrate 5 exposes rectangular area 3A of lead frame flag 3.
Another integrated circuit chip 13 is directly die bonded to the exposed surface area 3A of lead frame flag 3. ordinarily, chip 13 might dissipate much more power than integrated circuit chip 8, and therefore needs direct, low thermal resistance contact with the lead frame flag 3A in order to remove dissipated heat at an adequate rate to prevent excessive temperature buildup in integrated circuit chip 13. Various bonding pads 14-1, 14-3, etc., of integrated circuit chip 13 are wire bonded, using gold bonding wires, to various individual interconnects such as 12-1 and 11-1. Also, some bonding pads such as 14 -2 of chip 13 are wire bonded directly to lead frame fingers such as 27.
In Fig. 1,, which is drawn essentially to scale, chip 8 is a 0 very low power 80 rail by 140 nil CMOS chip, and integrated circuit chip 13 is a relatively high power bipolar 86 nil by 140 mil chip. 1.0 to 1.3 rail gold wire bonds are utilized.- The conductive gold plated strips such as 6.1. 6-2, etc., and 11-1 -71 _.and gold plated flag 7 are one ounce (1-4 mil) 25 micron minimum -:gold plated copper. The upper surface of the lead frame flag 3 is silver plated. The lead frame is 10 mils thick.
After all of the wire bonds liave been completed, plastic 5 encapsulation 22, shown in Fig. 4, is provided using a -conventional transfer molding process. The gold bonding wires are sufficiently ductile and sufficiently short that they reliably resist forces pKoduced thereon by flow of the melted plastic during the transfer molding process.
0 The matrix of lead frames shown in Fig. 2 is entirely conventional, and need not be described further. In Fig. 3, the flexible glass epoxy "tape" in ribbon 20 has a plurality of sprocket holes 20-1 along the edges, so "tape" 20 can be formed into a roll and advanced by a spool in an automated process. The -5 tape 20 is entirely formed of the copper clad glass epoxy material referred to above, and the individual glass epoxy insulative substrates 5 are punched out of the tape. Although not shown in Fig. 3, the pattern of individual gold plated strips 6-11 6-2, gold plated flag 7, and the gold plated strips 12-1, !0 etc., is repeated on each of the insulative substrates 5. The outline of each of insulative substrates 5 in Fig. 3 indicates the'-lines along which a conventional punch machine-separates those insulative substrates 5 from the film 20, severing the shorting bars 17-1.
Numerals 20-2 designate 3 vertical elongated gold plated "plating busses". A plurality of the horizontal lines such as 20-3 interconnect the vertical plating busses. All of the interconnects on the upper surfacp of insulative substrates 5 are connected by shorting bars 17-1 to the plating bus composed of lines 20-2 and lines 20-3 in Fig. 3 until they are severed as the individual insulative substrates are punched out of the film tape 20. This structure allows the plating bus to be easily connected to a suitable electric potential to effectuate electric plating of gold onto all of the copper foil pattern initially etched on the copper foil backed surface of the glass epoxy film 20.
Although the insulative substrate 5 in the above described embodiment of the invention is L-shaped, the cutouts can be within the insulative substrate 5, as shown in the section of film 20 at the top of Fig. 3, wherein several rectangular cutouts 15A and 15B are provided in each of the insulative substrates 5A to be punched out of the film 20. Round;cutouts also could be punched into the insulative substrates to allow wire bonding to the lead frame flag, if desired. The cutouts 15A and 15B expose !0 areas of the lead frame flag 3 large enough to allow components such as integrated circuit chips or other components to be directly die bonded to the exposed surface of lead frame flag 3.
It should be appreciated that in some instances, where the - 4A.
n7 C V.substrates of varkous integrated circuit chips may need to be _-maintained at different voltages, it may be desirable to attach low power chips to the conductive flags such as 7 on the insulative substrates 5 and attach other low power chips directly '-to the exposed areas of the.lead frame flag 3, thereby avoiding difficult routing of power supply busses on the upper surface of -the insulative substrates 5.
Multilayer metalization may be provided on the glass epoxy substrate. Of course, high or low power discrete and/or 0 integrated chips manufactured using various technologies can be die bonded to metal flags such as 7 on the insulative film and/or to exposed areas of the lead frame flag. The lead frame may be split into several separate lead frame flags, each electrically connected to a different lead frame finger, to allow different back voltages to be applied to separate chips respectively die bonded thereto.
-- 12

Claims (6)

CWHAT IS CLAIMED IS: I I.
1. A hybrid integrated circuit comprising in combination:
2 (a) a plurality.of lead frame fingers and a lead frame 3 flag surrounded by the fingers;- 4 (b) an insulative film adhesively attached to a _surface of the lead frame flag, a cutout in the film exposing an 6 area of the lead frame flag surface, a plurality of metalized 7 areas on the insulative film including a metalized first flag, 8 and a plurality of individual metalized bonding stiips; (c) a first integrated circuit chip die bonded to the 0 first flag, and a second integrated circuit chip die bonded to 1 the exposed area; 2 (d) a plurality of bonding wires each connected 3 between a bonding pad of one of the first and second integrated.4 circuit chips and one of the bonding strips, respectively; (e) plastic encapsulation filling a volume containing 6 the fingers, the lead frame flag, the first and second integrated.7 --- circuit chips, the metalized areas, and the bonding wires.
13 1
2. The hybrd integrated circuit of Claim 1 wherein the 2 second integrated circuit chip dissipates more power than could 3 be thermally conducted through the film if the second integrated 4 circuit chip were die bonded to the film.
1
3. The hybrid integrated circuit of Claim 2 wherein the 2 film is composed of glass epoxy material.
1
4. The hybrid integrated circuit of Claim 2 wherein the 2 metalized areas are composed of gold plated copper'foil material.
1
5. The hybrid integrated circuit-of Claim 2 wherein the 2 first integrated circuit chip is an MOS integrated circuit and 3 the second integrated circuit is a bipolar integrated circuit.
1
6. A hybrid integrated circuit comprising in combination:
2 (a) a plurality of lead frame fingers and a lead frame 3 flag surrounded by the fingers; 4 (b) an insulative film attached to a first area of the surface of the lead frame flag, a second area of the lead frame 14 41 6 surface being exposed, a plurality of metalized areas on the 7 insulative film including a plurality of individual metalized 8 bonding strips; 9 (c) a chip die bonded to the second area; 0 (d) a plurality of bonding wires each connected 1 between a bonding pad of the chip and one of the bonding strips, 2 respectively; 3 (e) plastic encapsulation filling a volume containing 4 the fingers, the lead frane flag, the chip, the miCalized areas, and the bonding wires.
is Published l9a9 atThe Patent Offloe, State Home, 66/71 High HoIborn,LDndon WClR4TP. PUrther copies maybe obtained from The Patent Office. Sales Branch, St Mary Cray, Orpington, Kent BF.5 3RD. Printed by Multiplex techmiques ltd, St Mary Cray, Kent, Con. 1187
GB8911054A 1988-06-02 1989-05-15 Plastic encapsulated multichip hybrid integrated circuit Expired - Fee Related GB2219435B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US20158988A 1988-06-02 1988-06-02

Publications (3)

Publication Number Publication Date
GB8911054D0 GB8911054D0 (en) 1989-06-28
GB2219435A true GB2219435A (en) 1989-12-06
GB2219435B GB2219435B (en) 1991-07-03

Family

ID=22746444

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8911054A Expired - Fee Related GB2219435B (en) 1988-06-02 1989-05-15 Plastic encapsulated multichip hybrid integrated circuit

Country Status (5)

Country Link
JP (1) JPH0712071B2 (en)
KR (1) KR970005724B1 (en)
DE (1) DE3916980A1 (en)
FR (1) FR2632454A1 (en)
GB (1) GB2219435B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0381054A2 (en) * 1989-01-30 1990-08-08 Kabushiki Kaisha Toshiba Semiconductor device package
EP0498446A2 (en) * 1991-02-08 1992-08-12 Kabushiki Kaisha Toshiba Multichip packaged semiconductor device and method for manufacturing the same
EP0506122A2 (en) * 1991-03-29 1992-09-30 Matsushita Electric Industrial Co., Ltd. Power module
US5491360A (en) * 1994-12-28 1996-02-13 National Semiconductor Corporation Electronic package for isolated circuits
EP3002784A1 (en) * 2014-09-30 2016-04-06 Renesas Electronics Corporation Semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7625286B2 (en) 2004-05-06 2009-12-01 Sony Computer Entertainment Inc. Electronic device and a game controller
DE102005014746A1 (en) 2005-03-31 2006-10-05 Friwo Mobile Power Gmbh Active primary-side circuit arrangement for a switching power supply
DE102006033175A1 (en) * 2006-07-18 2008-01-24 Robert Bosch Gmbh electronics assembly

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0015053A1 (en) * 1979-01-27 1980-09-03 LUCAS INDUSTRIES public limited company A method of manufacturing a semi-conductor power device assembly and an assembly thereby produced
JPS6041249A (en) * 1983-08-17 1985-03-04 Nec Corp Hybrid integrated circuit device
JPS60207358A (en) * 1984-03-30 1985-10-18 Nec Kansai Ltd Hybrid ic
JPS6292653U (en) * 1985-11-29 1987-06-13

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0381054A2 (en) * 1989-01-30 1990-08-08 Kabushiki Kaisha Toshiba Semiconductor device package
EP0381054A3 (en) * 1989-01-30 1993-03-31 Kabushiki Kaisha Toshiba Semiconductor device package
EP0498446A2 (en) * 1991-02-08 1992-08-12 Kabushiki Kaisha Toshiba Multichip packaged semiconductor device and method for manufacturing the same
EP0498446A3 (en) * 1991-02-08 1993-10-20 Toshiba Kk Multichip packaged semiconductor device and method for manufacturing the same
EP0506122A2 (en) * 1991-03-29 1992-09-30 Matsushita Electric Industrial Co., Ltd. Power module
EP0506122A3 (en) * 1991-03-29 1994-09-14 Matsushita Electric Ind Co Ltd Power module
US5491360A (en) * 1994-12-28 1996-02-13 National Semiconductor Corporation Electronic package for isolated circuits
EP3002784A1 (en) * 2014-09-30 2016-04-06 Renesas Electronics Corporation Semiconductor device
US9530721B2 (en) 2014-09-30 2016-12-27 Renesas Electronics Corporation Semiconductor device
TWI670805B (en) * 2014-09-30 2019-09-01 日商瑞薩電子股份有限公司 Semiconductor device

Also Published As

Publication number Publication date
DE3916980A1 (en) 1989-12-14
FR2632454A1 (en) 1989-12-08
GB8911054D0 (en) 1989-06-28
KR900001004A (en) 1990-01-31
JPH0232558A (en) 1990-02-02
KR970005724B1 (en) 1997-04-19
JPH0712071B2 (en) 1995-02-08
GB2219435B (en) 1991-07-03

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Effective date: 19950515